JP2002094053A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device in which, related to an MOS field effect transistor comprising a gate sidewall structure, a source/drain diffusion layer is formed very thin to suppress short- channel effect. SOLUTION: After a gate electrode 92 and a gate sidewall 101 are formed, an ion is vertically implanted into a substrate 81 to form a deep source/drain diffusion layer 112. Then a high-temperature or extended first thermal process is carried out for activation. Then ions are implanted obliquely into the substrate 81, to form a shallow source/drain diffusion layer 131 under the gate sidewall 101. A second thermal process is carried out at a temperature lower than the first thermal process for a short period to cause the source/drain diffusion layer 131 to be activated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art At present, in an integrated circuit including a field effect transistor, fine processing of the field effect transistor is being promoted in order to achieve higher integration. As a field effect transistor, in particular, a MOS field effect transistor using a silicon oxide film as a gate insulating film, a transistor having a gate length of less than 100 nm has been researched and developed. In such a MOS field effect transistor, when the gate length is less than 100 nm, a problem called a short channel effect comes to be seen.

One of the short channel effects of a MOS field effect transistor is deterioration of an element due to hot carriers. This is because the electric field concentrates on the channel side of the drain region due to the miniaturization of the gate length,
This is a phenomenon in which hot carriers are generated in this portion, causing deterioration of device characteristics.

As a means for suppressing the deterioration of the device due to the hot carriers, an LDD (Lightly D
Opined Drain) has been devised. This LDD structure has a lower impurity concentration than the source region and the drain region, a shallower junction, and a region of the same conductivity type as the source and drain regions (hereinafter referred to as an LDD region) on the channel side of the source and drain regions. Write)
Has the effect of weakening the electric field strength at the interface between the channel region and the drain region and suppressing the generation of hot carriers.

A conventional method of manufacturing a MOS transistor having this LDD structure (Japanese Patent Laid-Open No. 7-29797).
Will be described below with reference to the drawings.

First, as shown in FIG. 18, a P-type well 12 and an N-type well 13 are formed on a silicon single crystal substrate 11, and element isolation regions 14, 15, 16 made of a field oxide film are formed by using a LOCOS method. Is formed and partitioned into an NMOS formation region and a PMOS formation region.

Next, as shown in FIG. 19, boron is ion-implanted individually or separately into the NMOS formation region and the PMOS formation region in order to adjust the threshold voltage. As a result, thin channel implantation regions 21 and 22 are formed in the P-type well 12 and the N-type well 13.

Next, as shown in FIG. 20, a gate oxide film 31 is formed on the channel injection regions 21 and 22 by a thermal oxidation method. Next, polysilicon containing, for example, phosphorus as an N-type impurity is formed on the gate oxide film 31 and is patterned by anisotropic etching to form the gate electrode 32 on the P well 12 and the N well 13. Form on top.

Next, as shown in FIG. 21, a silicon oxide film having a thickness of 50 nm to 150 nm is formed on the entire surface of the silicon substrate 1 by a chemical vapor deposition method (CVD method). The gate side wall insulating film 41 is formed on the side surface of the gate electrode 32 by etching back by anisotropic etching.

Next, as shown in FIG. 22, a photoresist 51 is formed in the NMOS formation region, and using this photoresist 51 as a mask, boron is obliquely ion-implanted into the PMOS formation region to form a source-source in the PMOS field effect transistor. The LDD structure of the drain region is formed by a thin P-type impurity layer 52 (LDD region). At this time, the implantation angle of boron is 30 ° to 45 °. As described above, since the implantation angle of boron is oblique to the silicon substrate 1, a P-type impurity layer is also formed below the gate sidewall insulating layer 41.

Next, as shown in FIG. 23, using the same photoresist layer 51 as a mask, boron difluoride is ion-implanted into a PMOS formation region to form a P-type impurity layer 61 having a deep LDD structure in the PMOS field effect transistor. To form At this time, the implantation angle of boron difluoride is almost vertical. Then, the photoresist 51 is removed.

Next, as shown in FIG. 24, the NMOS formation region 12 similarly forms an LDD structure to form a CMOS field effect transistor. At this time, NMOS
Arsenic is obliquely ion-implanted into the LDD region 53 of FIG.
Arsenic is ion-implanted substantially perpendicularly to the N-type impurity layer 62 in the MOS region.

Finally, after all ion implantation steps are completed, the impurities in the LDD regions 52 and 53 and the impurity layers 61 and 62 are simultaneously activated by a single heat treatment.

[0014]

As described above, the conventional method of manufacturing a field-effect transistor having an LDD structure uses the LDD regions 52 and 53 and the heavy impurity regions 61 and 62.
Are simultaneously activated by one heat treatment step,
A drain region is formed. However, as the gate length becomes shorter, the impurity concentration of the source-drain region cannot be prevented unless the impurity concentration in the source-drain region is increased even in the LDD region. For this purpose, a heat treatment step at a high temperature of 1000 ° C. or more or a long time is required.

However, in the conventional method of manufacturing the LDD structure, since the LDD region and the deep source-drain region are simultaneously heat-treated, impurities in the LDD region which originally requires a shallow junction are not removed from the silicon substrate during the high-temperature heat treatment process. And the short channel effect cannot be suppressed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a method of manufacturing a semiconductor device in which a junction interface of an LDD region is sufficiently shallow even if a gate length is shortened and a short channel effect does not occur. And

[0017]

In order to achieve the above object, the present invention provides a method of forming a gate insulating film on a semiconductor substrate, a step of forming a gate electrode on the gate insulating film, Forming a gate side wall on a side surface of an electrode; a first ion implantation step of performing ion implantation to form an ion implantation region in the semiconductor substrate other than below the gate electrode and below the gate side wall; A first heat treatment step of activating the semiconductor region to form a source region and a drain region in the semiconductor substrate, and ion-implanting the semiconductor substrate obliquely from above to thereby form the source region and the source region below the gate sidewall. A second ion implantation step for forming an ion implantation region shallower than the drain region; and a second heat treatment step for activating the shallow ion implantation region. To provide a method of manufacturing a semiconductor device according to claim Rukoto.

According to the present invention, the gate electrode is formed of polycrystalline silicon, and ions are simultaneously implanted into the gate electrode at the time of the first ion implantation step. Preferably, the ions implanted into the gate electrode are activated.

Thus, the gate electrode can be ion-implanted at the same time as the first ion implantation step, and the gate electrode can be activated at the time of the heat treatment for activating the source and drain regions, so that the steps can be simplified.

Further, the second heat treatment step includes the first heat treatment step.
It is preferable that the heat treatment temperature is lower than that of the heat treatment step.

Further, the second heat treatment step includes the step of:
It is preferable that the heat treatment time is shorter than that of the heat treatment step.

By performing the second heat treatment step at a lower temperature or for a shorter time than the first heat treatment step, diffusion of the ion implantation region formed by the second ion implantation step can be prevented. It becomes possible.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) This embodiment is shown in FIGS.
Will be described. In this embodiment, when the element is miniaturized, LD
Since the concentration of the D region must be high, it cannot be said that the region is already LightlyDope, and this region is hereinafter referred to as a shallow source-drain region, and the dense source-drain region is referred to as a deep source-drain region. I will call it.

The main focus is on suppressing the increase in the parasitic resistance while suppressing the short channel effect by increasing the impurity concentration and forming the film thinner in such a shallow source-drain region.

This embodiment is applied to an NMOS field effect transistor.

First, as shown in FIG. 1, a P-type well 82 is formed on a silicon single crystal substrate 81, and an STI (Sh
The element isolation region 83 is formed by an allow trench isolation (Allow Trench Isolation) method. Next, a channel implantation region 84 is formed in the P-type well 82 by ion-implanting a P-type impurity to adjust the threshold voltage. The conditions for forming the channel implantation region 84 include, for example, boron as a P-type impurity and an implantation acceleration voltage of 10 keV to 20 kV.
ev, implantation dose amount 5 × 10 ¹² / cm ² to 1 × 10
Ion implantation is performed under the condition of ¹³ / cm ² .

Next, as shown in FIG.
The gate insulating film 91 is formed on the entire surface by forming the silicon oxynitride film of FIG. The conditions for forming the acid nitrided film are 4
RT at 900 ° C. for 30 seconds in NO atmosphere of Torr
P (Rapid Thermal Process). In addition, the gate insulating film 91 is not limited to the silicon oxynitride film, and may be a silicon oxide film, a silicon nitride film, or another high dielectric insulator film such as strontium barium titanate.

Next, CVD is performed on the gate insulating film 91.
A gate electrode 92 is formed by forming a 175-nm-thick polycrystalline silicon film by a method and patterning the same.
At this time, the gate electrode 92 may be a conductive film such as doped polysilicon, amorphous silicon, SiGe, or a metal.

Next, as shown in FIG. 3, a Si ₃ N ₄ film is deposited on the entire surface of the silicon single crystal substrate 81 by a CVD method, and is etched back by anisotropic etching to form a gate. Gate side wall 101 is provided on the side surface of electrode 92.
To form At this time, the thickness of the gate sidewall 101 (the thickness from the interface with the side surface of the gate electrode 92 to the surface of the gate sidewall 101) may be, for example, 10 nm to 50 nm.

Next, as shown in FIG. 4, a first ion implantation step of substantially vertically ion-implanting an N-type impurity into the silicon single crystal substrate 81 is performed. The impurity doping region 111 is formed in the gate electrode 92 by the first ion implantation step, and the impurity doping region 112 serving as a deep source-drain region is formed in the silicon single crystal substrate 81 at a position sandwiching the gate electrode 92. Is formed. The conditions for the first ion implantation step include, for example, arsenic as an N-type impurity at an implantation acceleration voltage of 50 keV to 70 keV and a dose of 5 × 10 ¹⁵ / cm ² .

Next, a first heat treatment process is performed to activate the impurity doping region 111 and the deep source-drain region 112. This first heat treatment step
RTP with a heat treatment temperature of 1035 ° C. and a heat treatment time of 10 seconds was used. In this first heat treatment step, the heat treatment temperature is set to 1
By setting the temperature to 000 ° C. or more, the gate electrode 92
The impurity doped region 111 in the inside can be sufficiently activated, and depletion of the gate electrode 92 can be suppressed. The higher the activation rate of impurities in the gate electrode, the more depletion of the gate electrode can be suppressed.

FIG. 5 shows the first heat treatment temperature (horizontal axis).
FIG. 4 is a diagram illustrating an activation rate (vertical axis) of a gate electrode 92.

As shown in FIG. 5, when the heat treatment temperature is 1000
If the temperature is lower than ℃, the activation rate of the gate electrode becomes low, and the effect of suppressing depletion is not sufficient. Also, the longer the heat treatment time, the higher the activation rate tends to be.

According to the study of the present inventors, heat treatment temperature 900 ° C. heat treatment time 30 seconds gate electrode activation rate 50% heat treatment temperature 1035 ° C. heat treatment time 20 seconds gate electrode activation rate 80% heat treatment temperature 1100 ° C. heat treatment time 10 seconds Gate The electrode activation rate was 85%.

From these tendencies, preferred conditions for the first heat treatment step are a heat treatment temperature of about 1000 ° C. or more and a heat treatment time of about 10 seconds or more. If the heat treatment temperature is too high, boron as an impurity penetrates into the channel region from the gate electrode 92 made of P-type polysilicon, and the problem of collapse of the channel retrograde profile occurs. If the heat treatment temperature is too low, impurity activation in the gate electrode 92 is activated. The problem of depletion of the gate electrode 92 due to the shortage occurs. Further, if the heat treatment time is too long, there arises a problem that boron as an impurity penetrates into the channel region from the gate electrode 92 made of P-type polysilicon, and a problem that a channel retrograde profile collapses. If the heat treatment time is too short, impurity activation in the gate electrode is activated. The shortage causes a problem of depletion of the gate electrode.

Next, as shown in FIG. 6, an N-type impurity is ion-implanted into the silicon single crystal substrate 81 from obliquely upward via the gate insulating film 91 to form a second source-drain region 121 for forming a shallow region. Is performed. In the second ion implantation step, the ion implantation also penetrates below the gate side wall 101 and the shallow source-drain region 121 is formed.
Is formed. Also, in the second ion implantation step, the smaller the angle between the substrate surface of the silicon single crystal substrate 81 and the direction of the ion implantation, the shallower the source-
The implantation depth of the drain region 121 can be reduced. Also, a shallower junction can be formed by lowering the implantation acceleration voltage than in the first ion implantation step.

The conditions of the second ion implantation step include, for example, arsenic implantation acceleration voltage of 5 keV to 10 keV, implantation dose of 5 × 10 ¹⁴ / cm ² to 1 × 10 ¹⁵ / cm ² ,
The ion implantation direction may be selected so that the angle between the normal direction of the surface of the silicon single crystal substrate 81 and the ion implantation direction is in the range of 30 ° to 60 °.

Next, a second heat treatment step is performed to activate the shallow source-drain regions 121. The conditions of the second heat treatment step are a lower heat treatment temperature of 900 ° C. and a heat treatment time of 10 seconds as compared with the first heat treatment step for forming the deep source-drain region 112. By doing so, the impurity in the shallow source-drain region 121 does not diffuse deeply into the silicon single crystal substrate 81.

Here, when the MOS field effect transistor is miniaturized, it is very important to reduce the parasitic resistance value for the deep source-drain region 112, and for the shallow source-drain region 121, Not really. Therefore, shallow source-drain regions 12
In the case of 1, the junction depth is more important than the parasitic resistance value from the viewpoint of suppressing the short channel effect. Accordingly, the deep source-drain region 112 is subjected to a first heat treatment at a high temperature and a long time in order to further increase the activation rate, and thereafter the shallow source-drain region 121 is subjected to a second heat treatment at a lower temperature or a short time. By forming the junction, the parasitic resistance can be reduced in the deep source-drain region 112 and an extremely shallow junction can be formed in the shallow source-drain region 121.

FIG. 7 shows a conventional MOS having an LDD structure.
In order to compare the junction depth of the LDD region of the field-effect transistor with the junction depth of the shallow source-drain region 121 of the field-effect transistor in this embodiment, the SIMS profiles of arsenic are shown. The horizontal axis represents the depth from the surface of the silicon single crystal substrate, and the vertical axis represents the arsenic concentration.

From this profile, the depth of the source-drain region 121 shallower according to the present embodiment is about 20 nm (depth at which the arsenic concentration becomes 1 × 10 ¹⁸ / cm ² ), and the LDD for simultaneous heat treatment in the conventional method. Compared with the junction depth of the region of 40 nm, the depth can be reduced to about half.

Next, as shown in FIG. 8, after removing the oxide film on the silicon single crystal substrate 81 and the gate electrode 92 with hydrofluoric acid, Co is deposited on the entire wafer by sputtering, and is heat-treated by RTA. Cobalt silicide region 1 is formed above source-drain region and gate electrode 92.
31 are formed. Then, the extra Co film is peeled off.

Next, as shown in FIG. 9, an interlayer insulating film 141 made of a silicon oxide film is formed by the CVD method, and the contact hole 1 is formed at a predetermined position by anisotropic etching.
42 is formed. Next, aluminum is deposited by a sputtering method and patterned to form the wiring 143.

As described above, an NMOS field effect transistor having the shallow source-drain region 121 and the deep source-drain region 112 and capable of sufficiently controlling gate depletion can be formed.

In this embodiment, by replacing the N-type impurity with a P-type impurity and replacing the P-type impurity with an N-type impurity, a PMOS transistor can be similarly manufactured.

(Embodiment 2) In this embodiment, an NMOS
In forming a CMOS field-effect transistor having a field-effect transistor and a PMOS field-effect transistor, polycrystalline silicon is adopted as a gate electrode, and impurities are simultaneously implanted in the gate electrode when ions are implanted into a deep source-drain region. , And simultaneously activated by heat treatment, a so-called dual gate structure is adopted.

CMOS having this dual gate structure
In the field-effect transistor, in order to suppress depletion of the gate electrode, the temperature of the heat treatment step for activating impurities in the gate electrode is as high as 1000 ° C.
Long-term heat treatment of more than seconds is required.

First, as shown in FIG.
STI (Shallow Trench)
h Isolation), the element isolation region 15
2 to form an NMOS formation region 153 and a PMOS formation region.
And an area 161. Next, the PMOS formation region 161
A photoresist 154 is formed on the
Using the 154 as a mask, a P-type
The P-type well 155 is formed by ion-implanting impurities.
To form Next, the same photoresist 154 is used as a mask.
In order to adjust the threshold voltage,
The channel injection region 156 is formed into a P-type
It is formed in the well 155. Shape of channel injection region 156
The formation conditions are, for example, the implantation acceleration of boron as a P-type impurity.
Voltage 10 keV to 20 keV, implantation dose 5 × 10
¹²/ Cm²~ 1 × 10¹³/ Cm ²Ion injection under the conditions
Enter. Then, the photoresist 154 is removed.

Next, as shown in FIG. 11, a photoresist 162 is formed on the NMOS formation region 153, and an N-type impurity is ion-implanted on the PMOS formation region 161 using the photoresist layer 162 as a mask.
A mold well 163 is formed. Next, using the same photoresist 162 as a mask, an N-type impurity is ion-implanted to adjust a threshold voltage, thereby forming a channel implantation region 164 in the N-type well 163. Conditions for forming channel implant region 164 may, for example, arsenic injection accelerating voltage 70keV~150keV as N-type impurity, in the conditions of implantation dose ^{5 × 10 1 2 / cm 2} ~5 × 10 13 / cm 2 is ion-implanted. Then, the photoresist 162 is removed.

Next, as shown in FIG.
The gate insulating film 171 is formed on the P-type well 155 and the N-type well 16
3 is formed. The conditions for forming the acid nitride film were RTP at 900 ° C. for 30 seconds in a 4 Torr NO atmosphere. Further, the gate insulating film 171 is not limited to the silicon oxynitride film, and may be a silicon oxide film, a silicon nitride film, or another high dielectric insulator film such as strontium barium titanate.

Next, on this gate insulating film 171, CV
A gate electrode 172 is formed by forming a 175-nm-thick polycrystalline silicon film by the method D and patterning it. At this time, the gate electrode 172 may be a conductive film of doped polysilicon, amorphous silicon, SiGe, or a metal.

Next, as shown in FIG. 13, a Si ₃ N ₄ film is deposited on the entire surface of the silicon single crystal substrate 151 by the CVD method, and is etched back by anisotropic etching to form a side surface of the gate electrode 172. A gate sidewall 181 is formed on the substrate. At this time, the thickness of the gate side wall 181 (the thickness from the interface with the side surface of the gate electrode 172 to the surface of the gate side wall 181) may be, for example, 10 nm to 50 nm.

Next, as shown in FIG. 14, a photoresist 191 is formed on the PMOS formation region 161, and using this photoresist 191 as a mask, the NMOS formation region 1 is formed.
First, an N-type impurity is ion-implanted substantially vertically on
Is performed. By this first ion implantation step, an impurity doping region 192 is formed in the gate electrode 172 of the NMOS formation region 153, and the gate electrode 172 is formed.
Are formed at positions that are deep source-drain regions in the silicon single crystal substrate 151 at positions sandwiching the. The first ion implantation condition is, for example, an arsenic implantation acceleration voltage of 50 keV to 70 keV.
V, and an implantation dose of 5 × 10 ¹⁵ / cm ² .
Then, the photoresist 191 is removed.

Hereinafter, the same steps are performed in the PMOS formation region 161, and the drawings explaining this step are omitted.

First, a photoresist is formed in the NMOS formation region 153, and a first ion implantation step of substantially vertically ion-implanting a P-type impurity into the silicon single crystal substrate 151 is performed. By the first ion implantation process, the PMOS
An impurity doping region is formed in the gate electrode 172 in the formation region 161, and an impurity doping region 193 serving as a deep source-drain region is formed in the silicon single crystal substrate 151 at a position sandwiching the gate electrode 172. The first ion implantation conditions include, for example, boron implantation acceleration voltage of 5 keV to 10 keV, and dose of 5 × 10 ¹⁵ / c.
m ^2, and the like. Then, the photoresist is removed.

Next, the NMOS formation region 153 and the PMO
The impurity doping regions 192 and 1 of the S formation region 161
A first heat treatment step is performed to activate 93. The conditions of this first heat treatment step are as follows: a heat treatment temperature of 1035 ° C.
RTP with a heat treatment time of 10 seconds was used. In the first heat treatment step, by setting the heat treatment temperature to a high temperature of 1000 ° C. or higher, the impurity doping region 192 in the gate electrode 172 can be sufficiently activated, and depletion of the gate electrode 172 can be suppressed. Can be. Preferred conditions for the first heat treatment step are as follows:
The heat treatment time is 0 ° C. or more and about 10 seconds or more. If the heat treatment temperature is too high, the problem that boron as an impurity penetrates from the gate electrode 172 made of P-type polysilicon into the channel region and the problem of collapse of the channel retrograde profile occur.
There is a problem that the gate electrode 172 is depleted due to insufficient activation of impurities in the gate electrode 72. If the heat treatment time is too long, boron as an impurity penetrates into the channel region from the gate electrode 172 made of P-type polysilicon,
The problem of collapse of the channel retrograde profile occurs, and if too short, the problem of depletion of the gate electrode due to insufficient activation of impurities in the gate electrode occurs.

Next, as shown in FIG. 15, a photoresist 201 is formed on the PMOS formation region 161 and an N-type impurity is ion-implanted into the silicon single crystal substrate 151 obliquely from above using the photoresist 201 as a mask. Then, a second ion implantation step for forming a shallow source-drain region 211 is performed. By this second ion implantation step, a shallow source-drain region 221 is also formed below the gate side wall 181. In the second ion implantation step, the smaller the angle between the surface of the silicon single crystal substrate 151 and the direction of the ion implantation becomes, the shallower the source is.
The implantation depth of the drain region 221 can be reduced. Also, a shallower junction can be formed by lowering the implantation acceleration voltage than in the first ion implantation step.

The conditions of the second ion implantation step include, for example, arsenic implantation acceleration voltage of 5 keV to 10 keV, implantation dose of 5 × 10 ¹⁴ / cm ² to 1 × 10 ¹⁵ / cm ² ,
The ion implantation direction may be selected so that the angle between the normal direction of the surface of the silicon single crystal substrate 151 and the ion implantation direction is not less than 30 ° and not more than 60 °. And the photoresist 201
Is removed.

Hereinafter, the same oblique implantation step is performed in the PMOS formation region 161, and the description with reference to the drawings is omitted.

First, a photoresist is formed on the NMOS formation region 153, and the photoresist is used as a mask.
P-type impurities are ion-implanted obliquely from above into the silicon single crystal substrate 151 to form shallow source-drain regions 211.
Is performed in the second ion implantation step. By this second ion implantation step, a shallow source-drain region 221 is also formed below the gate side wall 181. In the second ion implantation step, the silicon single crystal substrate 15
As the ion implantation angle becomes smaller with respect to 1, the implantation depth of the shallower source-drain region 221 can be made smaller. Also, a shallower junction can be formed by lowering the implantation acceleration voltage than in the first ion implantation step.

The conditions of the second ion implantation step are, for example, a method in which boron is accelerated at an acceleration voltage of 5 keV to 10 keV, a dose is 5 × 10 ¹⁴ / cm ² to 1 × 10 ¹⁵ / cm ² , and a silicon single crystal substrate 151 surface is formed. The ion implantation direction may be selected so that the angle between the linear direction and the ion implantation direction is 30 ° or more and 60 ° or less. Then, the photoresist is removed.

Next, as shown in FIG. 16, a second heat treatment step is performed to activate the shallow source-drain regions 221 in both the NMOS formation region 153 and the PMOS formation region 161. The conditions of the second heat treatment step are a heat treatment temperature of 1000 ° C. lower than that of the first heat treatment and a short heat treatment time of 5 seconds.

As described above, the shallow source-drain regions 2
As a second heat treatment step for activating the impurity 11, if the heat treatment time is shortened to 5 seconds even at a relatively high temperature of 1000 ° C., the shallow source-drain region 211 can prevent an increase in depth due to thermal diffusion.

Next, after removing the oxide film on the source-drain region and the gate electrode 92 with hydrofluoric acid, Co is deposited on the whole wafer by sputtering, and the source-drain region and the gate electrode 92 are heat-treated by RTP.
A cobalt silicide region 131 is formed thereon. Then, the extra Co film is peeled off.

Next, as shown in FIG. 17, an interlayer insulating film 221 is formed by a CVD method, and a contact hole 222 is formed at a predetermined position by anisotropic etching. Next, aluminum is deposited by a sputtering method and patterned to form a wiring 223.

As described above, a CMOS field effect transistor having a shallow source-drain region and a deep source-drain region and capable of sufficiently controlling gate depletion can be formed.

Although the present invention has been described using a silicon single crystal substrate as the semiconductor substrate, the SOI (Silic)
on On Insulator) substrate, SiGe, G
A substrate on which a semiconductor layer such as aAs or GaN is formed can be used.

[0069]

According to the present invention, in a field effect transistor having a deep source-drain region and a shallow source-drain region, diffusion of the shallow source-drain region is prevented.
It is possible to provide a method for manufacturing a semiconductor device in which a short channel effect does not occur even when a gate length is reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating one step of a method for manufacturing a field-effect transistor according to Embodiment 1 of the present invention.

FIG. 2 is a cross-sectional view illustrating one step of the method for manufacturing the field-effect transistor according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a step of the method for manufacturing the field-effect transistor according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating one step of the method for manufacturing the field-effect transistor according to the first embodiment of the present invention.

FIG. 5 is a graph showing a first heat treatment temperature and an activation ratio of an impurity in a gate electrode.

FIG. 6 is a cross-sectional view illustrating a step of the method for manufacturing the field-effect transistor according to the first embodiment of the present invention.

FIG. 7 is a graph comparing the junction depth of an LDD region of a conventional field effect transistor with the junction depth of a shallow source-drain region of the field effect transistor of the present invention.

FIG. 8 is a sectional view of one step in the method for manufacturing the field-effect transistor according to the first embodiment of the present invention.

FIG. 9 is a cross-sectional view illustrating a step of the method for manufacturing the field-effect transistor according to the first embodiment of the present invention.

FIG. 10 is a sectional view of one step in a method for manufacturing a field-effect transistor according to the second embodiment of the present invention.

FIG. 11 is a cross-sectional view illustrating one step of a method for manufacturing a field-effect transistor according to Embodiment 2 of the present invention.

FIG. 12 is a cross-sectional view illustrating one step of a method for manufacturing a field-effect transistor according to Embodiment 2 of the present invention.

FIG. 13 is a cross-sectional view illustrating one step of a method for manufacturing a field-effect transistor according to Embodiment 2 of the present invention.

FIG. 14 is a cross-sectional view illustrating one step of a method for manufacturing a field-effect transistor according to Embodiment 2 of the present invention.

FIG. 15 is a cross-sectional view illustrating one step of a method for manufacturing a field-effect transistor according to Embodiment 2 of the present invention.

FIG. 16 is a cross-sectional view illustrating one step of a method for manufacturing a field-effect transistor according to Embodiment 2 of the present invention.

FIG. 17 is a cross-sectional view illustrating one step of a conventional method for manufacturing a field-effect transistor.

FIG. 18 is a cross-sectional view illustrating one step of a conventional method for manufacturing a field-effect transistor.

FIG. 19 is a cross-sectional view illustrating one step of a conventional method for manufacturing a field-effect transistor.

FIG. 20 is a cross-sectional view illustrating one step of a conventional method for manufacturing a field-effect transistor.

FIG. 21 is a cross-sectional view illustrating one step of a conventional method for manufacturing a field-effect transistor.

FIG. 22 is a cross-sectional view illustrating one step of a conventional method for manufacturing a field-effect transistor.

FIG. 23 is a cross-sectional view illustrating one step of a conventional method for manufacturing a field-effect transistor.

FIG. 24 is a cross-sectional view illustrating one step of a conventional method for manufacturing a field-effect transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Silicon single crystal substrate 12 ... N-type well 13 ... P-type well 14, 15, 16 ... LOCOS element isolation region 21 ... NMOS channel region 22 ... PMOS channel region 31 ..Gate insulating film 32 ... Gate electrode 41 ... Gate sidewall insulating film 51 ... Photoresist layer 52 ... P-type LDD region 61 ... P-type deep source-drain diffusion layer region 81 ··· Silicon single crystal substrate 82 ··· P-type well 83 ··· element isolation region 84 ··· channel injection region 91 ··· gate insulating film 92 ··· gate electrode 101 ··· gate side wall 111 ··· -Impurity doping region to gate electrode 112 ... deep source-drain region 121 ... shallow source-drain region 131 ... cobalt silicide region 41 ... interlayer insulating film 142 ... contact hole 143 ... wiring 151 ... silicon single crystal substrate 152 ... element isolation region 153 ... NMOS formation region 154 ... photoresist 155 ... P-type well 156... P-type channel injection region 161... PMOS formation region 162... Photoresist 163... N-type well 164. ..Gate electrode 181 ... Gate side wall 191 ... Photoresist 192 ... Impurity doping region to gate electrode 193 ... Deep source-drain region 201 ... Photoresist 202 ... Shallow source-drain Region 211 ... Interlayer insulating film 222 ... Contact hole 223 ... Wiring

Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat II (Reference) H01L 29/786 F term (Reference) 5F040 DA06 DB03 DC01 DC03 EC04 EC07 EC10 EC13 ED03 ED04 EF02 EH02 EH05 EK05 EL02 FA07 FB03 FC13 FC19 5F048 AA07 AC01 AC03 BB04 BB06 BB07 BB11 BB14 BC06 BD04 BE03 BE04 BF02 BF06 BG14 DA27 5F110 AA04 AA06 BB04 CC02 DD05 DD13 EE05 EE08 EE09 EE14 EE27 EE32 EE45 EE50 FF01 FF02 J03 H04 GG03 FF03 GG03 FF03 GG03 FF03 GG03 FF03 GG03 FF03 GG02 HM15 NN02 NN23 NN35 NN62 NN65 QQ11

Claims (4)

[Claims] A step of forming a gate insulating film on a semiconductor substrate; a step of forming a gate electrode on the gate insulating film; a step of forming a gate sidewall on a side surface of the gate electrode; A first ion implantation step of implanting ions below the gate electrode and below the gate side wall to form an ion implantation region; and activating the ion implantation region to form a source region and a drain region in the semiconductor substrate. Forming a first heat treatment step; and ion-implanting the semiconductor substrate obliquely from above to form an ion-implanted region shallower than the source region and the drain region below the gate sidewall. A method of manufacturing a semiconductor device, comprising: an implantation step; and a second heat treatment step for activating the shallow ion implantation region. 2. The method according to claim 1, wherein the gate electrode is formed of polycrystalline silicon, and ions are simultaneously implanted into the gate electrode at the time of the first ion implantation step, and the gate electrode is formed at the time of the first heat treatment step. 2. The method according to claim 1, wherein the ions implanted into the electrodes are activated. 3. The method according to claim 1, wherein the second heat treatment step has a lower heat treatment temperature than the first heat treatment step. 4. The method of manufacturing a semiconductor device according to claim 1, wherein said second heat treatment step has a shorter heat treatment time than said first heat treatment step.