JPS6344769A - Field effect transistor and manufacture of the same - Google Patents
Field effect transistor and manufacture of the sameInfo
- Publication number
- JPS6344769A JPS6344769A JP18881686A JP18881686A JPS6344769A JP S6344769 A JPS6344769 A JP S6344769A JP 18881686 A JP18881686 A JP 18881686A JP 18881686 A JP18881686 A JP 18881686A JP S6344769 A JPS6344769 A JP S6344769A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- insulating film
- diffusion layer
- gate insulating
- effect transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 9
- 230000003647 oxidation Effects 0.000 claims abstract description 5
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 54
- 238000009792 diffusion process Methods 0.000 claims description 37
- 239000012535 impurity Substances 0.000 claims description 9
- 238000002844 melting Methods 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 239000007772 electrode material Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000002356 single layer Substances 0.000 claims description 3
- 229910021332 silicide Inorganic materials 0.000 claims 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 7
- 239000002784 hot electron Substances 0.000 abstract description 7
- 230000006866 deterioration Effects 0.000 abstract description 5
- 230000005684 electric field Effects 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はホントキャリヤ効果を抑制するための電界効果
型トランジスタ（通称ＭＯ３Ｔｒ）の謙−” ゲート電
極及
びソース・ドレイン拡散層の構造に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to the structure of the gate electrode and source/drain diffusion layer of a field effect transistor (commonly known as MO3Tr) for suppressing the real carrier effect. be.
第２図は従来の通称ＬＤＤ ：ライトリー ドープト
ドレイン （Ｌｉｇｈｔｌｙ Ｄｏｐｅｄ Ｄｒａｉｎ
）といわれるＭ ＯＳ Ｔ ｒの断面構造を工程順に示
したものである。図中、１はシリコン基キ反、２はゲー
トへ色縁膜、３はゲート電極、４は低濃度ソース・ドレ
イン拡散層、５はサイドウオール、６は高濃度ソース・
ドレイン拡散層である。Figure 2 shows the conventional name LDD: Lightly Doped.
Lightly Doped Drain
) shows the cross-sectional structure of MOSTr in the order of steps. In the figure, 1 is a silicon base film, 2 is a color border film to the gate, 3 is a gate electrode, 4 is a low concentration source/drain diffusion layer, 5 is a side wall, and 6 is a high concentration source/drain layer.
This is a drain diffusion layer.
次に製造方法について説明する。Next, the manufacturing method will be explained.
基板１上にゲート絶縁膜２を介して例えば多結晶シリコ
ンあるいは高融点金属のような導電材料を形成した後、
該導電材料をプラズマ反応を利用して公知の方法で選択
的に加工し、ゲート電極３を形成する（第２図［５１）
。After forming a conductive material such as polycrystalline silicon or high melting point metal on the substrate 1 via the gate insulating film 2,
The conductive material is selectively processed by a known method using a plasma reaction to form the gate electrode 3 (FIG. 2 [51])
.
次いで基板１と逆導電型の不に物をｌＸｌ０”／ａｊ〜
ｌ Ｘ Ｉ Ｑ ”／’ｃｄ程度の濃度でイオン注入等
の方法で基板１０表面に入射する。このとき、ゲート電
極３をマスクとして自己整合的にゲート電極３の両側に
、例えばＮ型であればＮ−の拡散層４が形成される。Next, a non-conductor of the opposite conductivity type to the substrate 1 is
Ion implantation is applied to the surface of the substrate 10 at a concentration of about lXIQ''/'cd. At this time, ions, for example of N type Then, an N- diffusion layer 4 is formed.
次いで例えばシリコン酸化膜等の絶縁膜を一定の厚さで
全面に形成した後、イオンエツチング等の方向性を有す
るいわゆる異方性エツチングを全面に行って、垂直なゲ
ート電極３の側壁に、サイドウオール５と呼ばれるシリ
コン酸化膜を形成する。Next, after forming an insulating film such as a silicon oxide film on the entire surface with a constant thickness, so-called anisotropic etching with directionality such as ion etching is performed on the entire surface to form sidewalls on the vertical side walls of the gate electrode 3. A silicon oxide film called wall 5 is formed.
この後、その全面に、基板と逆導電４型の不純物を高濃
度（Ｉ Ｘ １０ ”／ｃｉ以上）イオン注入し、高温
の熱処理を加えることによって活性化した高濃度ソース
・ドレイン拡散層６を形成する（第２図（ト）））。Thereafter, a high concentration source/drain diffusion layer 6 is formed by ion-implanting impurities of type 4 with conductivity opposite to that of the substrate at a high concentration (I x 10''/ci or more) over the entire surface and by applying high temperature heat treatment. form (Figure 2 (g))).
このとき、高濃度ソース・ドレイン拡散層６はサイドウ
オール５をマスクに自己整合的に形成されるため、上記
低濃度不純物拡散層４の端からはみ出さないように形成
され、２重拡散層構造が得られる。この構造のＭＯ３Ｔ
ｒでは、ドレイン近傍での強電界を弱め、ホットエレク
トロン効果を抑制することができる。At this time, the high concentration source/drain diffusion layer 6 is formed in a self-aligned manner using the sidewall 5 as a mask, so that it is formed so as not to protrude from the edge of the low concentration impurity diffusion layer 4, resulting in a double diffusion layer structure. is obtained. MO3T with this structure
With r, the strong electric field near the drain can be weakened and the hot electron effect can be suppressed.
しかし、サイドウオール形成のための工程が増加する。 However, the number of steps required to form the sidewalls increases.
サイドウオール巾の制御が困難である等の問題に加えて
、最近この構造によるｇｍ劣化の問題点が明らかになっ
てきた。すなわち第２図（Ｃ）に模式的に示すようにド
レイン近傍での強電界によって発生したホットエレクト
ロンがゲート３側壁のサイドウオール５にトラップされ
、このトラップ電子によって低４度のソース・ドレイン
層４の表面がＰ型に反転しやすくなり、実行的にＮ−濃
度がより低くなり、Ｍ ＯＳ Ｔ ｒのソース抵抗の増
大となってｇｍ等が劣化する現象である。In addition to problems such as difficulty in controlling the sidewall width, the problem of GM deterioration due to this structure has recently become clear. That is, as schematically shown in FIG. 2(C), hot electrons generated by a strong electric field near the drain are trapped in the sidewall 5 on the side wall of the gate 3, and these trapped electrons cause the low-4 degree source/drain layer 4 to be trapped. This is a phenomenon in which the surface of the MOS transistor becomes more likely to be inverted to P type, effectively lowering the N- concentration, increasing the source resistance of the MOS transistor, and deteriorating the gm, etc.
本発明は上記のような欠点に観みてなされたもので、ホ
ットエレクトロン効果及びｇｍ劣化を防止できる信鎖性
の高い電界効果型トランジスタ及びその製造方法を得る
ことを目的とする。The present invention was made in view of the above-mentioned drawbacks, and an object of the present invention is to provide a field effect transistor with high signal chain properties that can prevent the hot electron effect and GM deterioration, and a method for manufacturing the same.
本願の第１の発明のかかる電界効果型トランジスタは、
ゲート絶縁膜の両側端部を厚くし、ゲー・ト絶縁膜の薄
い部分と重ならない＃テ形城透土造２重拡散ソース・ド
レイン層を設けたものである。The field effect transistor according to the first invention of the present application includes:
Both ends of the gate insulating film are made thicker, and double diffusion source/drain layers are provided in a T-shaped transparent earthen structure that do not overlap with the thinner parts of the gate insulating film.
本願の第２の発明にかかる電界効果型トランジスタの製
造方法は、基板上に絶縁膜を介してゲート電極を形成し
た後、同種又は異種のイオンを注入して２重ソース・ド
レイン拡散層を形成し、その後、ゲート電極の外側から
熱酸化して上記ゲート絶縁膜の両側端部を厚く成長させ
るようにしたものである。In the method for manufacturing a field effect transistor according to the second invention of the present application, after forming a gate electrode on a substrate via an insulating film, ions of the same type or different types are implanted to form a double source/drain diffusion layer. Then, the gate electrode is thermally oxidized from the outside to grow thicker both ends of the gate insulating film.
本願の第１の発明においては、ゲート絶縁膜の両側端部
を厚くし２２、ケ゛−ト絶縁膜の薄い部分と重ならない
よりニ形成〜ぎ上方２重拡散ソース・ドレイン層を設け
たから、ゲートとソース・ドレイン間の付加容量はなく
ドレイン近傍での電界強度は緩和され、またホットエレ
クトロンがゲート絶縁膜にトラップされてもゲート電極
の正電位により電子の負電位を中和できる。In the first invention of the present application, both end portions of the gate insulating film are thickened22, and the upper double diffusion source/drain layers are provided so as not to overlap with the thin portions of the gate insulating film. There is no additional capacitance between the source and the drain, so the electric field strength near the drain is relaxed, and even if hot electrons are trapped in the gate insulating film, the negative potential of the electrons can be neutralized by the positive potential of the gate electrode.
本願の第２の発明においては、ゲート電極の外側からゲ
ート絶縁膜を酸化するようにしたから、容易にかつ確実
にゲート絶縁膜の側部を厚（することができる。In the second invention of the present application, since the gate insulating film is oxidized from the outside of the gate electrode, the side portions of the gate insulating film can be easily and reliably thickened.
以下、本発明の一実施例を図について説明する。 Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例によるＭ ＯＳ Ｔ ｒの断
面構造を工程順に示し、図において、１はシリコン基板
、２は側端部が厚いゲート絶縁膜、３は該ゲート屯縁膜
２上に形成されたゲート電極、４は低２３度ソース・ド
レイン拡散層、６はゲート電極３に対して核層４より外
側に核層４と連続して形成された高濃度ソース・ドレイ
ン拡散層である。FIG. 1 shows the cross-sectional structure of an MOS transistor according to an embodiment of the present invention in the order of steps. The gate electrode formed above, 4 is a low 23 degree source/drain diffusion layer, and 6 is a high concentration source/drain diffusion layer formed continuously with the nucleus layer 4 outside the nucleus layer 4 with respect to the gate electrode 3. It is.
次に製造方法について説明する。Next, the manufacturing method will be explained.
シリコン基ｖｉ１の上にゲート絶縁膜２を形成した後、
ゲー）を極３用材籾を形成する。この材料は例えば多結
晶シリコンあるいは高融点金属等の単一層膜あるいは両
者を含む２層以上の複数層膜のいづれでもよい。After forming the gate insulating film 2 on the silicon base vi1,
Ge) is used to form paddy for pole 3. This material may be either a single layer film of polycrystalline silicon or a high melting point metal, or a multilayer film of two or more layers containing both.
この電極材料を公知のエツチング方法で加工してゲート
電極３を形成した後、基板１と逆導電型の不純物を低濃
度（１×１０＋２／ｃＩａ〜１×１０′４／−）にイオ
ン注入して低濃度拡散層４を形成しく第１図ｆａｎ）、
続いて上記不純物と同導電型の不純物を高濃度（５Ｘ１
０１〜ｌＸｌ０１ｂ／ｃｕｔ）にイオン注入して高濃度
拡散層６を形成する（第１図（ト）））。この時、低濃
度層４と高濃度層６とは互いに連続し、かつ低濃度層４
が高４度層６の内側となるよう、すなわち低濃度Ｎ４が
高濃度層よりゲート電極３側に近い２重拡散構造となる
よう、不純物元素及び熱処理等の条件を設定している。After forming the gate electrode 3 by processing this electrode material using a known etching method, impurities of the opposite conductivity type to the substrate 1 are ion-implanted at a low concentration (1×10+2/cIa to 1×10'4/-). to form a low concentration diffusion layer 4 (see FIG. 1),
Next, impurities of the same conductivity type as the above impurities were added at a high concentration (5X1
01 to lXl01b/cut) to form a high concentration diffusion layer 6 (FIG. 1(g))). At this time, the low concentration layer 4 and the high concentration layer 6 are continuous with each other, and the low concentration layer 4
Conditions such as impurity elements and heat treatment are set so that N4 is inside the high-4 degree layer 6, that is, a double diffusion structure is formed in which the low concentration N4 is closer to the gate electrode 3 than the high concentration layer.
次いで、ゲート電極３の外側から熱酸化してゲート電極
３と基板１との間のゲート絶縁膜２の側端部分を厚く成
長させる（第１図（Ｃ））。ここで酸化時間、’ＩＡ度
等は酸化膜２が低４度拡散層４の側端上部から外側すな
わち高濃度層６側に向かってしだいに厚くなるよう選択
している。その結果ＭＯ３Ｔｒの特性を決める実効チャ
ネル長（Ｌｅｆｆ）に相当する部分のゲート絶縁膜２の
厚さは、当初設定した膜厚と変わらず、ｇｍ等の基本特
性は設計値通りの値を得ることができる。Next, thermal oxidation is performed from the outside of the gate electrode 3 to thicken the side end portions of the gate insulating film 2 between the gate electrode 3 and the substrate 1 (FIG. 1(C)). Here, the oxidation time, IA degree, etc. are selected so that the oxide film 2 gradually becomes thicker from the upper side end of the low 4 degree diffusion layer 4 toward the outside, that is, toward the high concentration layer 6 side. As a result, the thickness of the gate insulating film 2 corresponding to the effective channel length (Leff), which determines the characteristics of MO3Tr, remains the same as the initially set thickness, and basic characteristics such as gm can be obtained as designed values. Can be done.
このように本実施例ではゲート絶縁膜の両側端部を厚く
し、ソース・ドレイン拡散層を２重拡散構造としたので
、ドレイン近傍での電界強度は低濃度層４で緩和され、
また発生したホットエレクトロンがゲート絶縁膜２にト
ラップされても、その上にゲート電極３があるため、ゲ
ート電））の正電位によって電子の負電位を中和するこ
とができ、従来問題となったトラップ電子によるｇｍ劣
化を防止することができる。またゲート電極の外側から
ゲート絶縁膜を酸化するようにしたから、容易にかつ確
実にゲート絶縁膜の側部を厚くすることができる。In this way, in this embodiment, both ends of the gate insulating film are thickened and the source/drain diffusion layers have a double diffusion structure, so the electric field strength near the drain is relaxed by the low concentration layer 4.
Furthermore, even if the generated hot electrons are trapped in the gate insulating film 2, since the gate electrode 3 is located above it, the negative potential of the electrons can be neutralized by the positive potential of the gate electrode), which has been a problem in the past. It is possible to prevent gm deterioration due to trapped electrons. Furthermore, since the gate insulating film is oxidized from the outside of the gate electrode, the side portions of the gate insulating film can be easily and reliably thickened.
なお、本発明はＮ型あるいはＰ型のいずれのＭＯ３Ｔｒ
にも適用でき、また、単一基板上のみならず、エピタキ
シャル層、あるいはウェハ上に形成されたＭＯ３Ｔｒに
も適用できこの場合も、上記実施例と同様の効果が得ら
れる。又本発明はシリコン半導体以外の化合物半導体に
おいても適用できるのは勿論である。Note that the present invention applies to either N-type or P-type MO3Tr.
Furthermore, it can be applied not only to a single substrate but also to an epitaxial layer or MO3Tr formed on a wafer, and in this case, the same effects as in the above embodiment can be obtained. It goes without saying that the present invention can also be applied to compound semiconductors other than silicon semiconductors.
また上記実施例ではソース・ドレイン層が２重拡散構造
である場合について述べたが、高濃度ソース・ドレイン
層はソース・ドレイン抵抗を低くし、かつソース・ドレ
イン電極との接触抵抗を下げるために形成するもので、
例えば表面をシリサイド化する等の低抵抗化手段を用い
た場合、あるいは低抵抗化の必要のない場合等において
は高濃度ソース・ドレイン層は不要となり、これらの場
合にはソース・ドレイン拡散層は低濃度ソース・ドレイ
ン拡散層の単一層構造でもよい。Furthermore, in the above embodiment, the case where the source/drain layer has a double diffusion structure has been described, but the highly doped source/drain layer is used to lower the source/drain resistance and the contact resistance with the source/drain electrode. It forms
For example, if a low resistance method such as siliciding the surface is used, or if there is no need to reduce the resistance, the high concentration source/drain layer is not necessary.In these cases, the source/drain diffusion layer is A single layer structure of low concentration source/drain diffusion layers may be used.
以上のように本願の第１の発明によれば、ゲート電極下
のゲート絶縁膜の側端部を厚くし、ゲート絶縁膜の厚い
分の下に低濃度拡散層を、その外側に高濃度拡散層を連
続的に形成したので、ドレイン近傍でのホットキャリヤ
の発生を抑えることができるだけでな（、絶縁膜中にト
ラップされたキャリヤによるｇｍ劣化等を防止でき信頼
性の高い電界効果型トランジスタを得ることができる。As described above, according to the first invention of the present application, the side edges of the gate insulating film under the gate electrode are thickened, a low concentration diffusion layer is provided under the thick part of the gate insulating film, and a high concentration diffusion layer is provided outside the thick part of the gate insulating film. Since the layers are formed continuously, it is possible to not only suppress the generation of hot carriers near the drain (but also prevent GM deterioration caused by carriers trapped in the insulating film, making it possible to create a highly reliable field effect transistor. Obtainable.
また、本願の第２の発明によれば、ゲート電極の外側か
らゲート絶縁膜を酸化するようにしたので、ゲート絶縁
膜の側端部の厚いＭＯＳ）ランジスタを容易にかつ確実
に製造できる。Further, according to the second invention of the present application, since the gate insulating film is oxidized from the outside of the gate electrode, it is possible to easily and reliably manufacture a MOS transistor with thick side edges of the gate insulating film.
第１図は、本発明の一実施例によるＭＯ３ｒの断面構造
を工程順に示す図、第２図は従来のＬＤＤ型Ｍ ＯＳ
Ｔ ｒの断面構造を工程順に示す図である。
図中、１はシリコン基板、２はゲート絶縁膜、３はゲー
ト電極、４は低１度ソース・ドレイン拡散層、６は高濃
度ソース・ドレイン拡散層である。
なお図中同一符号は同−又は相当部分を示す。FIG. 1 is a diagram showing the cross-sectional structure of MO3r according to an embodiment of the present invention in the order of steps, and FIG. 2 is a diagram showing a conventional LDD type MOS.
It is a figure which shows the cross-sectional structure of T r in order of process. In the figure, 1 is a silicon substrate, 2 is a gate insulating film, 3 is a gate electrode, 4 is a low-1 degree source/drain diffusion layer, and 6 is a high concentration source/drain diffusion layer. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (6)
より厚いゲート絶縁膜と、 該ゲート絶縁膜上に形成されたゲート電極と、該ゲート
電極両側の基板表面にゲート絶縁膜の薄い部分と重なら
ないよう形成されたソース・ドレイン拡散層とを備えた
ことを特徴とする電界効果型トランジスタ。(1) In a field effect transistor, a gate insulating film is formed in a predetermined region on a substrate, and its side edges are thicker in the center, a gate electrode formed on the gate insulating film, and both sides of the gate electrode. 1. A field effect transistor characterized by comprising a source/drain diffusion layer formed on the surface of a substrate so as not to overlap with a thin portion of a gate insulating film.
点金属またはそのシリサイドからなる単一層構造あるい
は多結晶シリコン及び高融点金属の両者もしくはこれら
のシリサイドからなる二層構造であることを特徴とする
特許請求の範囲第１項記載の電界効果型トランジスタ。(2) A patent characterized in that the gate electrode has a single-layer structure made of polycrystalline silicon, a high-melting point metal, or a silicide thereof, or a two-layer structure made of both polycrystalline silicon and a high-melting point metal, or their silicides. A field effect transistor according to claim 1.
せて形成された低濃度拡散層及び該低濃度拡散層より厚
くこれと連続してかつゲート電極からやや離して形成さ
れた高濃度拡散層からなる２重拡散層構造であることを
特徴とする特許請求の範囲第１項または第２項記載の電
界効果型トランジスタ。(3) The source/drain layer includes a low-concentration diffusion layer formed close to the gate electrode and a high-concentration diffusion layer thicker than the low-concentration diffusion layer and continuous with the low-concentration diffusion layer and slightly separated from the gate electrode. 3. The field effect transistor according to claim 1, wherein the field effect transistor has a double diffusion layer structure.
２／ｃｍ＾２〜４×１０＾１＾４／ｃｍ＾２の範囲であ
り、上記高濃度拡散層の不純物濃度は、５×１０＾１＾
４／ｃｍ＾２〜１×１０＾１＾６／ｃｍ＾２の範囲であ
ることを特徴とする特許請求の範囲第３項記載の電界効
果型トランジスタ。(4) The impurity concentration of the above low concentration diffusion layer is 1×10^1^
2/cm^2 to 4 x 10^1^4/cm^2, and the impurity concentration of the high concentration diffusion layer is 5 x 10^1^
4/cm^2 to 1x10^1^6/cm^2.
ート電極材料を形成する第１の工程、次にゲート電極材
料を選択的にエッチングしてゲート電極を形成した後、
ゲート電極両側の基板上に不純物を注入してソース・ド
レイン拡散層を形成する第２の工程、 その後、ゲート電極の外側から熱酸化して上記ゲート絶
縁膜の側端部を中央部より厚く成長させる第３の工程を
含むことを特徴とする電界効果型トランジスタの製造方
法。(5) In a method for manufacturing a field effect transistor, a first step of forming a gate insulating film on a semiconductor substrate, forming a gate electrode material thereon, and then selectively etching the gate electrode material. After forming the gate electrode,
The second step is to form source/drain diffusion layers by injecting impurities onto the substrate on both sides of the gate electrode, and then thermal oxidation is performed from the outside of the gate electrode to grow the side edges of the gate insulating film thicker than the center. A method for manufacturing a field effect transistor, comprising a third step of:
又は異種のイオンを注入して、低濃度拡散層をゲート電
極に近接させて形成するとともに、高濃度拡散層をゲー
ト電極からやや離して形成し、これにより２重拡散ソー
ス・ドレイン層を形成する工程であることを特徴とする
特許請求の範囲第５項記載の電界効果型トランジスタの
製造方法。(6) In the second step, ions of the same or different types are implanted into the substrate on both sides of the gate electrode to form a low concentration diffusion layer close to the gate electrode, and a high concentration diffusion layer slightly away from the gate electrode. 6. The method of manufacturing a field effect transistor according to claim 5, further comprising forming double diffused source/drain layers separately from each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18881686A JPS6344769A (en) | 1986-08-12 | 1986-08-12 | Field effect transistor and manufacture of the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18881686A JPS6344769A (en) | 1986-08-12 | 1986-08-12 | Field effect transistor and manufacture of the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6344769A true JPS6344769A (en) | 1988-02-25 |
Family
ID=16230316
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18881686A Pending JPS6344769A (en) | 1986-08-12 | 1986-08-12 | Field effect transistor and manufacture of the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6344769A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05302297A (en) * | 1991-02-12 | 1993-11-16 | Agency Of Ind Science & Technol | Synthetic pulp and product using the same |
| US5510648A (en) * | 1994-01-04 | 1996-04-23 | Motorola, Inc. | Insulated gate semiconductor device and method of fabricating |
| US5541132A (en) * | 1995-03-21 | 1996-07-30 | Motorola, Inc. | Insulated gate semiconductor device and method of manufacture |
| US5612244A (en) * | 1995-03-21 | 1997-03-18 | Motorola, Inc. | Insulated gate semiconductor device having a cavity under a portion of a gate structure and method of manufacture |
| US5661048A (en) * | 1995-03-21 | 1997-08-26 | Motorola, Inc. | Method of making an insulated gate semiconductor device |
| US5679968A (en) * | 1990-01-31 | 1997-10-21 | Texas Instruments Incorporated | Transistor having reduced hot carrier implantation |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5215273A (en) * | 1975-07-28 | 1977-02-04 | Hitachi Ltd | Semiconductor device |
| JPS5326683A (en) * | 1976-08-25 | 1978-03-11 | Hitachi Ltd | Manufacture of semiconductor devic e |
| JPS5492183A (en) * | 1977-12-29 | 1979-07-21 | Fujitsu Ltd | Manufacture of mis type semiconductor device |
-
1986
- 1986-08-12 JP JP18881686A patent/JPS6344769A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5215273A (en) * | 1975-07-28 | 1977-02-04 | Hitachi Ltd | Semiconductor device |
| JPS5326683A (en) * | 1976-08-25 | 1978-03-11 | Hitachi Ltd | Manufacture of semiconductor devic e |
| JPS5492183A (en) * | 1977-12-29 | 1979-07-21 | Fujitsu Ltd | Manufacture of mis type semiconductor device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5679968A (en) * | 1990-01-31 | 1997-10-21 | Texas Instruments Incorporated | Transistor having reduced hot carrier implantation |
| JPH05302297A (en) * | 1991-02-12 | 1993-11-16 | Agency Of Ind Science & Technol | Synthetic pulp and product using the same |
| US5510648A (en) * | 1994-01-04 | 1996-04-23 | Motorola, Inc. | Insulated gate semiconductor device and method of fabricating |
| US5541132A (en) * | 1995-03-21 | 1996-07-30 | Motorola, Inc. | Insulated gate semiconductor device and method of manufacture |
| US5612244A (en) * | 1995-03-21 | 1997-03-18 | Motorola, Inc. | Insulated gate semiconductor device having a cavity under a portion of a gate structure and method of manufacture |
| US5661048A (en) * | 1995-03-21 | 1997-08-26 | Motorola, Inc. | Method of making an insulated gate semiconductor device |
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