JPS6344770A - Field effect transistor and manufacture of the same - Google Patents

Field effect transistor and manufacture of the same

Info

Publication number
JPS6344770A
JPS6344770A JP18881786A JP18881786A JPS6344770A JP S6344770 A JPS6344770 A JP S6344770A JP 18881786 A JP18881786 A JP 18881786A JP 18881786 A JP18881786 A JP 18881786A JP S6344770 A JPS6344770 A JP S6344770A
Authority
JP
Japan
Prior art keywords
gate electrode
drain
diffused layers
formed
invert
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18881786A
Other versions
JPH0571174B2 (en
Inventor
Koji Ozaki
Takahisa Sakaemori
Shinichi Sato
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP61188817A priority Critical patent/JPH0571174B2/ja
Publication of JPS6344770A publication Critical patent/JPS6344770A/en
Publication of JPH0571174B2 publication Critical patent/JPH0571174B2/ja
Anticipated expiration legal-status Critical
Application status is Expired - Lifetime legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T

Abstract

PURPOSE: To suppress hot carrier effect and avoid gm deterioration by a method wherein side walls are provided between the brim parts of a gate electrode which has an invert T-shape cross-section and a substrate and the substrate side part of the gate electrode does not overlap source and drain diffused layers.
CONSTITUTION: A gate electrode 3 which has brim parts and has an invert T-shape cross-section is formed by applying plasma etching to electrode materials 3a and 3b. After an insulating film such as a silicon oxide film is formed over the whole surface with a certain thickness, the whole surface is anisotropically etched to form silicon oxide films which are called side walls 5 on the sides of the gate electrode 3. Then, high concentration source and drain diffused layers 6 are so formed as to be continuous with low concentration source and drain diffused layers 4 and not to spread over the edges of the low concentration regions to penetrate under a gate insulating film 2 to form a double diffused structure. With this constitution, an electric field near a drain is relaxed and creation of hot carriers can be suppressed.
COPYRIGHT: (C)1988,JPO&Japio
JP61188817A 1986-08-12 1986-08-12 Expired - Lifetime JPH0571174B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61188817A JPH0571174B2 (en) 1986-08-12 1986-08-12

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61188817A JPH0571174B2 (en) 1986-08-12 1986-08-12

Publications (2)

Publication Number Publication Date
JPS6344770A true JPS6344770A (en) 1988-02-25
JPH0571174B2 JPH0571174B2 (en) 1993-10-06

Family

ID=16230333

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61188817A Expired - Lifetime JPH0571174B2 (en) 1986-08-12 1986-08-12

Country Status (1)

Country Link
JP (1) JPH0571174B2 (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02117947A (en) * 1988-10-28 1990-05-02 Asahi Organic Chem Ind Co Ltd Curable composition
US5089863A (en) * 1988-09-08 1992-02-18 Mitsubishi Denki Kabushiki Kaisha Field effect transistor with T-shaped gate electrode
US5146291A (en) * 1988-08-31 1992-09-08 Mitsubishi Denki Kabushiki Kaisha MIS device having lightly doped drain structure
US5217913A (en) * 1988-08-31 1993-06-08 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing an MIS device having lightly doped drain structure and conductive sidewall spacers
US5254490A (en) * 1990-01-11 1993-10-19 Seiko Epson Corporation Self-aligned method of fabricating an LDD MOSFET device
US5371024A (en) * 1988-09-30 1994-12-06 Kabushiki Kaisha Toshiba Semiconductor device and process for manufacturing the same
US5441904A (en) * 1993-11-16 1995-08-15 Hyundai Electronics Industries, Co., Ltd. Method for forming a two-layered polysilicon gate electrode in a semiconductor device using grain boundaries
US5543646A (en) * 1988-09-08 1996-08-06 Mitsubishi Denki Kabushiki Kaisha Field effect transistor with a shaped gate electrode
US5559049A (en) * 1994-07-25 1996-09-24 Hyundai Electronics Insustries Co., Ltd Method of manufacturing a semiconductor device
JP2002532870A (en) * 1998-12-07 2002-10-02 インテル・コーポレーション Transistor with a notched gate
JP2005217245A (en) * 2004-01-30 2005-08-11 Toshiba Corp Semiconductor device and its manufacturing method
JP2009060104A (en) * 2007-08-31 2009-03-19 Samsung Electronics Co Ltd Finfet and manufacturing method thereof

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0740542U (en) * 1993-12-22 1995-07-18 積水化成品工業株式会社 Cushioning freshness holding sheet
JPH07251876A (en) * 1994-03-09 1995-10-03 Shin Nippon Chem Oonamento Kogyo Kk Underlay sheet for food

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54108582A (en) * 1978-02-15 1979-08-25 Toshiba Corp Manufacture of silicon type field effect transistor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54108582A (en) * 1978-02-15 1979-08-25 Toshiba Corp Manufacture of silicon type field effect transistor

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5146291A (en) * 1988-08-31 1992-09-08 Mitsubishi Denki Kabushiki Kaisha MIS device having lightly doped drain structure
US5217913A (en) * 1988-08-31 1993-06-08 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing an MIS device having lightly doped drain structure and conductive sidewall spacers
US5543646A (en) * 1988-09-08 1996-08-06 Mitsubishi Denki Kabushiki Kaisha Field effect transistor with a shaped gate electrode
US5089863A (en) * 1988-09-08 1992-02-18 Mitsubishi Denki Kabushiki Kaisha Field effect transistor with T-shaped gate electrode
US5834817A (en) * 1988-09-08 1998-11-10 Mitsubishi Denki Kabushiki Kaisha Field effect transistor with a shaped gate electrode
US5650342A (en) * 1988-09-08 1997-07-22 Mitsubishi Denki Kabushiki Kaisha Method of making a field effect transistor with a T shaped polysilicon gate electrode
US5471080A (en) * 1988-09-08 1995-11-28 Mitsubishi Denki Kabushiki Kaisha Field effect transistor with a shaped gate electrode
US5371024A (en) * 1988-09-30 1994-12-06 Kabushiki Kaisha Toshiba Semiconductor device and process for manufacturing the same
JPH02117947A (en) * 1988-10-28 1990-05-02 Asahi Organic Chem Ind Co Ltd Curable composition
US5254490A (en) * 1990-01-11 1993-10-19 Seiko Epson Corporation Self-aligned method of fabricating an LDD MOSFET device
US5441904A (en) * 1993-11-16 1995-08-15 Hyundai Electronics Industries, Co., Ltd. Method for forming a two-layered polysilicon gate electrode in a semiconductor device using grain boundaries
US5559049A (en) * 1994-07-25 1996-09-24 Hyundai Electronics Insustries Co., Ltd Method of manufacturing a semiconductor device
JP2002532870A (en) * 1998-12-07 2002-10-02 インテル・コーポレーション Transistor with a notched gate
JP2005217245A (en) * 2004-01-30 2005-08-11 Toshiba Corp Semiconductor device and its manufacturing method
JP4580657B2 (en) * 2004-01-30 2010-11-17 株式会社東芝 Semiconductor device and manufacturing method thereof
JP2009060104A (en) * 2007-08-31 2009-03-19 Samsung Electronics Co Ltd Finfet and manufacturing method thereof

Also Published As

Publication number Publication date
JPH0571174B2 (en) 1993-10-06

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