JPH0321074A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To assure high integration and a high operation speed by providing a p type gate electrode, and providing a buried type n type semiconductor region in a region surrounded by a pair of low concentration n type semiconductor regions. CONSTITUTION:A type gate electrode 12 is provided and a buried type n type semiconductor region 100 is provided. Hereby, a channel becomes a buried one to reduce surface dispersion of carriers due to unevenness of the boundary between a substrate 1 and an insulating film and hence increase the mobility of the carrier. Further, since there is provided a p<+> type semiconductor region 7, it is unnecessary to increase the concentration of the p<-> type well region 2 because of the reduction of punch-through even when high integration is contemplated, and hence concentration of the p<-> type well region 2 can be reduced. Accordingly, capacity formed between the p<-> type well region 2 and the channel is reduced, so that an electric field in the depth direction of the substrate 1 due to said capacitance is reduced to reduce dispersion of the carriers by the electric field and hence increase the mobility of the carrier. Hereby, high integration is contemplated along with a high speed operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device having an n-channel MISFET or a p-channel MISFET.

[Conventional technology]

Conventionally, in order to improve the mobility of carriers (electrons) in an n-channel MISFET, a p-type gate electrode is provided and a region surrounded by a pair of highly doped n-type semiconductor regions, which are a source region and a drain region. n-channel MISF with a buried n-type semiconductor region and a p-type gate electrode
ET has been proposed. This Yuzu technology is described in, for example, Science Forum Co., Ltd., published on November 28, 1980, Very LSI Device Hunt Book, pages 42 to 43.

Conventionally, as semiconductor integrated circuit devices become more highly integrated, punch-through or a decrease in threshold voltage occurs when the channel length becomes smaller. A source region and a drain region each formed of a type semiconductor region are provided, and in a region defined by the pair of highly doped n-type semiconductor regions, a p-type semiconductor is provided below the pair of lightly doped n-type semiconductor regions. An n-channel MTSFET has been proposed in which a region is provided and an n-type gate electrode is provided.

In addition, conventionally, n-channel MISFET and p-channel MISFET
Complementary MISFET where SFET is formed on the same substrate
In the above, it has been proposed that the conductivity type of the gate electrode of an n-channel MISFET is n-type, and the conductivity type of the gate electrode of a p-channel MISFET is p-type.

[Problem to be solved by the invention]

However, as a result of studying the above-mentioned prior art, the inventor found the following problems.

That is, in the conventional 1-channel MISFET described above, punch-through occurs as the channel length becomes smaller as semiconductor integrated circuit devices become higher quadrants. In order to reduce the occurrence of punch-through, increasing the impurity concentration of the p-type semiconductor substrate or p-type well region reduces the amount of depletion layer formed between the channel and the p-type semiconductor substrate or p-type well region. It is necessary to suppress the growth of Therefore, when the impurity concentration of the p-type semiconductor substrate or the p-type well region is increased, there is a problem that the current driving ability is reduced due to the substrate effect. Furthermore, there is a problem in that the electric field in the depth direction of the substrate increases, which makes carriers more likely to concentrate on the surface, and the mobility of carriers decreases due to surface scattering.

Furthermore, due to the work function difference between the p-type semiconductor substrate or p-type well region and the n-type gate electrode, a channel is formed on the surface of the p-type semiconductor substrate or p-type well region. There is a problem in that carriers are scattered due to the unevenness of the interface of the insulating film, and the mobility of the carriers 3-4 is reduced.

Furthermore, in the conventional complementary MISFET mentioned above,
Since the conductivity type of the gate electrode of an n-channel MISFET is different from that of the gate electrode of a P-channel MISFET, the conductive film constituting the gate electrode must be formed in the n-channel MISFET type region after or during shaping. In this method, the process of introducing or diffusing the n-type impurity into the conductive film and the process of introducing or diffusing the p-type impurity into the conductive film in the p-channel MISFET formation region need to be performed in separate processes, which increases the number of steps. There was a problem.

SUMMARY OF THE INVENTION An object of the present invention is to provide a technique that can achieve higher integration and higher speed in a semiconductor integrated circuit device having an n-channel MISFET.

Another object of the present invention is to provide a technique that can simplify the process in a semiconductor integrated circuit device having complementary MISFETs.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In a semiconductor integrated circuit device having an n-channel MISFET, a source region and a drain region configured of a pair of highly doped n-type semiconductor regions and a pair of lightly doped n-type semiconductor regions are provided on the main surface of the substrate, and A buried type n-type semiconductor is provided in a region defined by the pair of low concentration n-type semiconductor regions.
a p-type semiconductor region is provided below the pair of low-concentration 0-type semiconductor regions in a region defined by the pair of high-concentration n-type semiconductor regions, and a p-type gate electrode is provided. It is something that

Also, n-channel MISFET and p-channel MISFE
In a semiconductor integrated circuit device having complementary MISFETs formed on the same substrate, the n-channel MISFET
The conductivity type of the gate electrode of the FET is p-type, and the conductivity type of the electrodes of the p-channel MISFET is p-type.
It is made up of molds.

[For production]

In a semiconductor integrated circuit device having an n-channel MISFET, by providing a p-type gate electrode, the channel is formed inside the substrate due to the work function difference between the p-type gate electrode and the p-type semiconductor substrate or p-type well region. As a result, surface scattering of carriers due to irregularities at the interface between the substrate and the insulating film is reduced, and the mobility of the carriers is increased.

At the same time, by providing a buried n-type semiconductor region in a region surrounded by a pair of low concentration n-type semiconductor regions, the channel becomes a buried channel, and carriers move inside the substrate. Therefore, surface scattering of carriers due to unevenness at the interface between the substrate and the insulating film is reduced, and the mobility of carriers is increased. Therefore, together with the provision of the p-type gate electrode, the mobility of carriers increases.

Further, at the same time, a source region and a drain region composed of a pair of highly doped n-type semiconductor regions and a pair of lightly doped n-type semiconductor regions are provided on the main surface of the substrate, and the pair of high-concentration n-type semiconductor regions By providing a p-type semiconductor region under the pair of low-concentration n-type semiconductor regions in a region defined around the region, the high-concentration n-type semiconductor region and the p-type semiconductor substrate or p-type well region Since the elongation of the depletion layer formed during this process is reduced, the occurrence of punch-through is reduced. Therefore, even when the channel length becomes smaller due to higher integration, the impurity concentration of the p-type semiconductor substrate or p-type well region can be increased to connect the high-concentration n-type semiconductor region to the p-type semiconductor substrate or p-type well region. Since there is no need to reduce the extension of the depletion layer formed between the well region and the p
The impurity concentration of the type semiconductor substrate or the p-type well region can be lowered.

Furthermore, by lowering the impurity concentration of the p-type semiconductor substrate or p-type well region, the capacitance exerted between the p-type semiconductor substrate or p-type well region and the channel region becomes smaller, so the substrate effect can be reduced. 7 = 8- can be reduced, and the current rotation capacity can be increased.

Furthermore, since the electric field in the depth direction becomes smaller, the scattering of carriers becomes smaller and the mobility of carriers becomes larger. Therefore, by providing a P-type gate electrode and providing a buried n-type semiconductor region in a region surrounded by a pair of low concentration n-type semiconductor regions, the mobility of carriers increases. , it is possible to achieve higher integration and higher speed of a semiconductor integrated circuit device having an n-channel MISFET.

Furthermore, in a semiconductor integrated circuit device having complementary MISFETs, the conductivity type of the gate electrode of the n-channel MISFET is configured as p-type, and the conductivity type of the gate electrode of the p-channel MISFET is configured as p-type. , a step of introducing or diffusing an impurity into a conductive film forming a gate electrode in an n-channel MISFET formation region, and a step of introducing or diffusing an impurity into a conductive film forming a gate electrode in a formation region of a p-channel MISFET. Since this process can be performed in the same process, the process of manufacturing a semiconductor integrated circuit device having complementary MISFETs can be simplified.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be specifically described using the drawings.

In all the figures for explaining the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

FIG. 1 is a sectional view of a main part showing a schematic structure of an embodiment in which the present invention is applied to a complementary MI SFET.

As shown in FIG. 1, the complementary MI SFET includes a p-type semiconductor substrate 1. As shown in FIG. The element-shaped surface of the substrate is hereinafter referred to as the main surface.

The complementary MISFET is an n-channel MISFETQ
．． and a p-channel MISFET QP.

The space between each element is defined by an isolation region mainly composed of the p-type semiconductor substrate 1, the isolation film 20, and the channel stopper region 4.

The n-channel MISFETQN is the element ? It is provided on the main surface of the p-type well region 2 provided on the main surface of the p-type semiconductor substrate 1 in a region defined by the isolation insulating film 20 .

The n-channel MISFET QN has a gate electrode 1 and a gate electrode 1.
2. Gate insulating film 21. A pair of n' type semiconductor regions 8 and a pair of n1 type semiconductor regions 5 are provided which form a source region and a rain region. Also provided are a p type well region 2 which is a channel type region, a buried type n type semiconductor region 100 which forms a buried channel region, and a pair of p type semiconductor regions 7 for punch-through prevention.

The gate electrode 12 is, for example, a deposited polycrystalline silicon film 1.
0 and a high melting point metal silicide film l1. The polycrystalline silicon film 10 is doped with a p-type impurity such as B.
has been introduced. The high melting point metal silicide film 11 is made of, for example, W Si ■.

The gate insulating film 21 is composed of, for example, a silicon oxide film formed by oxidizing a substrate.

The pair of n-type semiconductor regions 8 and the pair of n-type semiconductor regions 5 forming the source region and the drain region are L D
D (Lj.ghtly Doped Drain)
It has a structure. Further, a wiring 14 is connected to one of the pair of n-type semiconductor regions 8 through a connection hole provided in an insulating film 25.

The n-type semiconductor region 100 is the n-type semiconductor region 5.
In the region defined around the p-type well region 2
is provided on the main surface of the

The P'' type semiconductor region 7 is provided below the n1 type semiconductor region 5 in a region surrounded by the n'' type semiconductor region 8.

The p-channel M I S F E T Q p includes:
Gate electrode 13, gate insulating film 21. An n-type well region 3 which is a channel type region, a pair of p-type semiconductor regions 9 and a pair of p-type semiconductor regions 6 forming a source region and a drain region are provided. Further, a buried n-type semiconductor region 101 for threshold voltage adjustment is provided.

The gate electrode 13 is made of, for example, a deposited polycrystalline silicon film 1.
It is composed of a laminated film of 0 and a high melting point metal silicide film l1. A p-type impurity such as B is introduced into the polycrystalline silicon film 10. The high melting point metal silicide film l1 is made of, for example, WSi2.

The gate #fA edge film 21 is made of, for example, a silicon oxide film formed by oxidizing a substrate.

A pair of p-type semiconductor regions 9 and a pair of p-type semiconductor regions 6 forming the source region and drain region are L D
D (Lightly D aped D rai
n) It has a structure. Further, a wiring 15 is connected to one of the pair of p' type semiconductor regions 9 through a connection hole provided in the insulating film 25.

The buried n-type semiconductor region 101 is provided on the main surface of the n-type well region a in a region defined by the pair of p-type semiconductor regions 6.

The insulating film 25 is for recording #I between each element and the wirings 14 and 15. The insulating film 25 is
For example, it is composed of a deposited silicon oxide film.

The wirings 14 and 15 are made of, for example, aluminum or an aluminum alloy.

Said #l! ! A passivation film 26 is provided on the edge film 25 and the wirings 14 and 15. The passivation film 26 is composed of, for example, a deposited silicon nitride film or a PSG (fossilicone glass) film.

Next, FIG. 2A (n-channel MISFET shown in FIG. 1)
2B (a diagram showing the impurity concentration distribution of the channel region of the n-channel MISFET QN shown in FIG. 2A), FIG. 2C (the n-channel MISFET shown in FIG. 2A) 2D (a diagram showing the energy band during operation of the channel region of MISFET QN) and FIG. 2D (a diagram showing the carrier distribution during operation of the channel region of n-channel MISFET QN shown in FIG. 2A) The functions and effects of each part of the channel MISFETQN will be explained.

The above-mentioned FIG. 2A shows the n-channel MIS F shown in the construction drawing.
Since this is an enlarged view of only E T Q N,
Detailed explanation will be omitted. Note that in FIG. 2A, the interlayer M edge film, wiring, etc. are not shown for ease of viewing the diagram.

Next, the n-channel MISFET of this embodiment
As shown in FIG. 2B, by providing a buried n-type semiconductor region 100, a region with a high concentration of n-type impurities (A in FIG. 2B) is formed on the substrate main surface side of the channel region.
). Since a large amount of electrons (carriers) exist in this region A, the channel is formed in this region A.
, the channel becomes an embedded channel.

Next, as shown in FIG. 2C, by providing the P-type gate electrode 12, energy is generated near the main surface of the substrate due to the work function difference between the p-type gate electrode 12 and the p-type well region 2. The band is curved and bends in both directions so that the channel is a buried channel. Further, by providing the buried n-type semiconductor region 100, the energy band is curved in the region A, so carriers are collected near this region A, and the channel becomes a buried channel.

Therefore, by providing the p-type gate electrode 12 and providing the buried n-type semiconductor region 100, the channel becomes a buried channel. Since the channel is a buried channel, the surface scattering of carriers due to unevenness at the interface between the substrate and the #I edge film is reduced, so that the mobility of the carriers is increased.

By providing the p-type gate electrode 12 and the n-type semiconductor region 100 in this way, as shown in FIG. 2D,
Since carriers exist in a region extending from the substrate surface to the n-type semiconductor region 100, the current flowing through the channel increases. That is, it is possible to improve the current driving ability of the n-channel MISFET.

Furthermore, since the p-type semiconductor region 7 is provided, even when high integration is achieved, there is no need to increase the concentration of the p-type well region 2 to reduce punch-through. The concentration in region 2 can be lowered. By lowering the concentration of the p-type well region 2, the capacitance formed between the p-type well region 2 and the channel becomes smaller, so the electric field in the depth direction of the substrate due to this capacitance becomes smaller. 151-161 depending on the electric field? Carrier scattering is reduced and carrier mobility is increased.

As explained above, the p-type gate 1/electrode 12 is provided, and the n
By providing the p-type semiconductor region 100 and the p-type semiconductor region 7, it is possible to achieve higher integration and higher speed of a semiconductor integrated circuit device having an n-channel MISFET.

In addition, FIG. 3 shows the n-channel MIS F shown in FIG.
The channel conductance versus gate voltage of E T Q N is shown. Here, the gate voltage is v0■■(v0
: gate voltage, vTo: threshold voltage).

Channel conductance indicates the ease with which current flows through a channel, that is, the mobility of carriers. In FIG. 3, a conventional n-channel MISFET is indicated by C, and an n-channel M:[SFET to which the present invention is applied is indicated by D. Third
As shown in the figure, according to the present invention, the conventional n-channel M
The channel conductance is approximately 30% larger than that of ISFET. That is, the mobility of carriers in the channel is increasing.

Next, FIG. 4A (p-channel MIS F shown in FIG. 1)
(Enlarged cross-sectional view of the main part showing the schematic structure of E T Q
(Figure showing the impurity concentration distribution of the channel region of p), 4th C
(band diagram during operation of the channel region of p-channel MISFET Q p shown in FIG. 4A), FIG. 4D (band diagram during operation of the channel region of p-channel MISFET Q p shown in FIG.
The operation and effects of the p-channel MISFET Q p of this embodiment will be described using the diagram (a diagram showing the distribution of carriers during operation of the channel region of the n-channel MISFET Q p shown in the figure).

FIG. 4A shows the p-channel MIS F shown in FIG.
Since only E T Q p is shown in an enlarged manner, detailed explanation will be omitted. Note that in FIG. 4A, interlayer insulating films, wiring, etc. are not shown for ease of viewing.

As shown in FIG. 4B, the p-channel MISFETQ of this embodiment has a buried n-type semiconductor region 101, so that a region with a high concentration of n-type impurities is formed on the substrate main surface side of the channel region. (region indicated by B in FIG. 4B), by using the p-type gate electrode 13, it is possible to reduce the threshold voltage from increasing to one side and make the threshold voltage close to zero. .

Next, as shown in FIG. 4C, by providing the p-type gate electrode 13, due to the work function difference between the p-type gate electrode 13 and the n-type well region 3, The energy band curves upward, so the channel becomes a surface channel. Since the channel becomes a surface channel, the distance between the gate electrode 13 and the channel becomes smaller, and the controllability of the channel by the gate electrode 13 improves, so the channel length can be reduced by achieving high integration. Even in this case, it is possible to reduce the show 1 channel effect such as a decrease in threshold voltage.

By providing the p-type gate electrode 13 in this way,
As shown in FIG. 4D, the carriers become distributed near the main surface of the substrate.

Next, FIGS. 5A to 5F (complementary MI shown in FIG. 1)
The method for manufacturing the complementary MISFET of the embodiment will be briefly described using cross-sectional views of main parts shown for each SFET manufacturing process.

First, the impurity concentration on the surface is, for example, 1×O15 to I
P-type semiconductor substrate 1 of approximately X 1 017 [cm”3]
Prepare.

Next, in the formation region of the n-channel MISFET QN, from the main surface of the p-type semiconductor substrate 1,
A p-type well region 2 is formed by introducing or diffusing p-type impurities.
form. After that, in the formation region of the p-channel MISFET Qp, from the main surface of the p-type semiconductor substrate 1,
An n-type impurity is introduced or diffused to form an n-type well region 3.

Next, the main surface of the substrate is selectively oxidized to form an inter-element isolation insulating film 2.
Shape 0. Further, in substantially the same process as forming the inter-element isolation insulating film 20, the inter-element isolation insulating film 20 is
A p-type channel header region 4 is formed at the bottom of the channel.

Next, the substrate is thermally oxidized to form a gate insulating film 21 as shown in FIG. 5A. The gate 1/insulating film 21 is made of, for example, a silicon oxide film. The gate insulating film 2
The film thickness of No. 1 is, for example, 11 to 13 [nml19-120].

Next, in the area defined by the element isolation IMA film 20, an n-type impurity, for example, As, is ion-implanted into a region of, for example, 6X10'' to 6X10''.
About 7 [cm-3] is introduced. The peak of ion implantation occurs when the depth from the main surface of the substrate is, for example, 0.04 to 0.0.
The area is 6 [μm].

Next, for example, a polycrystalline silicon film 10 is deposited. The thickness of the polycrystalline silicon film 10 is, for example, 25 to 35 [nm]. Thereafter, a p-type impurity such as B is introduced or diffused into the polycrystalline silicon film 10 to change the conductivity type of the polycrystalline silicon film 10 to p.
Make it into a mold. After this, as shown in FIG. 5B, the high melting point metal silicide film 11. For example, deposit WSi2. The film thickness of the high melting point silicide film 11 is, for example, 90 to 11
0 [nml.

Next, the laminated film of the polycrystalline silicon film 10 and the high melting point metal silicide film 11 is subjected to predetermined patterning to form gate electrodes 12 and 13, respectively. Next, thermally oxidize the substrate and #! The lamina 22 is shaped. The insulating film 22 is made of, for example, a silicon oxide film.

Next, in the n-channel M I S F E T Q +i formation region, using the insulating film 22 as a mask, a p-type impurity, for example, B, is implanted by ion implantation, for example, 5
X 1 016 to 5 X 1 0 1Il [cm-
3] Introduce a degree.

The peak of ion implantation is in a region where the depth from the main surface of the substrate is, for example, 0.14 to 0.16 C μm]. Thereafter, in the n-channel MISFET QN formation region, using the #l edge film 22 as a mask, an n-type impurity, such as P, is ion-implanted to form an impurity of, for example, 1×10 17 to I
About 101g [cm-3] is introduced.

The peak of ion implantation of n-type impurities is in a region shallower in depth from the main surface of the substrate than the peak of ion implantation of B mentioned above.

Next, as shown in FIG. 5C, the p-channel MIS F
E T Q In the p-type region, a p-type impurity such as B is introduced by ion implantation using the insulating film 22 as a mask.

Next, as shown in FIG. 5D, an insulating film 23 is formed using, for example, a deposited silicon oxide film. The thickness of the insulating film 23 is
For example, it is 140 to 160 [nm].

Next, the insulating film 23 deposited in the step shown in FIG. 5D
The site wall spacer 24 is formed by etching to a thickness corresponding to the film thickness.

Next, in the n-channel MISFETQN formation region, using the sidewall spacer 24 and the gate electrode 12 as a mask, an n-type impurity such as As is ion-implanted, for example, from 2X1019 to 2X.
10" [cm-31]. The peak of ion implantation is in the region where the depth from the main surface of the substrate is, for example, 0.14 to 0.16 [μm]. After this, the n-channel M
In the ISFETQN type region, using the sidewall spacer 24 and gate electrode 12 as a mask, an n-type impurity such as As is ion-implanted again, for example, from 3 x 1 019 to 3 x 1 0'' [cm-3].
Introduce degree. The peak of ion implantation is the first A
This region is shallower in depth from the main surface of the substrate than the peak of ion implantation of s.

In this way, n-channel M I S F E T Q
In the N formation region, by ion implanting an n-type impurity, for example, As, in two steps, an n-channel MI
Since a pair of n-type semiconductor regions 8 forming the source region and drain region of S F E T Q N are formed, the impurity concentration is high on the main surface side of the substrate, so that the resistance of the n-type semiconductor region 8 is low. The value can be lowered. At the same time, since the impurity concentration is low in the region where the n-type semiconductor region 8 and the p-type well region 2 are in contact, a depletion layer formed between the n-type semiconductor region 8 and the p-type well region 2 The growth of can be suppressed.

Next, as shown in FIG. 5E, the p-channel MISFET
In a QP type certain area, the side wall spacer 2
4 and the gate electrode 13 as masks, a p-type impurity such as B is introduced by ion implantation. This ion implantation is performed using the n-channel MISFET described above.
Similar to the As ion implantation performed in a certain region of the QN shape, the implantation is performed in two steps.

Next, by performing annealing for 15 to 25 minutes at, for example, 850 to 950°C,
A pair of n-type semiconductor regions 8 forming the source region and drain region of the n-channel MISFET QN, a pair of n-type semiconductor regions 5, a p-type semiconductor region 7, a buried n-type semiconductor region 100, A pair of p' type semiconductor regions 9 forming a source region and a drain region of the p channel MISFET Qp, a pair of P1 type semiconductor regions 6, and a buried n type semiconductor region 10
1 are formed.

Next, an insulating film 25 is formed using, for example, a deposited silicon oxide film.

Next, a contact hole reaching one of the pair of n' type semiconductor regions 8 of the n-channel MISFET QN is formed in the insulating film 25. Also, p-channel MISFET
A connection hole reaching one of the pair of p' type semiconductor regions 9 of Qp is formed in the insulating film 25.

Next, through the connection hole, the n-channel MISF E
The wiring 14 is formed so as to be directly connected to one of the pair of n' type semiconductor regions 8 of TQN. Further, the wiring l is connected directly to one of the pair of p-type semiconductor regions 9 of the P-channel MISFETQ through the connection hole.
Shape 5. The wirings 14 and 15 are formed of, for example, an aluminum film or an aluminum alloy film.

Next, a passivation film 26 is deposited. The passivation film 26 is made of, for example, a silicon nitride film or a PSG (fossilicone glass) film.

By the steps shown above, the complementary type M shown in FIG.
ISFET is perfect.

As explained above, according to this embodiment, n-channel M
The conductivity type of the polycrystalline silicon film 10 constituting the gate electrode l2 of the ISFET QN is p-type, and the gate electrode 13 of the p-channel MISFET Qp is configured. By configuring the conductivity type of the polycrystalline silicon film 10 as p-type, n-channel MISFETQ
A step of introducing or diffusing P-type impurities into the polycrystalline silicon film 10 forming the gate electrode 12 in the N formation region and a step of introducing or diffusing P-type impurities into the polycrystalline silicon film 10 forming the gate electrode 13 in a p-type region. Since the process of introducing or diffusing p-type impurities into the silicon film 10 can be performed in the same process, the process can be simplified.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

For example, in this embodiment, each semiconductor region is formed by annealing in the step shown in FIG. 5F, but it is also possible to perform annealing after introducing impurities forming each semiconductor region by ion implantation or the like. is also possible.

Further, in this embodiment, an example was shown in which a p-type well region and an n-type well region were provided on the main surface of the substrate, but it is also possible to provide only an n-type well region using a p-type substrate, or to provide an n-type well region on the main surface of the substrate. Of course, it is also possible to provide only the p-type well region using a substrate.

〔Effect of the invention〕

To briefly explain the effects obtained by the representative inventions disclosed in this application, they are as follows.In a semiconductor integrated circuit device having an n-channel MISFET, high integration and high speed are achieved. be able to.

Further, in a semiconductor integrated circuit device having complementary MISFETs, the process can be simplified.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a main part showing a schematic structure of an embodiment in which the present invention is applied to a complementary MISFET. FIG. 2A is a main part showing a schematic structure of an n-channel MISFET TQN shown in FIG. 2B is a diagram showing the impurity concentration distribution of the channel region of the n-channel MISF E T Q N shown in FIG. 2A, and FIG. 2C is a diagram showing the impurity concentration distribution of the n-channel MISF E T Q N shown in FIG.
Figure 2D is a diagram showing the energy band during operation of the channel region of TQN.
FIG. 3 is a diagram showing the distribution of carriers during operation in the channel region of TQN. Figure 4A shows the p-channel MISFETQ shown in the construction drawing.
FIG. 4B is an enlarged sectional view of main parts showing the schematic structure of FIG. 4A.
FIG. 4C is a diagram showing the impurity concentration distribution of the channel region of the p-channel MISF E T Q p shown in FIG.
FIG. 4D is a diagram showing the energy band during operation of the channel region of T Q p.
5A to 5F are cross-sectional views of essential parts of complementary MISFETs according to embodiments shown in each manufacturing process. In the figure, 1... p-type semiconductor substrate, 2... p-type well region, 3... n-type well region, 5... n-type semiconductor region, 6... p-type semiconductor region, 8...n-type semiconductor region, 7,9...p-type semiconductor region, 12.13...
Gate 1/electrode, 2/gate #l rim film. Figure 4A Figure 4C

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device having an n-channel MISFET, a source region including a pair of highly doped n-type semiconductor regions and a pair of lightly doped n-type semiconductor regions on the main surface of the substrate; A drain region is provided, and a buried n-type semiconductor region is provided in a region defined by the pair of low concentration n-type semiconductor regions, and a buried n-type semiconductor region is defined by the pair of high concentration n-type semiconductor regions. A p-type semiconductor region is provided below the pair of lightly doped n-type semiconductor regions in the
An n-channel MI characterized by having a type gate electrode.
A semiconductor integrated circuit device having SFET. 2. n-channel MISFET and p-channel MISFET
In a semiconductor integrated circuit device having complementary MISFETs formed on the same substrate, the n-channel MISFET
1. A semiconductor integrated circuit device having a complementary MISFET, characterized in that the conductivity type of the gate electrode of the ET is p-type, and the conductivity type of the gate electrode of the p-channel MISFET is p-type.