JPS61190983A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To inhibit a creeping to a channel forming region, and to suppress the variation of the threshold voltage of a MISFET by forming a LDD section to a gate electrode in a self-alignment manner and shaping a semiconductor region to the side section of a mask for introducing an impurity formed to the side section of the gate electrode in the self-alignment manner to the gate electrode. CONSTITUTION:A P-type impurity is introduced to the main surface section of a semiconductor substrate 1 in the lower section of a semiconductor region 5 in both side sections of a conductive layer 4 by using masks 6 for introducing the impurity shaped to both side sections of the conductive layer 4 after a process in which the semiconductor region 5 is formed, thus shaping P<+> type semiconductor regions 7. An N-type impurity is introduced to the main surface section of the semiconductor substrate 1 in both side sections of the conductive layer 4 by employing masks 8 for introducing the impurity formed to both side sections of the masks 6 for introducing the impurity, thus shaping N<+> type semiconductor regions 9. Since the semiconductor regions 7 in the lower sections of the semiconductor regions 5 as LDD sections are constituted by the masks 6 for introducing the impurity, a creeping to a channel forming region can be inhibited, thus suppressing the variation of the threshold voltage of a MISFET.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor integrated circuit device, and in particular to a technique that is effective when applied to a semiconductor integrated circuit device having an MI S FET.

[Background technology] In semiconductor integrated circuit devices, which are trending toward higher integration, M
ISFET reduces the electric field strength near the drain region,
Threshold voltage due to generation of hot carriers (Vsil+)
It is necessary to suppress fluctuations in Therefore, in order to reduce the electric field strength near the train region, 1. ν, I+channel M[5FET is LDD(1,jgbLly D
(opened drain) structure is adopted.

This means that between the 1-rain region and the channel forming region,
A semiconductor region (LDD portion) is provided which is of the same conductivity type as the 1-rain region, is electrically connected to it, and has a lower impurity concentration than the 1-rain region. This LDD portion makes the impurity concentration gradient between the train region and the channel forming region gentle.

Furthermore, since the impurity concentration in the LDD portion is lower than that in the drain region, the impurity concentration in the LDD portion is small, so that it is suitable for shortening the channel.

However, as higher integration progresses and the chai length becomes less than about 0.8 [μm], punch-through occurs between the source region 1 and the train region due to the coupling of the respective depletion regions. It becomes easier.

Therefore, in a MISFET with an LDD structure, it has been proposed to provide a semiconductor region of the opposite conductivity type (p" type) below the LDD part in order to form a pn junction with a high impurity concentration with the source region or train region. By 29,
The extension of the depletion region from the source region or the drain region is suppressed, thereby suppressing leakage current due to punch-through.

. The [,00 part and the semiconductor region below it are implanted using ion implantation technology using the gate electrode as a mask for introducing impurities.
It is formed by introducing type and p-type impurities and stretching and diffusing the impurities.

However, since the diffusion rate of p-type impurities is faster than that of n-type impurities, the P'-type semiconductor region wraps around the channel formation region, making it difficult to control the threshold voltage of the MISFET having the LDD structure.

Note that a semiconductor integrated circuit device having a MISFET with an LDD structure in which a semiconductor region of an opposite conductivity type is provided under the LDD section is, for example, IEDM 8229.6rA HA.
LF MICRON MOSFET USING DO
BLE INPLANTEDLDDJ p718-p7
It is described in 21.

[9! [Object of the present invention] An object of the present invention is to facilitate the control of the threshold voltage of a MISFET, suppress the extension of the depletion region from the source region or the train region, and suppress leakage current due to punch-through. The goal is to provide technology.

The above-mentioned and other objects and novel features of the present invention will become clear from the description of the Nihoncho letter and the accompanying drawings.

[Summary of the Invention] A brief outline of one typical invention disclosed in this application is as follows.

In other words, an M I S FET having an LDD structure in which a semiconductor region of the opposite conductivity type is provided under the LDD section.
, in the conductor collector circuit device, the LDD section is connected to data 1-
The semiconductor region is configured in self-alignment with the side of the electrode, and the semiconductor region is configured in self-alignment with the D1-electrode using a first impurity introduction mask provided on the side of the gate electrode, and the semiconductor region is configured in self-alignment with the electrode. drain area.

011 The second mask provided on the side of the first impurity introduction mask
Using an impurity introduction mask, the structure is self-aligned with the gate electrode.

This makes it possible to suppress the semiconductor region from wrapping around the channel forming region.

Fluctuations in the threshold voltage of the M r S FET can be suppressed, and leakage current due to punch-through can be suppressed.

Hereinafter, the configuration of the present invention will be explained along with examples.

[Example! ] FIG. 1 is a MISF for explaining embodiment i of the present invention.
1 is a sectional view of a main part of a semiconductor integrated circuit device having an ET.

It should be noted that in all the examples, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

In FIG. 1, l is a p-type semiconductor substrate.

A field insulating film 2 is provided on the upper main surface of the semiconductor substrate l between semiconductor elements.

Field insulating film 2 is configured to electrically isolate semiconductor elements. Furthermore, a p-type channel stopper region may be provided on the main surface of the semiconductor substrate l below the field insulating film 2.

3 is an insulating film, and the semiconductor 411 in the semiconductor element formation region
- Provided on the upper part of the main surface of temporary 1. The impurity 3 mainly constitutes the gate insulating film of the MI S FET.

Reference numeral 4 denotes a conductive layer, which is provided on a predetermined upper part of the insulating film 3. The conductive layer 4 mainly constitutes the gate electrode #@ of the MrSFET.

5 is an n-type semiconductor region (LDD part), and the conductor ff1
They are provided on the main surface of the semiconductor substrate 1 on both sides of ff4. The semiconductor region 5 constitutes a MISFET having an LDD structure. Semiconductor region 5 is configured in self-alignment with conductive layer 4 .

! In addition, the conductor region 5 is configured to alleviate the impurity concentration gradient at the p11 junction between the substantial drain region and the channel forming region, and to alleviate the electric field strength. Thereby, it is possible to suppress the generation of hot carriers and to suppress the change in the threshold voltage of the 1MrsFET over time.

6 is a mask for impurity introduction, and on both sides of the conductive layer 4,
It is provided above the semiconductor region 5 with an insulating film 3 interposed therebetween. The impurity introduction mask 6 defines a semiconductor region provided below the semiconductor region 5.

The impurity introduction mask 6 is constituted by a conductive layer electrically connected to the conductive layer 4, and includes the semiconductor region 5 and the insulating film 3.
The gate electrode of the MIS structure is configured together with the gate electrode. That is, when a predetermined potential is applied to the conductive layer 4, an inversion layer is formed on its main surface.
The resistance value of semiconductor region 5 can be reduced. As a result, the MISFET due to the provision of the semiconductor region 5
It is possible to suppress a decrease in mutual conductance between the source region and the drain region of the semiconductor device, thereby increasing the operating speed.

Note that as the impurity introduction mask 6, it is also possible to use a mask formed using an insulator such as a silicon oxide film, a silicon nitride film, or the like.

Reference numeral 7 denotes a p-type semiconductor region, which is provided on the main surface of the semiconductor substrate FF1f below the semiconductor region 5.

The semiconductor region 7 is configured to suppress the extension of a depletion region formed in the semiconductor substrate 1 (channel formation region) from the pnFjj junction of the source region or train region of the MI SFE'T and the semiconductor substrate 1. There is.

That is, it is configured to suppress bunch-through between the source region and the drain region. by this,
Since the channel length can be shortened, M I S
It is possible to shorten the FET channel.

The semiconductor region 7 has a conductive layer ``!i'' with respect to the channel forming region.
A mask 6 for impurity introduction provided outside the layer 4 is used to self-align with the conductive layer 4. As a result, the semiconductor region 7 made of p-type impurities whose diffusion rate is faster than that of n-type impurities is configured to surround the semiconductor region 5, but it is possible to suppress the impurity from going around to the channel formation region. That is, it is possible to suppress fluctuations in the threshold voltage of the MISFET and to suppress deterioration of the electrical characteristics of the semiconductor integrated circuit device.

8 is a mask for introducing impurities; mask 6 for introducing impurities;
They are provided on both sides of the conductive layer 4 with the conductive layer 4 interposed therebetween. The impurity introduction mask 8 is configured to form a substantial source region or drain region of the MI S FET in self-alignment with the conductive layer 4.

The impurity introduction mask 8 is made of an insulating film.

9 is an n° type semiconductor region, and an impurity introduction mask 6
．． They are provided on the main surface of the semiconductor substrate l on both sides of the conductive layer 4 via the conductive layer 8 . The semiconductor region 9 is.

It constitutes a substantial source region or drain region of the MISFET. The semiconductor region 9 serving as the drain region is electrically connected to the semiconductor region 5 serving as the LDD portion, and has a higher impurity concentration than the semiconductor region 5.

MISFET consists of a semiconductor substrate l, an insulating film 3, a conductive layer 4.
Semiconductor region 9 serving as a source region or drain region, LD
It is constituted by a semiconductor region 5 which becomes part D and a semiconductor region 7 which suppresses bunch-through between the source region and the drain region.

10 is an insulating film provided to cover the semiconductor element, 11
is a contact hole formed by removing the insulating film 3.10 above the predetermined semiconductor region 9.

A conductive layer 12 is provided extending over a predetermined upper part of the insulating film 10 so as to be electrically connected to a predetermined semiconductor Xt+ or 9 through the connection hole 11.

Next, regarding the specific manufacturing method of this example.

Explain briefly.

FIGS. 2 to 4 are sectional views of essential parts of a semiconductor integrated circuit device having a MISFET in each manufacturing process for explaining the manufacturing method of Example 2 of the present invention.

First, a field insulating film 2 and an insulating film 3 are formed on a semiconductor substrate 1.

Then, a conductive layer 4 is formed on a predetermined upper part of the insulating film 3.

The conductive layer 4 is made of, for example, a polycrystalline silicon film, a high melting point metal (
M o , T J , T i , W ) film, silicide (MoSi2.TaSi□, TjSi2r WSi
2) Formed with a film or a combination thereof.

Next, II is applied to the main surface of the semiconductor substrate 1 on both sides of the conductive layer 4.
TJ:! As shown in Figure 2, r
An I-type semiconductor region 5 is formed. The semiconductor region 5 is formed, for example, by using the conductive layer 4 and the field insulating film 2 as a mask for impurity introduction, and by stretching and diffusing phosphorus ions introduced by ion implantation technology.

After the step of forming semiconductor region 5 shown in FIG. 2, impurity introduction masks 6 are formed on both sides of conductive layer 4. The impurity introduction mask 6 is formed, for example, by applying an anisotropic etching technique to a polycrystalline silicon film formed by a CVD technique.

Then, using the impurity introduction mask 6, a P type impurity is introduced into the main surface of the semiconductor substrate 1 under the semiconductor region 5 on both sides of the conductive layer 4, and as shown in FIG. A semiconductor region 7 is formed. The semiconductor region 7 is formed, for example, by stretching and diffusing boron ions introduced by an ion implantation technique.

After the step of forming the semiconductor region 7 shown in FIG. 3, impurity introduction masks 8 are formed on both sides of the impurity introduction mask 6. The impurity introduction mask 8 is formed, for example, by applying an anisotropic etching technique to a silicon oxide film formed by a CVD technique.

Then, using an impurity introduction mask 8, an n-type impurity is introduced into the main surface of the semiconductor substrate l on both sides of the conductive layer 4 to form an n-type semiconductor region 9, as shown in FIG. .

The semiconductor region 9 is formed, for example, by stretching and diffusing arsenic ions introduced by ion implantation technology.

After the step of forming semiconductor region 9 shown in FIG. 4, insulating film 10, connection hole 11, and conductive layer 12 are formed to complete the semiconductor integrated circuit device of this embodiment.

As described above, according to the present embodiment (2), by configuring the semiconductor region 7 below the semiconductor region 5 that becomes the LDD portion with the mask 6 for introducing impurities, it is possible to suppress the doping from entering the channel forming region. MISFE
Variations in the threshold voltage of T can be suppressed. Thereby, deterioration of the electrical characteristics of the semiconductor integrated circuit device can be suppressed.

Also, on the upper part of the semiconductor region 5 which becomes the LDD section.

By providing a conductive impurity introduction mask that is electrically connected to the conductive layer 4 via the insulating film 3, an inversion layer is formed on the main surface thereof, so that the resistance value of the semiconductor region 5 can be reduced. can be reduced. As a result, the mutual conductance between the semiconductor regions 9 serving as the source region or the drain region can be improved, so that the operating speed of the semiconductor integrated circuit device can be increased.

[Example 2] This example 2 describes another example of suppressing a decrease in mutual conductance of an MI S FET having an LDD structure.

FIG. 5 is an M I for explaining the embodiment
1 is a sectional view of a main part of a semiconductor integrated circuit device having an S FET.

In FIG. 5, reference numeral 13 denotes an n-type semiconductor region, which is provided on the main surface of the semiconductor substrate l in an intervening area between the semiconductor region 5 and the semiconductor region 7, and is electrically connected to the semiconductor region 5 and the semiconductor region 9. It is being The semiconductor region 13 constitutes a current path flowing between the semiconductor regions 9 instead of a part of the semiconductor region 5 that becomes the LDD section. As a result, the current flowing between the semiconductor regions 9 flows through the semiconductor region 13 having a smaller resistance value instead of through a part of the semiconductor region 5, so that a decrease in mutual conductance can be suppressed. That is, the operating speed of the semiconductor integrated circuit device can be increased.

Next, a specific manufacturing method of Example 2 will be explained.

FIG. 6 is a sectional view of a main part of a semiconductor integrated circuit device having an MISFET in a predetermined manufacturing process for explaining the manufacturing method of Example 2 of the present invention.

After the step of forming the semiconductor region 5 of Example 1, an impurity introduction mask 6 is formed. This impurity introduction mask 6 may be formed of a conductive layer or an insulating film.

Thereafter, using the impurity introduction mask 6, n-type and p-type impurities are introduced into the main surface of the semiconductor substrate 1.

As shown in FIG. 6, semiconductor regions 7 and 13 are formed.

After the step of forming semiconductor regions 7 and 13 shown in FIG. 6, the steps after the step shown in FIG. 3 of the embodiment I are performed to complete the semiconductor integrated circuit device of this embodiment.

As explained above, according to the first embodiment (2), substantially the same effects as those of the above-mentioned embodiment I can be obtained.

Further, by configuring the current path flowing between the semiconductor regions 9 with the semiconductor region 13 having a small resistance value instead of a part of the semiconductor region 5, the mutual conductance of the MISFET can be improved.

〔effect〕

As explained above, according to the novel technology disclosed in this application, the following effects can be obtained.

(1) In a semiconductor integrated circuit device having an LDD structure MISFET in which a semiconductor region of an opposite conductivity type is provided below an LDD portion, the LDD portion is provided in self-alignment with respect to a gate electrode, and the semiconductor region is By providing self-alignment with the gate electrode on the side of the impurity introduction mask provided on the side of the MISFE, it is possible to suppress C1+ from entering the channel formation region.
Fluctuations in the threshold voltage L of T can be suppressed.

(2) According to the previous work (1), the threshold value of MfSFET'
! ! Leakage current due to punch-through can be suppressed while suppressing fluctuations in LL.

(3) By forming the impurity introduction mask with a conductive layer electrically connected to the gate electrode, an inversion layer can be formed on its main surface, thereby reducing the resistance value of the LDD section. can do.

(4) According to (3) above, the mutual conductance between the source region and the drain region can be improved, so that the operating speed of the semiconductor integrated circuit device can be increased.

(5) At an intervening portion between the LDD portion and the semiconductor region.

By providing a semiconductor region that electrically connects the LDD portion to the source region or the drain region and has a higher impurity concentration than the LDD portion as a current path.

Mutual conductance between the source region and the train region can be improved.

(6) According to (5) above, the operating speed of the semiconductor integrated circuit device can be increased.

Although the invention made by the present inventor has been specifically explained in the above embodiments, the present invention is as follows.

It goes without saying that the invention is not limited to the embodiments described above, and that various modifications may be made without departing from the spirit thereof.

For example, in the above embodiment, the source region or the drain region of the MI S FET and the semiconductor region of the opposite conductivity type below the LDD section were formed in different manufacturing processes, but the same impurity introduction mask was used and the same It may be formed in the manufacturing process.

[Brief explanation of the drawing]

FIG. 1 is an MTSF diagram for explaining the embodiment
FIG. 1 is a cross-sectional view of a main part of a semiconductor integrated circuit device having an ET. 2 to 4 are cross-sectional views of main parts of a semiconductor integrated circuit device having a MISFET in each manufacturing process for explaining the manufacturing method of Example i of the present invention, and FIG. FIG. 6 is a cross-sectional view of a main part of a semiconductor integrated circuit device having an MISFET for explaining (1). FIG. 1 is a cross-sectional view of a main part of a semiconductor integrated circuit device. In the figure, ■: semiconductor substrate, 2: field insulating film. 3, IO...Insulating film, 4.12... Conductive layer, 5,7,
9゜13...Semiconductor region, 6,8...Mask for impurity introduction, 11...Connection hole. Figure 1 Figure 2/(P Figure 3/(P- Figure 4/(p-) Procedural amendment (method) % formula % Name of the invention Semiconductor integrated circuit device Amendment person and 1 Rei Patent applicant name Ya '51Q1 Co., Ltd. Hitachi Manufacturing Company fee
[IEDM
8229.6 rA HALF MICRONMO8
FET USING DOBLE INPLANTE
DLDDJ is replaced with “IED
M), 1982, A HALF MICRONMO8FE using 29.6r' double ion implanted L.D.
T USING DOUBLE IMPLANTE
DLDD) Correct to JJ.

Claims (1)

[Claims] 1. The first region used as a source region or a drain region
electrically connected between the first semiconductor region of the conductivity type and the channel forming region, having the same conductivity type as the first semiconductor region;
Further, a second semiconductor region having an impurity concentration lower than that of the first semiconductor region is provided, and a second semiconductor region is provided below the second semiconductor region.
MISF configured by providing a third conductive type semiconductor region
A semiconductor integrated circuit device having an ET, wherein the second semiconductor region is self-aligned with respect to the gate electrode, and the third semiconductor region is formed using an impurity introduction mask provided on a side of the gate electrode. A semiconductor integrated circuit device, characterized in that the gate electrode is provided in self-alignment with respect to the gate electrode. 2. The semiconductor integrated circuit device according to claim 1, wherein the first impurity introduction mask is composed of a conductive layer. 3. The first impurity introduction mask is composed of a conductive layer or an insulating film, and the second impurity introduction mask is composed of an insulating film. The semiconductor integrated circuit device described above. 4. Electrically connected to the intervening portion between the second semiconductor region and the third semiconductor region with the same conductivity type as the first semiconductor region and the second semiconductor region, and from the second semiconductor region. 2. The semiconductor integrated circuit device according to claim 1, further comprising a fourth semiconductor region having a high impurity concentration.