JPS61125084A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the degree of integration, by providing a gate electrode in a small hole or a small groove in a semiconductor substrate, providing a substantial source or drain region on both sides of the gate electrode, providing a source or drain region beneath said region, and constituting a MISFET having an LDD structure. CONSTITUTION:On a p<-> type semiconductor substrate 1, a field insulating film 2 and a p type channel stopper region 3 are formed. Thereafter, a small hole 4 is formed. Then, an insulating film 5 is formed on the upper part of the main surface of the semiconductor substrate 1, which is to becomes a semiconductor element forming region. A conducting layer 6 is formed on the upper part of the main surface of the semiconductor substrate 1 along the small hole 4 through the insulating film 5. On the main surface parts of the semiconductor substrate 1 on both end parts of the conducting layer 6, n<-> type semiconductor regions 8 are formed in order to form an LDD part. On the main surface parts of the semiconductor regions 8, n<+> type semiconductor regions 7 are formed in order to form a substantial source or drain region. Then an insulating film 9, connecting holes 10 and conducting layers 11 are formed. Thus the occupying area of the MISFET can be reduced, and the degree of integrating can be enhanced.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a semiconductor integrated circuit device, and in particular to an insulated gate field effect transistor (hereinafter referred to as 1MrS).
The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device equipped with a FET (FET).

[Background Art] In order to suppress the short channel effect caused by high integration, MISFETs constituting semiconductor integrated circuit devices are
D D (Light, lydan opedan rain)
structure. This MISFET is provided with a semiconductor region (LDD region) having a lower impurity concentration than the substantial source or drain region and the region where the channel is formed.

The semiconductor region becomes a part of the source region or the drain region, and the diffusion distance of impurities to the region where the channel is formed is small, so that the effective channel length can be sufficiently maintained. Further, since the semiconductor region forms a pn junction with a low impurity concentration with the semiconductor substrate or well region, the electric field strength near the drain region can be relaxed and hot carriers can be suppressed.

However, as a result of studies on this technology, the present inventor found that in order to form an MIS FET with an LDD structure, it is necessary to form impurity introduction masks on both sides of the gate electrode, so that the area in the channel length direction is It has been found that the problem is that this increases the density and hinders the degree of integration.

In addition, the present inventor believes that since the impurity concentration in the semiconductor region is low and reduces the transconductance (gm), the MI
We have discovered a problem in that the driving ability of SFET is reduced.

Note that a method for manufacturing a semiconductor integrated circuit device equipped with an MI S FET having an LDD structure is disclosed in, for example, Japanese Patent Laid-Open No. 57-97.
It is described in Publication No. 676.

[Object of the Invention] An object of the present invention is to provide a technique that can improve the degree of integration in a semiconductor integrated circuit device equipped with an M r S FET.

Another object of the present invention is to provide a technique capable of improving the driving ability of the MI S FET in a semiconductor integrated circuit device equipped with the MI S FET.

The above and other objects and novel features of the present invention will become clear from the description in Book Ra and the accompanying drawings.

[Summary of the Invention] □ A brief overview of typical inventions disclosed in this application is as follows.

That is, pores or narrow grooves are provided in the semiconductor substrate.

A gate electrode is provided in the pore or narrow groove, and a substantial source region or drain region is provided on the main surface of the semiconductor substrate on both sides of the gate electrode, and on the main surface of the semiconductor substrate below the source region or drain region,
A source region or a drain region that becomes an LDD section is provided to
A DD structure MTSFET is constructed.

As a result, the LDD section can be configured within the area required for a substantial source region or drain region.
The area occupied by the MISFET can be reduced and the degree of integration of the semiconductor integrated circuit device can be improved.

Furthermore, since a channel can be formed in the main surface of the LDD section by the gate electrode, a decrease in transconductance between the source region and the drain region can be suppressed, and the driving ability of the MISFET can be improved.

Hereinafter, the configuration of the present invention will be explained along with one embodiment.

[Embodiment] FIG. 1 is a plan view of a main part of a semiconductor integrated circuit device equipped with an MI S FET of an LDD structure for explaining an embodiment of the present invention, and FIG. It is a sectional view taken along the -■ cutting line. In FIG. 1, insulating films other than the field insulating film provided between each conductive layer are not shown in order to make the structure easier to understand.

In addition, in all the figures of the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

In FIGS. 1 and 2, 1 is a p-type semiconductor substrate (or P'' type well region) made of single crystal silicon;
2 is a field insulating film, 3 is a p-type channel stopper region provided under the field insulating film 3; 4 is a pore (or narrow groove) in the semiconductor substrate l in the MI S FET formation region; It is provided on the main surface.

The pore 4 is mainly for burying the gate electrode of the MI S FET.

Reference numeral 5 denotes an insulating film, which is provided at least along the pores 4 and above the main surface of the semiconductor substrate 1 . This absolute #C film 5 is
This is for configuring the gate insulating film of MISFET.

A conductive layer 6 is provided on the upper main surface of the semiconductor substrate 1 along the pore 4 with an insulating film 5 interposed therebetween. This conductive layer 6 is for configuring the gate electrode of the MI S FET.

Reference numeral 7 denotes an n+ type semiconductor region, which is provided on the main surface of the semiconductor substrate l on both sides of the conductive layer 6.

``This semiconductor region 7 is for forming a substantial source region or drain region of MrSFET.

Reference numeral 8 denotes a low-type semiconductor region, which is located on the main surface of the semiconductor substrate 1 on both sides of the conductive layer 6, electrically connected to the semiconductor region 7, and provided under the semiconductor region 7. This semiconductor region 8 is provided in connection with a region where a channel is formed,
This is for configuring an LDD section used as a part of the source region or drain region of the MISFET.

The MI S FET manufactured by LDDJit mainly consists of a semiconductor substrate 1, a pore 4, an insulating film 5. It is composed of a conductive layer 6, a pair of semiconductor regions 7, and a pair of semiconductor regions 8.

In this M [S FET, a semiconductor region 8 which becomes an LDD section is provided below a semiconductor region 7 which becomes a substantial source region or a drain region, so the latter can be constructed within the area required for the former. In particular, since the area occupied by the MISFET in the channel length direction can be reduced, the degree of integration of the semiconductor integrated circuit device can be improved.

Furthermore, since the semiconductor region 8 serving as the LDD section has an MIS structure in which a conductive layer 6' is provided with an insulating film 5 interposed therebetween, a channel is formed on the main surface of the semiconductor region 8 by the conductive layer 6. be able to. This makes it possible to reduce the resistance value of the semiconductor region 8, thereby suppressing a decrease in transconductance between the source region and the drain region, and improving the driving ability of the MISFET.

Furthermore, between the semiconductor regions 7 or between the semiconductor regions 8.

A conductive layer 6 embedded in the pores 4 is provided with an intervening conductive layer 6,
The distance between them within the semiconductor substrate 1 is set to be long. Thereby, unnecessary coupling between the depletion regions formed inside the semiconductor substrate 1 from the source region or the drain region can be suppressed, and punch-through can be prevented.

Reference numeral 9 denotes an insulating film, which is provided to cover semiconductor elements such as MISFETs. 1O is a connection hole, which is provided by removing the insulating film 9.5 above the predetermined semiconductor region 7.

11 is a conductive layer, which connects the semiconductor region 7 through the connection hole lo.
It is provided so as to be electrically connected to and extend over the insulating film 11.

Next, the specific manufacturing method of this example will be briefly explained.

FIGS. 3 to 5 show M t of the LDD structure in each manufacturing process for explaining the manufacturing method of one embodiment of the present invention.
1 is a sectional view of a main part of a semiconductor integrated circuit device including an S FET.

First, a P-type semiconductor substrate 1 is prepared, and as shown in FIG. 3, a field insulating film 2 and a P-type channel stopper region 3 are formed.

After the step of forming field insulating film 2 and channel stopper region 3 shown in FIG. 3, pores 4 are formed. The pores 4 are formed by, for example, using anisotropic etching technology to have a width in the gate length direction of about 0.8 to 1.5 [μm] and a depth of about 0.7 to 1.0 [μm]. Form.

Thereafter, an insulating film 5 is formed on the upper main surface of the semiconductor substrate l, which will be a semiconductor element formation region. This insulating film 5 is, for example, a silicon oxide film formed by thermal oxidation technology.

As shown in FIG.
A conductive layer 6 is formed with the conductive layer 6 interposed therebetween. This conductive layer 6 is made of, for example, a polycrystalline silicon film formed by a CVD technique in which phosphorus is diffused in order to reduce the resistance value.

Moreover, the conductive M6 is a high melting point metal film (M o , T i
, T a , W ), silicide film (MoSi
2. TiSi2. TaSi2. WSi2) or a polycide film in which a silicide film is provided on top of a polycrystalline silicon film may be used.

After the step of forming the conductive layer 6 shown in FIG.
On both sides of the main surface of the semiconductor substrate 1, n-type semiconductor regions 8 are formed to form an LDD section. In this semiconductor region 8, for example, a predetermined dose of arsenic ions is introduced by ion implantation technology, and stretched and diffused to a junction depth x j ) of about 0.6 to 0.8 [μm]. Form.

Then, as shown in FIG. 5, an n-type semiconductor region 7 is formed on the main surface of the semiconductor region 8 in order to form a substantial source or drain region. This semiconductor region 7 is made by introducing, for example, a predetermined dose of arsenic ions or phosphorus ions using ion implantation technology, and then performing stretching diffusion to achieve a junction depth xj) of approximately 0.3 to 0.5 [μm]. to form.

After the step of forming the semiconductor region 7 shown in FIG. 5, as shown in FIGS.
By forming the conductive layer 11, the semiconductor integrated circuit device of this embodiment is completed. Note that, after this, a treatment process such as a protective film may be performed.

[Effects] As explained above, according to the novel technology disclosed in this application, the following effects can be obtained.

(1) A pore or a narrow groove is provided in a semiconductor substrate, a gate electrode is provided in the pore or narrow groove, and a substantial source region and a drain region are formed on the main surface of the semiconductor substrate on both sides of the gate electrode. A source region and a drain region which will become an LDD part are provided on the main surface of the semiconductor substrate under the
By configuring the ISFET, it is possible to configure the LDD portion within the area substantially required for the source region or drain region.

(2) According to (1) above, the area occupied by the MISFET can be reduced, so the degree of integration of the semiconductor integrated circuit device can be improved.

(3) According to (1) above, since the LDD section has an MIS structure in which the gate electrode is provided with an insulating film interposed therebetween, a channel can be formed on the main surface of the LDD section by the gate electrode.

(4) According to (3) above, the resistance value of the LDD section can be reduced, suppressing the decrease in transconductance between the source region and the drain region, and increasing the M I S
The driving ability of the FET can be improved.

(5) According to (2) and (4) above, MI of LDD structure
In a semiconductor integrated circuit device including an SFET, the degree of integration thereof can be improved, and the driving ability of the MISFET can be improved.

The invention made by the present inventor has been specifically explained in the above embodiments, but one aspect of the present invention is as follows.

It goes without saying that the invention is not limited to the embodiments described above, and that various modifications may be made without departing from the spirit thereof.

For example, in the MISFET of the above embodiment, an example has been described in which the source region or the drain region which becomes the LDD section is provided substantially over the entire lower part of the source region or the drain region. It may be provided.

[Brief explanation of drawings]

FIG. 1 is a plan view of a main part of a semiconductor integrated circuit device equipped with an LDD structure MI S FET for explaining one embodiment of the present invention. FIG. A cross-sectional view. FIGS. 3 to 5 show the M I of the LDD structure in each manufacturing process for explaining the manufacturing method of one embodiment of the present invention.
1 is a sectional view of a main part of a semiconductor integrated circuit device including an S FET. In the figure, l: semiconductor substrate, 2: field insulating film, 3: channel stopper region, 4: pore, 5.
9...-insulating film, 6.11... conductive layer, 7,8...
Semiconductor region, 10... Connection hole. Figure 1 Figure 2 Figure 4 Figure 5

Claims (1)

[Claims] 1. A pore or a narrow groove is provided in the main surface of a first semiconductor region of a first conductivity type that is electrically isolated from other regions, and a pore or a narrow groove is provided along the pore or narrow groove. A conductive layer is provided above the main surface of the first semiconductor region via an insulating film, and second semiconductor regions of a second conductivity type are provided on the main surface of the first semiconductor region on both sides of the conductive layer. A second semiconductor region is provided, and is electrically connected to the main surface of the first semiconductor region under the second semiconductor region and has the same conductivity type as the second semiconductor region, and has a lower impurity concentration than the second semiconductor region. What is claimed is: 1. A semiconductor integrated circuit device comprising three semiconductor regions forming an insulated gate field effect transistor. 2. The second semiconductor region and the third semiconductor region are used as a source region or a drain region, and the conductive layer is used as a gate electrode, according to claim 1. semiconductor integrated circuit devices. 3. The semiconductor integrated circuit device according to claim 1, wherein the third semiconductor region is connected to a region where a channel is formed. 4. The semiconductor integrated circuit device according to claim 1, wherein the conductive layer is provided to be interposed between the third semiconductor regions.