JPH06105715B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effectively applied to a semiconductor integrated circuit device having a MISFET having an LDD (Lightly Doped Drain) structure. Is.

[Background Art] In MISFETs constituting a semiconductor integrated circuit device, the electric field strength near the drain region is increased due to scale down due to high integration, so that hot carriers are significantly generated. The hot carriers are trapped at the interface between the semiconductor substrate and the gate insulating film, and the threshold voltage (Vth) changes with time.

Therefore, an MISFET having an LDD structure in which a semiconductor region (LDD portion) having the same conductivity type as that of the drain region and an impurity concentration lower than that is provided between the drain region and the channel formation region is adopted. The LDD portion is configured to be self-aligned with the gate electrode by using an insulating film formed in the same manufacturing process as the gate electrode and the gate insulating film as a first impurity introduction mask. The source region or the drain region is formed by self-aligning a second impurity introduction mask (sidewall) on both sides of the gate electrode and using the second impurity introduction mask. It

In addition, the MISFET having the LDD structure is suitable for shortening the channel because the LDD portion having a low impurity concentration can prevent the LDD portion from sneaking into the channel formation region and sufficiently secure the effective channel length.
In order to further promote the shortening of the channel, it is necessary to make the junction depth of the LDD portion shallow. Therefore, the LDD portion is formed by introducing impurities so as to have the maximum impurity concentration in the first impurity introduction mask. Therefore, LD
The D part is configured to have the maximum impurity concentration on its main surface.

However, as a result of the study by the present inventor, it has been found that hot carriers are easily trapped in the interface portion formed between the LDD portion and the second impurity introduction mask. This is because the extension of the depletion region becomes large in the LDD portion on the drain region side, and the maximum electric field intensity is generated under the second impurity introduction mask, that is, outside the gate electrode. Further, since the gate electrode is processed by the dry etching technique, the surface portion of the first impurity introduction mask is roughened.

Therefore, due to the field effect of hot carriers, the series resistance of the LDD section increases or the field effect movement of carriers decreases, so the current between the source region and the drain region decreases, and the MISFET of the LDD structure is reduced. Causes a problem of deterioration of electrical characteristics.

Regarding the MISFET having the LDD structure, for example, "IEEE TRANSACTIONS ON ERECTRON DEVICE (IEEE TRANSACTIONS ON ERECTRON DEVICE)
S), VOL.ED-27, p1359 to p1367, NO.8, AUGUST 1980. ".

[Object of the Invention] An object of the present invention is to provide a technique capable of suppressing deterioration of electrical characteristics in a semiconductor integrated circuit device having an LDD structure MISFET.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[Outline of the Invention] The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.

That is, in the main surface portion of the semiconductor substrate between the first semiconductor region forming the source region and the drain region and the channel forming region, the same conductivity type as that of the first semiconductor region and an impurity concentration higher than that of the first semiconductor region. In a method of manufacturing a semiconductor integrated circuit device having a MISFET having a second semiconductor region having a low LDD structure, a gate electrode is formed on an upper surface of a main surface of a first conductivity type semiconductor substrate via an insulating film serving as a gate insulating film. Forming a second conductive type second semiconductor region on the main surface portion of the semiconductor substrate in a self-aligned manner with the conductive layer, and forming a second conductive type second semiconductor on the main surface of the semiconductor substrate. A third semiconductor region of a first conductivity type having a higher impurity concentration than that of the semiconductor substrate and one end of which does not extend closer to the channel formation region than one end of the second semiconductor region; Conductive layer And a step of forming a mask for introducing impurities on both sides of the conductive layer in a self-aligned manner with respect to the conductive layer, and then forming the second surface on the main surface portion of the semiconductor substrate. Forming a first semiconductor region having the same conductivity type as that of the semiconductor region and having an impurity concentration higher than that of the second semiconductor region in a self-aligned manner with respect to the impurity introduction mask.

This allows a current between the source region and the drain region to flow in the deep portion of the LDD portion, so that the influence of the electric field effect of hot carriers trapped unnecessarily can be suppressed. As a result, a decrease in mutual conductance can be suppressed, and thus deterioration in electrical characteristics can be suppressed.

Hereinafter, the structure of the present invention will be described with reference to examples and examples.

Reference Example 1 FIG. 1 is a sectional view of a main part of a semiconductor integrated circuit device having an LDD-structured MISFET for explaining Reference Example 1 of the present invention, and FIG. 2 is a line II of FIG. 3 is a diagram showing the impurity concentration distribution of the semiconductor region in FIG. 3, and FIG. 3 is a diagram showing an energy band structure along the line I-I in FIG.

In all the drawings of the reference example and the embodiment, those having the same function are designated by the same reference numeral, and the repeated description thereof will be omitted.

In FIG. 1, reference numeral 1 is a P ⁻ type semiconductor region (or well region) made of single crystal silicon. The semiconductor substrate 1 is
As indicated by reference numeral 1 in FIG. 2, for example, 1 × 10 ¹⁵ [atom
s / cm ³ ].

A field insulating film 2 is provided above the main surface of the semiconductor substrate 1 between the semiconductor element forming regions. A p-type channel stopper region 3 is provided on the main surface portion of the semiconductor substrate 1 below the field insulating film 2. The field insulating film 2 and the channel stopper region 3 are configured to electrically isolate the semiconductor elements.

Reference numeral 4 denotes an insulating film, which is the semiconductor substrate 1 in the semiconductor element formation region.
Is provided on the main surface of the. The insulating film 4 is mainly MI
It is designed to form the gate insulating film of SFET. In addition, the insulating film 4 constitutes an impurity introduction mask for constituting the semiconductor region.

Reference numeral 5 denotes a conductive layer, which is provided on a predetermined main surface portion of the insulating film 4. The conductive layer 5 mainly constitutes the gate electrode of the MISFET. The conductive layer 5 is formed by the first conductive layer forming step in the manufacturing process, and is formed of, for example, a polycrystalline silicon film. In addition, the conductive layer 5 is
In order to reduce the wiring resistance value, refractory metal film (Mo, Ti, T
a, W), silicide film (MoSi ₂ , TiSi ₂ , TaSi ₂ , WSi ₂ ),
It is composed of a superposed film in which a refractory metal film or a silicide film is provided on the polycrystalline silicon film. In addition, the conductive layer 5
Form an impurity introduction mask for forming a semiconductor region.

Reference numeral 6 denotes an n-type semiconductor region (LDD portion), which is the main surface portion of the semiconductor substrate 1 on both sides of the conductive layer 5, in other words, the main surface of the semiconductor substrate 1 between the source or drain region and the channel formation region. It is provided on the surface.

The semiconductor region 6 is configured to suppress the extension of the depletion region formed at the pn junction between the semiconductor substrate 1 and the drain region of the MISFET and reduce the electric field strength near the drain region. Further, the impurity concentration is lower than that of a substantial source region or drain region, diffusion of impurities toward the channel formation region side is suppressed, and a sufficient effective channel length can be secured.

The semiconductor region 6 is a portion deeper than the main surface of the semiconductor substrate 1,
For example, the maximum impurity concentration is at a depth of about 0.05 to 0.10 [μm], and the junction depth (xj) is about 0.25 to
It is configured to be about 0.30 [μm]. Then, the semiconductor region 6 is formed by, for example, using the conductive layer 5 as a mask for introducing impurities, introducing an impurity (for example, P) into the semiconductor substrate 1 by an ion implantation technique, and performing extension diffusion. As shown by reference numeral 6 in FIG. 2, the semiconductor region 6 is formed with an impurity concentration of, for example, about 1 × 10 ¹⁷ [atoms / cm ³ ].

Reference numeral 7 denotes a P-type semiconductor region, which is provided on the main surface portion (or upper portion) of the semiconductor region 6. This semiconductor region 7 is
The semiconductor region 6 is mainly formed in a portion deeper than the main surface of the semiconductor substrate 1. In other words, the semiconductor region 7 constitutes a potential barrier viewed from hot carriers (electrons) trapped in the interface formed between the semiconductor region 6 and an impurity introduction mask (sidewall) described later. Has become. Thereby, the current (electrons) between the source region and the drain region flowing in the semiconductor region 6 is configured not to pass near the interface.

As shown by reference numeral 7 in FIG. 2, the semiconductor region 7 is formed, for example, with an impurity (eg, B, BF) concentration of about 8 × 10 ¹⁶ [atoms / cm ³ ] higher than that of the semiconductor substrate 1. The junction depth is about 0.15 to 0.20 [μm].

Due to the provision of the semiconductor region 7, FIG.
As shown in the figure, the semiconductor region 6 is formed in a portion deeper than the main surface of the semiconductor substrate 1, and a current between the source region and the drain region (electron: e ₂ ) can be passed through this semiconductor region 6. Is configured. That is, it is possible to suppress the influence of the electric field effect due to hot carriers (electrons: e ₁ ) unnecessarily trapped at the interface.

Further, since the path through which the current flowing between the source region and the drain region is separated from the interface and the potential barrier is configured, the efficiency of injecting hot carriers into the interface can be reduced.

Note that FIG. 3 is a diagram showing an energy band in a voltage applied state, where Ev is a valence band, Ec is a conduction band, Ef is a Fermi level, and h is a hole.

An impurity introduction mask 8 is provided on the main surface of the insulating film 4 on both sides of the conductive layer 5. The impurity introduction mask 8 serves as a mask for forming a substantial source region or drain region.

The impurity introduction mask 8 is formed by, for example, subjecting a silicon oxide film formed by a CVD technique to an anisotropic etching technique. The impurity introduction mask 8 is configured to be self-aligned with the conductive layer 5.

Reference ^numeral 9 denotes an n ⁺ type semiconductor region, which is provided on the main surface portion of the semiconductor substrate 1 on both sides of the conductive layer 5 or the impurity introduction mask 8 so as to be electrically connected to the semiconductor region 6. The semiconductor region 9 constitutes a substantial source region or drain region.

In the semiconductor region 9, impurities (for example, As) are introduced into the main surface portion of the semiconductor substrate 1 by an ion implantation technique, stretched and diffused, and the impurity concentration is, for example, about 1 × 10 ²⁰ [atoms / cm ³ ]. And the junction depth is set to about 0.30 to 0.35 [μm].

The MISFET having the LDD structure is mainly composed of a semiconductor substrate 1, an insulating film 4, a conductive layer 5, a pair of semiconductor regions 6 and a pair of semiconductor regions 9. This LDD structure MISFET
The unnecessary hot carriers are trapped in the interface formed between the semiconductor region 6 and the impurity introduction mask 8.

An insulating film 10 is provided to cover a semiconductor element such as MISFET. The insulating film 10 is configured to electrically separate the conductive layers.

Reference numeral 11 is a connection hole, which is an insulating film above the predetermined semiconductor region 9.
It is provided by removing 4,10. The connection hole 11 is configured to electrically connect the conductive layers.

Reference numeral 12 denotes a conductive layer, which is provided so as to extend above the insulating film 10 so as to be electrically connected to a predetermined semiconductor region 9 through the connection hole 11.

Next, the manufacturing method of Reference Example I will be briefly described.

FIG. 4 and FIG. 5 are cross-sectional views of essential parts of a semiconductor integrated circuit device having an LDD-structured MISFET in each manufacturing step for explaining the manufacturing method of Reference Example I of the present invention.

First, the field insulating film 2 and the channel stopper region 3 are formed on the main surface portion and the main surface portion of the semiconductor substrate 1 which will be the semiconductor element formation region.

Then, over the main surface of the semiconductor substrate 1 which becomes the semiconductor element forming region, the insulating film 4 which becomes the gate insulating film and the conductive layer 5 which becomes the gate electrode are formed on the insulating film 4.

After that, the field insulating film 2, the insulating film 4, and the conductive layer 5 are used as a mask for introducing impurities, and the n-type semiconductor is self-aligned with the conductive layer 5 on the main surface portion of the semiconductor substrate 1 through the insulating film 4. Region 6 is formed. Then, as shown in FIG. 4, a p-type semiconductor region 7 is formed in a self-aligned manner on the main surface portion of the semiconductor region 6 in substantially the same manner as the semiconductor region 6.

After the step of forming the semiconductor regions 6 and 7 shown in FIG. 4, the impurity introduction masks 8 are formed on both sides of the conductive layer 5 in self-alignment with the conductive layer 5.

Then, as shown in FIG. 5, mainly using the impurity introducing mask 8, the n ⁺ type semiconductor region 9 is formed in self-alignment with the impurity introducing mask 8.

By forming the insulating film 10, the connection hole 11 and the conductive layer 12 after the step of forming the semiconductor region 9 shown in FIG.
The semiconductor integrated circuit device of Reference Example I is completed.

It should be noted that after this, a treatment step of a protective film or the like may be performed.

Further, the impurity introducing mask 8 may be removed in a predetermined process of the manufacturing process and may be omitted when the semiconductor integrated circuit device is completed.

As described above, according to this reference example I, the M of the LDD structure is
In the ISFET, by providing the semiconductor region 7 on the main surface portion of the semiconductor region (LDD portion) 6, a current between the source region and the drain region flows in a deep portion of the semiconductor region 6, so that undesired trapping of hot carriers occurs. The influence of the electric field effect can be suppressed.

Further, since the path through which the current flows between the source region and the drain region and the interface in which hot carriers are trapped are separated and a potential barrier can be formed, the efficiency of injecting hot carriers into the interface can be reduced. You can

These can suppress a decrease in mutual conductance, and thus can suppress deterioration in electrical characteristics.

Example I This example I is the MISFE of the LDD structure described in the above reference example I.
An example of suppressing the loss of mutual conductance at T will be described.

FIG. 6 is a cross-sectional view of essential parts of a semiconductor integrated circuit device having a LDD-produced MISFET manufactured by the method of the present Example I.

In FIG. 6, 6A is an n-type semiconductor region, which has substantially the same function as the semiconductor region 6 of Reference Example I. The semiconductor region 6A is configured to surround the semiconductor region 7 and reaches the channel formation region.

That is, the semiconductor region 6A is configured to remove the barrier formed between the semiconductor region 6A and the channel forming region and suppress the loss of the current between the source region and the drain region.

As described above, according to the present Example I, it is possible to obtain substantially the same effects as those of the Reference Example I.

Further, since the semiconductor region 6A reaching the channel region is provided, there is no barrier between the semiconductor region 6A and the channel formation region, so that the loss of current between the source region and the drain region can be suppressed.

[Example II] In Example II, an example of suppressing the punch-through between the source region and the drain region in the MISFET having the LDD structure described in Reference Example I and Example I will be described.

FIG. 7 is a cross-sectional view of a main part of a semiconductor integrated circuit device having an LDD-structured MISFET manufactured by the method of this Example II, and FIG. 8 is an impurity in the semiconductor region taken along line II-II in FIG. FIG. 9 shows a concentration distribution, and FIG. 9 shows another reference example II of the present invention.
FIG. 3 is a cross-sectional view of essential parts of a semiconductor integrated circuit device having a MISFET having an LDD structure for explaining.

In FIG. 7, 13 is a p-type semiconductor region, which is provided on the main surface portion of the semiconductor substrate 1 below the semiconductor region 6A. The semiconductor region 13 is composed of the semiconductor region 9 and the semiconductor substrate 1.
It is configured to suppress the extension of the depletion region formed on the semiconductor substrate 1 side from the pn junction. That is, in the MISFET having the LDD structure, unnecessary coupling of the depletion region between the source region and the drain region is suppressed, and punch through is suppressed.

The semiconductor region 13 is constituted by an impurity concentration of, for example, about 2 × 10 ¹⁶ [atoms / cm ³ ] as indicated by reference numeral 13 in FIG.

The semiconductor region 13 may be connected to the semiconductor region 7 as shown in FIG.

As described above, according to Example II, the reference example
It is possible to obtain substantially the same effects as those of I and Example I.

Further, in the LDD structure MISFET, since the semiconductor region 13 is provided, unnecessary coupling of the depletion region between the semiconductor regions 9 used as the source region or the drain region can be suppressed, and punch through can be suppressed.

[Effects] As described above, according to the novel technique disclosed in the present application, the effects described below can be obtained.

(1) In the LDD structure MISFET, the LD is formed on the main surface of the LDD part.
By providing a semiconductor region having a conductivity type opposite to that of the D portion and having an impurity concentration higher than that of the semiconductor substrate, a current between the source region and the drain region flows in a deep portion of the LDD portion, so that undesired trapped hot carriers The influence of the electric field effect can be suppressed.

(2) Because of the above (1), the path through which the current flows between the source region and the drain region and the interface where hot carriers are trapped are separated from each other, and a potential barrier can be formed, so that hot carriers are injected into the interface. Efficiency can be reduced.

(3) According to (1) above, since the LDD portion reaches the channel region, there is no barrier between the LDD portion and the channel formation region, so that the loss of current between the source region and the drain region is suppressed. can do.

(4) Since the reduction of the mutual conductance can be suppressed by the above (1) to (3), it is possible to suppress the deterioration of the electrical characteristics of the semiconductor integrated circuit device including the MISFET manufactured by LDD.

As described above, the invention made by the present inventor was specifically described based on the above-mentioned embodiment, but the present invention is not limited to the above-mentioned embodiment, and within the scope of the spirit thereof, Of course, it can be variously modified.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a main part of a semiconductor integrated circuit device having an LDD-structured MISFET for explaining Reference Example I of the present invention, and FIG. 2 is an impurity of a semiconductor region taken along the line II of FIG. FIG. 3 is a diagram showing a concentration distribution, FIG. 3 is a diagram showing an energy band structure on line II shown in FIG. 1, and FIGS. 4 and 5 are for explaining a manufacturing method of Reference Example I of the present invention. 6 is a cross-sectional view of a main part of a semiconductor integrated circuit device having a MISFET having an LDD structure in each manufacturing step of FIG. 6 and FIG. 6 shows an LD manufactured by the method of Example I of the present invention.
FIG. 7 is a sectional view of a main part of a semiconductor integrated circuit device having a D structure MISFET, and FIG. 7 shows an LD manufactured by the method of Example II of the present invention.
FIG. 8 is a cross-sectional view of a main part of a semiconductor integrated circuit device having a D structure MISFET, FIG. 8 is a diagram showing an impurity concentration distribution of a semiconductor region along line II-II in FIG. 7, and FIG. 9 is a reference example of the present invention. FIG. 3 is a cross-sectional view of a main part of a semiconductor integrated circuit device having an LDD-structured MISFET for explaining II. In the figure, 1 ... Semiconductor substrate, 2 ... Field insulating film, 3 ... Channel stopper region, 4, 10 ... Insulating film, 5, 12 ... Conductive layer, 6,
6A, 7, 9, 13 ... Semiconductor region, 8 ... Mask for introducing impurities, 11
... It is a connection hole.

Claims (1)

[Claims] 1. A first forming a source region and a drain region
A second semiconductor region having the same conductivity type as that of the first semiconductor region and having an impurity concentration lower than that of the first semiconductor region is provided in the main surface portion of the semiconductor substrate between the semiconductor region and the channel formation region. A method of manufacturing a semiconductor integrated circuit device having a MISFET, comprising the following steps (a) to (c). (A) After forming a conductive layer to be a gate electrode on the main surface of the first conductivity type semiconductor substrate through an insulating film to be a gate insulating film, the main surface portion of the semiconductor substrate is provided with respect to the conductive layer. Forming a second semiconductor region of the second conductivity type in a self-aligned manner by: (b) an impurity concentration higher than that of the semiconductor substrate at one end of the main surface portion of the second semiconductor region of the second conductivity type Forming a third semiconductor region of the first conductivity type that does not extend to the channel formation region side from one end of the second semiconductor region in a self-aligned manner with the conductive layer, (c) of the conductive layer Impurity introduction masks on both sides,
After being formed in self-alignment with the conductive layer, a first semiconductor region having the same conductivity type as the second semiconductor region and a higher impurity concentration than the second semiconductor region is formed on the main surface portion of the semiconductor substrate. A step of forming the impurity introduction mask in a self-aligned manner.