JP3031282B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device that controls a relatively high voltage and a large current.

[0002]

2. Description of the Related Art A power device such as a power MOSFET or an IGBT which controls a high voltage and a large current has a breakdown voltage between a drain and a source when the transistor is off of two.
0 to 1500 V is required. As shown in FIG. 6, this type of power device includes an electric field relaxation region 602 mainly formed on a semiconductor substrate 601 by epitaxial growth or the like.
Is a drain potential, and a diffusion layer having a conductivity type opposite to that of a semiconductor substrate called a base region (or body region) 603 formed above the electric field relaxation region is a source potential.
The aforementioned voltage of 20 to 1500 V is applied to the junction between the electric field relaxation region 602 and the base region 603, and a necessary drain-source breakdown voltage is obtained mainly by extending the depletion layer 604 in the electric field relaxation region. In this type of power device, the outermost periphery (scribe region) of the chip has the same potential as the drain electrode, and when a high voltage is applied between the drain and the source, the electric field concentrates on the outermost edge of the diffusion layer in the base region 603. And the breakdown between the drain and source occurs at a voltage significantly lower than the PN junction of the cell transistor region other than the outermost periphery (indicated by an arrow). In order to avoid such electric field concentration at the outermost edge of the diffusion layer in the base region, as shown in FIG. 7, a connection is made with the outermost periphery of the diffusion layer in the base region 703 to form a junction deeper than the diffusion layer in the base region. , That is, a diffusion layer of a well region 714 having an edge having a curvature larger than that of the outermost edge of the diffusion layer of the base region at the outermost periphery of the chip.

However, in a power device requiring a drain-source breakdown voltage of 100 V or more, the breakdown at the edge of the diffusion layer in the well region is significantly lower than the PN junction in the cell transistor region other than the outermost periphery. . Conventionally, Japanese Patent Laid-Open No. 6-45612
As shown in FIG. 12, in order to alleviate the electric field concentration at the corner portion of the edge of the diffusion layer in the well region and to approach the flat breakdown voltage of the PN junction, a field limited ring (also called a guard ring, A method of forming a diffusion layer called FLR) is well known. As shown in FIG. 8, two FLRs 815 provided outside the well region 814 facilitate the extension of the depletion layer from the edge of the diffusion layer of the well region 814 toward the chip outer periphery. For devices that require a source-to-source breakdown voltage, formation of the FLR has significantly improved the drain-source breakdown voltage. For example, when a power MOSFET having a drain-source withstand voltage of 350 V when the FLR is not formed and the cell transistor has the same structure as the FLR is formed,
There is an example in which the withstand voltage between the drain and the source is improved to 660 V. Other than the FLR, there is a field plate or the like that produces the same effect.

[0004]

However, in order to make the withstand voltage between the drain and source of the cell transistor near the outer periphery of the chip close to the withstand voltage of the PN junction of the cell transistor region other than the outermost periphery by using the FLR, it is necessary to use the cell transistor. A large area is required for forming the FLR on the chip outer peripheral portion outside the region. In a conventional power MOSFET having a drain-source withstand voltage of 600 V class, an FLR region width of about 120 μm is required to maintain a drain-source withstand voltage equal to that of the transistor region other than the outer peripheral portion. region of FLR when the power MOSFET chip requires about 1.44 mm ² things area corresponding to 16% of the chip total area 9.0 mm ^2. For this reason, there has been a problem that the area of the chip other than the cell transistor region functioning as a transistor increases. Further, the field plate and the like also have a problem that the area other than the cell region increases.

SUMMARY OF THE INVENTION It is an object of the present invention to reduce the deterioration of the withstand voltage between the drain and the source in the outer peripheral portion of the chip in the high voltage semiconductor chip in which the drain and the source are provided on the back surface and the front surface of the substrate, respectively, without increasing the chip area. In other words, the purpose is to increase the cell transistor region formed in the same chip area, or to reduce the area of a chip having the same performance.

[0006]

The present invention will be described with reference to FIGS. 5A and 5B schematically showing the present invention.

FIG. 5A shows that when a high voltage is applied between the drain and the source, the base region 50 is formed around the periphery of the chip.
The curvature of the PN junction is high at the edge portion 3 (marked by X), indicating that the electric field is concentrated. Note that a hatched portion 504 indicates a depletion layer mainly extending to the electric field relaxation region 502 side.

FIG. 5B shows an outer peripheral groove formed by removing an edge portion of the base region 503 at an electric field concentration portion (shown by a circle) in FIG. This indicates that the side surface 505 is protected by the outer peripheral insulator 506. In other words, by providing a groove surrounding the cell transistor region near the outside of the cell transistor region located on the outer peripheral portion of the chip, the PN junction surface of the transistor region on the outer peripheral portion is also cut at a flat surface, and there is no portion having a curvature.

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a sectional view of an outer peripheral portion of a semiconductor chip according to the present invention formed on a semiconductor substrate 101. FIG.
The configuration of the semiconductor chip shown in FIG. 1 includes a back surface (lower surface) of a semiconductor substrate 101 having one conductivity type, for example, an N-type conductivity type.
An electric field relaxation region 102 having an N-type conductivity is formed on the upper portion of the substrate.
A base region 103 having a P-type conductivity type opposite to the conductivity type of the electric field relaxation region is formed at the upper part of FIG. An N conductivity type source region 105 is formed in the base region 103, and a groove 106 that penetrates the source region 105 and the base region 103 from the surface of the base region 103 in the direction of the substrate 101 and reaches the electric field relaxation region 102. Is formed,
The inside of the groove 106 is the gate electrode 107 of the MOS transistor.
The gate electrode 107 and the silicon surface in the trench are insulated by an insulator 108 such as silicon oxide. Source region 10 on the surface of base region 103
5 is connected to a source electrode 109 made of metal or the like, and the source electrode 109 has the same potential as the base region 103. The source electrode 109 and the gate electrode 107 are insulated from each other by an interlayer insulating film 110. MO having gate, source and drain electrodes with the above configuration
An S transistor is formed. Here, the electric field relaxation region 102
The PN junction between the substrate region 103 and the base region 103 is a flat surface, and this flat surface is exposed at the outermost periphery to the side surface of the outer peripheral groove 113 formed so as to surround the cell transistor region. The side surface is covered with an insulator 104.

When a voltage is applied between the drain electrode (substrate 101) and the source electrode 109 of the MOS transistor shown in FIG. 1 and the potential difference between the gate electrode 107 and the source electrode 109 exceeds the threshold voltage of the MOS transistor. , This MOS transistor is turned on, and
When a voltage is applied between the drain and source electrodes, the MOS transistor is off if both the gate and source electrodes have the same potential. The voltage applied between the drain and source electrodes is applied to the electric field relaxation region 102 and the base region 10.
3 by a PN junction. That is, the depletion layer expands mainly from the PN junction in the direction of the electric field relaxation region 102, and shares the voltage depending on the depleted distance. Conventionally, this type of transistor requires a large area for forming an FLR around the chip in order to prevent breakdown due to electric field concentration at the edge of the diffusion layer in the base region in the periphery of the chip. Since there is no edge of the diffusion layer on the outer periphery of the chip that causes concentration, the point of causing electric field concentration is the groove 106 where the gate electrode 107 is formed in FIG.
, The electric field relaxation region 102 and the base region 1
The PN junction between the cells 03 has a drain-source breakdown voltage of each cell transistor region without forming an FLR or the like.
The withstand voltage between the drain and the source of the MOS transistor on the outer periphery of the chip is improved.

FIGS. 2A to 2F show an example of an actual manufacturing process of an N-channel enhancement type power MOSFET chip which has a configuration according to FIG. 1 and requires a drain-source breakdown voltage of 200 V. .

The resistivity of adding arsenic as an impurity is 0.0
20 μm of an N-type epitaxial layer having a resistivity of 5.6 Ωcm on an N-type substrate 201 of 01 to 0.006 Ωcm.
Grow to a thickness of The N-type epitaxial layer becomes the electric field relaxation region 202. (FIG. 2 (A)) Next, a thermal oxide film of 600 A (0.06 μm) is formed on the surface of the electric field relaxation region 202 by wet oxidation at 900 ° C., and boron is supplied with an energy of 70 keV and a dose of 2.0 E.
By performing ion implantation at 13 and performing a heat treatment at 1140 ° C., a diffusion layer of the base region 203 is formed at a junction depth of 2.0 μm above the electric field relaxation region. Next, BF2 is selectively applied with energy of 50 ke by photolithography technology.
V, ion implantation at a dose of 8.0E14, 1000 ° C.
Is performed, a diffusion layer of the back gate contact region 212 is formed in the base region 203 with a junction depth of 1.5 to 1.9 μm. Furthermore, arsenic is selectively irradiated with an energy of 70 ke by photolithography technology.
V, ion implantation at a dose of 1.0E16, 1000 ° C.
Is performed, a diffusion layer of the source electrode 205 is formed in the base region 203 with a junction depth of 0.3 to 0.4 μm. (FIG. 2B) Next, the source region 20 is formed by photolithography.
5. A groove 206 penetrating through the base region 203 and reaching the electric field relaxation region 202 is formed with a depth of 2.2 μm and a width of 1.0 μm. Next, 500 A by wet oxidation at 900 ° C.
(0.05 μm) thermal oxide film 208 is formed.
The 0A thermal oxide film 208 becomes a gate insulating film of the MOS transistor. (FIG. 2C) Next, polycrystalline silicon is grown to a thickness of 12000 A (1.2 μm) by CVD (Chemical Vapor Deposition), and phosphorus is diffused into the polycrystalline silicon in a phosphorus atmosphere at 920 ° C. Form polycrystalline silicon. Next RI
By performing anisotropic etching using E (Reactive Ion Etching), N-type polycrystalline silicon is left only in the groove where the above-described thermal oxide film 208 is formed, and N-type polycrystalline silicon on the surface of the semiconductor substrate is left. The silicon is removed. The N-type polycrystalline silicon remaining in the trench becomes the gate electrode 107 of the MOS transistor. (FIG. 2 (D)) Next, silicon oxide was deposited by CVD to a thickness of 8000 A (0.
After growth to 8 μm), the polycrystalline silicon oxide on the outer peripheral portion of the chip which is to be a scribe region of the power MOSFET is selectively removed by anisotropic etching using RIE by photolithography, and then the silicon oxide is used as a mask. HBr with high selectivity between silicon oxide and silicon
Silicon is anisotropically etched by RIE using a gas such as O ₂ + SF ₆ or HBrO ₂ + NF ₃ to form an outer peripheral groove 213 having a depth of 20 μm that penetrates the electric field relaxation region and reaches the substrate. (FIG. 2 (E)) Next, PSG is deposited by CVD to a thickness of 6000 A (0.6 μA).
m) and selectively removed by anisotropic etching using RIE by photolithography to expose the surfaces of the back gate contact region 212 and the source region 205 of the semiconductor substrate. The remaining PSG film becomes an interlayer insulating film 210 between the gate electrode 207 and the source electrode,
Also, it becomes an insulator inside the outer peripheral groove 213. Next, aluminum 109 serving as a source electrode is sputtered to a thickness of 5.0 μm,
It is selectively removed by anisotropic etching using RIE by a photolithography technique to separate the gate electrode and the source electrode, to expose the PSG of the chip outer peripheral groove 213 to be a scribe area, and to make each chip on the wafer a scribe area. It is completed if it separates with. Here, in the chip shown in FIG. 2F, the PN junction surface between the base region 203 and the electric field relaxation region 202 at the outermost periphery is exposed to the side surface of the outer peripheral groove 213 while being flat, and the PSG as the outer peripheral insulator 204 is provided. Is in contact with (FIG. 2 (F)) When a voltage is applied between the drain and the source in a transistor-off state in which the gate and the source are short-circuited, the base region 20
3 and a voltage is applied to the PN junction between the electric field relaxation region 202 and
A depletion layer mainly extends to the electric field relaxation region 202 and shares a voltage. Since the power MOSFET chip of this example does not have the edge of the diffusion layer in the base region in the outer periphery of the chip as in the power MOSFET according to the prior art, and no electric field concentration occurs in the outer periphery of the base region, the breakdown voltage is set to the gate of each cell transistor. It is determined by the tip of the electrode groove 206.

Next, a second embodiment of the present invention will be described.
This will be described in detail with reference to the drawings.

The semiconductor chip shown in FIG. 3 is provided with a drain electrode on the back surface of a semiconductor substrate 301 having one conductivity type, for example, N-type conductivity, and an electric field relaxation region 302 having N-type conductivity above the substrate. A base region 303 having a P-type conductivity type opposite to the conductivity type of the electric field relaxation region is formed above the electric field relaxation region 302. Base area 3
Numeral 03 is separated for each cell transistor, an N-conductivity type source region 305 is formed in each base region 303, and an insulating film 308 is formed on the surface of the base region 303 and the source region 305. . A gate electrode 307 of the MOS transistor is formed on the surface of the semiconductor substrate via the insulating film 308. The source region 305 is connected to a source electrode 309 made of metal or the like, and the source electrode 309 has the same potential as the base region 303. The source electrode 309 and the gate electrode 307 are insulated from each other by the interlayer insulating film 310. With the above configuration, a MOS transistor having the gate, source, and drain electrodes is configured. Here, the surface of the PN junction between the electric field relaxation region 302 and the base region 303 is located at the outermost periphery of the chip.
It is exposed on the side surface of an outer peripheral groove 313 formed so as to surround the cell transistor region.
Covered with.

When a voltage is applied between the drain electrode (substrate 301) and the source electrode 309 of the MOS transistor shown in FIG. 3, if the potential difference between the gate electrode 307 and the source electrode 309 exceeds the threshold voltage of the cell transistor, ,
This MOS transistor is turned on, and when a voltage is applied between the drain and source electrodes, the MOS transistor is turned off if the gate and source electrodes have the same potential. The voltage applied between the drain and source electrodes is equal to the P
Paused by N-junction. That is, the depletion layer expands mainly from the PN junction in the direction of the electric field relaxation region, and the voltage is shared by the depleted distance. In FIG. 3, since there is no edge of the diffusion layer that causes electric field concentration, electric field concentration does not occur in the outer peripheral portion of the chip, and the point of electric field concentration is caused by the diffusion layer in the base region separated from each other in the cell transistor region. The edge, and the PN junction between the electric field relaxation region and the base region at the outermost periphery of the chip becomes the drain-source breakdown voltage of each cell transistor region without forming FLR or the like.
The withstand voltage between the drain and the source of the MOS transistor is improved.

FIGS. 4A to 4F show an example of an actual manufacturing process of an N-channel enhancement type power MOSFET chip having the configuration according to FIG. 3 and requiring a drain-source breakdown voltage of 200 V. .

The resistivity of arsenic added as an impurity of 0.0
20 μm of an N-type epitaxial layer having a resistivity of 5.6 Ωcm on an N-type substrate 401 of 01 to 0.006 Ωcm.
Grow to a thickness of The N-type epitaxial layer becomes the electric field relaxation region 402. (FIG. 4A) Next, a thermal oxide film of 500 A is formed on the surface of the electric field relaxation region 402 by wet oxidation at 900 ° C. This 500 A thermal oxide film becomes the gate insulating film 408 of the MOS transistor. Next, polycrystalline silicon is deposited to a thickness of 4000 by CVD.
A is grown, and phosphorus is diffused into the polycrystalline silicon in a phosphorus atmosphere at 920 ° C. to form N-type polycrystalline silicon. Next, by performing anisotropic etching using RIE, a gate electrode 407 of a MOS transistor made of N-type polycrystalline silicon is formed on the gate insulating film 408. (FIG. 4B) Next, a 200 A thermal oxide film is formed on the surface of the electric field relaxation region 402 and the side and upper surfaces of the polycrystalline silicon gate electrode 407 by wet oxidation at 900 ° C. Boron is ion-implanted into the gate self-alignment at an energy of 70 keV and a dose of 2.0E13, and is heat-treated at 1140 ° C. to form a diffusion layer of the base region 403 at a junction depth of 2.0 μm above the electric field relaxation region. . Next, BF2 is selectively applied with energy of 50 k by photolithography technology.
eV, ion implantation at a dose of 8.0E14, 1000
By performing a heat treatment at a temperature of ℃, a diffusion layer of the back gate contact region 412 is formed in the base region 403 with a junction depth of 1.5 to 1.9 μm. Further, arsenic is selectively applied with an energy of 50 ke by photolithography technology.
V, ion implantation at a dose of 1.0E16, 1000 ° C.
Is performed, a diffusion layer of the source electrode 405 is formed in the base region 403 with a junction depth of 0.3 to 0.4 μm. (FIG. 4C) Next, silicon oxide is grown to a thickness of 8000 A by CVD, and the power MOSF is grown by photolithography technology.
The silicon oxide on the outer peripheral portion of the chip, which becomes the ET scribing region, is selectively removed by anisotropic etching using RIE. Next, using silicon oxide as a mask, silicon is anisotropically etched by RIE using a gas having a high selectivity with respect to silicon oxide to form a groove 413 having a depth of 20 μm penetrating the electric field relaxation region and reaching the substrate. (FIG. 4 (D) Next, PSG is grown to a thickness of 6000 A by CVD.
It is selectively removed by anisotropic etching using RIE by a photolithography technique to expose the back gate contact region and the source region of the semiconductor substrate and the surface of the N-type polycrystalline silicon in the trench. The remaining PSG film becomes an interlayer insulating film 410 between the gate electrode 407 and the source electrode 409. (FIG. 4E) Next, aluminum serving as the source electrode 409 is sputtered to a thickness of 5.0 μm, and is selectively removed by anisotropic etching using RIE by a photolithography technique. 409, and exposing the PSG on the outer peripheral portion of the chip which is to be a scribe area, to separate each chip on the wafer in the scribe area. (FIG. 4 (F))

[0019]

By providing a groove surrounding the cell transistor region and removing the edge of the diffusion layer in the outer peripheral portion of the chip by the groove, the portion having the curvature of the PN junction surface in the cell transistor region located at the outermost peripheral portion of the chip is provided. Has the effect of avoiding the concentration of an electric field and improving the withstand voltage between the drain and source in the outer peripheral portion to a value that is not different from the withstand voltage between the drain and source in the cell transistor region other than the outer peripheral portion.

This eliminates the need for the outer peripheral structure such as the FLR on the outer periphery, which is conventionally required to prevent the deterioration of the drain-source breakdown voltage, and reduces the area of the chip peripheral structure while maintaining the same drain-source breakdown voltage as in the past. It can be made smaller, and therefore, the chip size can be reduced to produce transistors of the same performance. For example, in the case of a power MOSFET that requires a drain-source withstand voltage of 600 V, in the prior art, the outer periphery FLR of the transistor region, the structure of the field plate, and the like are two in order to maintain the same drain-source breakdown voltage as the transistor region other than the outer periphery.
For a chip having a side of 3.0 mm, about 3.2% corresponding to 36% of a total chip area of 9.0 mm ² is required.
Although an area of as much as 4 mm ² is required in areas other than the transistor region, the effect of the present invention eliminates the necessity of a structure such as the FLR and the field plate on the outer periphery.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a first embodiment of a semiconductor device of the present invention.

FIG. 2 is a sectional view showing an example of a manufacturing process of the power MOSFET chip according to the embodiment of FIG. 1;

FIG. 3 is a sectional view showing a second embodiment of the semiconductor device of the present invention.

FIG. 4 is a sectional view showing a manufacturing step of the power MOSFET chip according to the embodiment of FIG. 2;

FIG. 5 is an explanatory sectional view schematically showing the present invention.

FIG. 6 is a cross-sectional view showing a breakdown point of a conventional power MOSFET chip.

FIG. 7 is a cross-sectional view showing an outer peripheral structure of a conventional power MOSFET chip in which a well is formed.

FIG. 8 is a cross-sectional view showing an outer peripheral structure of a conventional power MOSFET chip on which an FLR is formed.

[Explanation of symbols]

 101, 201 semiconductor substrate 102, 202 electric field relaxation region 103, 203 base region 104, 204 outer peripheral insulator 105, 205 source region 106, 206 groove 107, 207 gate electrode 108, 208 gate insulating film 109, 209 source electrode 110, 210 Interlayer insulating film 113, 213 Outer groove 212 Back gate contact region 301, 401 Semiconductor substrate 302, 402 Electric field relaxation region 303, 403 Base region 304, 404 Outer insulator 305, 405 Source region 307, 407 Gate electrode 308, 408 Gate insulation Film 309, 409 Source electrode 310, 410 Interlayer insulating film 313, 413 Outer peripheral groove 412 Back gate contact region 502 Electric field relaxation region 503 Base region 504 Depletion layer 505 Side surface of outer peripheral groove 506 Outer insulator 601, 701, 801 Semiconductor substrate 602, 702, 802 Electric field relaxation region 603, 703, 803 Base region 604, 704, 804 Depletion layer 714, 814 Well region 815 FLR

Claims (3)

(57) [Claims] 1. A semiconductor device in which a plurality of transistors each having a drain electrode on a back surface and a source electrode on a surface are formed, the semiconductor device having an outer peripheral groove surrounding an outer periphery of a transistor region of the device.
The PN junction surface forming the base region and the electric field relaxation region
A semiconductor device characterized by being cut by the outer peripheral groove at a portion having a planar shape parallel to a substrate of the device. 2. The semiconductor device according to claim 1, wherein the outer peripheral groove is formed by etching, and a side surface of the outer peripheral groove is covered with an insulator. 3. The semiconductor device according to claim 1, wherein the outer peripheral groove penetrates the base region and the electric field relaxation region, and reaches the substrate serving as a drain region.