JPS63122174A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To relax an electric field spreading in the transverse direction between a source and a drain, to suppress the occurrence of an avalanche breakdown and a hot carrier, and to realize a hig-withstand-voltage and a high-speed operation by a method wherein a region coming into contact with a gate insulating film, out of a depleted region in a source-drain region, is covered with a gate electrode. CONSTITUTION:An n-type low-concentration source-drain region 3 is formed by introducing an n-type impurity into a p-type Si substrate 8 and by self-aligning with a first gate electrode 1 by making use of the first gate electrode 1 and an insulating film 5 as a mask. Then, an electric-conductive film composed of polycrystalline silicon, a silicide or the like, doped with an electric-conductive impurity of high concentration is deposited on the whole surface. After that, said electric-conductive film is etched anisotropically so that a second gate electrode 6 remains only at the side wall of the first gate electrode 1. Then, after the insulating film has been deposited again on the whole surface, an etching process is executed so that an insulating film 7 can be formed at the side wall so as to cover the second gate electrode 6. Tie film overlaps with the low-concentration source-drain region 3 by means of the second gate electrode 6. The overlapping amount can be controlled by the deposited film thickness for the second gate electrode 6 and by the overetching amount of said electric-conductive film.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having a MOS transistor, and more particularly to a semiconductor device suitable for relaxing an electric field between a source and a drain.

[Conventional technology]

LDD (Lightly Doped Drain) is a high-voltage transistor structure proposed as a basic device for VLSH.
)) There is a structure. (Literature on LDD structure: IE Transactions on Electron Devices is E.D.-27, pp. 1359-1367 (I.E.E.
E Trans, E 1ectronDevic
es, ED-27pp1359-1367))LDD
In this structure, impurities are introduced into the surface region of the semiconductor substrate using the gate electrode as a mask, and low concentration source/drain regions are formed in self-alignment with the gate electrode. The low-concentration drain region alleviates the lateral spreading electric field between the source and drain when voltage is applied, suppressing avalanche breakdown and the generation of hot carriers (carriers that obtain energy from the electric field and enter a high-energy state). do the work.

Therefore, conventionally, in order to enhance the electric field relaxation effect of the LDD structure, the lightly doped drain region has been formed long or the impurity concentration of the lightly doped drain region has been lowered.

[Problem that the invention seeks to solve]

However, as the impurity concentration in the lightly doped drain region is lowered, characteristic deterioration such as a decrease in drain breakdown voltage due to avalanche breakdown, a decrease in transfer conductance due to the generation of hot carriers, and fluctuations in threshold voltage becomes noticeable. , the reliability of the device decreases. In particular, significant deterioration appears at the beginning of the stress period (early stage of high voltage application). This is said to be caused by hot carriers injected into the sidewall spacer (insulator 11 formed on the sidewall of the gate electrode) of the LDD type MOS transistor. That is, hot carriers injected into and captured by the sidewall spacer pinch off the low concentration drain region.

Causes a decrease in transfer conductance.

In this way, in the conventional LDD type MOS transistor,
If the impurity concentration in the lightly doped drain region is not strictly controlled, a drop in drain breakdown voltage due to avalanche breakdown, a drop in transfer conductance due to hot carriers, and fluctuations in threshold voltage will become noticeable, resulting in a problem of lower device reliability. there were.

Furthermore, in the conventional LDD structure, no consideration was given to the amount by which the gate electrode overlaps the lightly doped source/drain region (hereinafter referred to as the amount of overlap).

In other words, since the lightly doped source/drain regions were formed in self-alignment with the gate electrode by impurity doping using the gate electrode as a mask, the dose of impurities for forming the lightly doped source/drain regions was reduced. If the depth of the diffusion layer is small, the extension of the lateral diffusion layer in the direction toward the channel is also short, and the amount of overlap between the lightly doped source/drain region and the gate electrode is reduced.

By the way, as a result of simulations conducted by the present inventors, it has been found that the strength of the lateral floor electric field between the source and drain and the position of the maximum point of the electric field are sensitively affected by the amount of overlap. First, FIG. 2 shows the results regarding the electric field strength.

The length of the lightly doped drain region is 0.44. The n-dose amount in the drain region is 5×10”/e♂ and 1×10
”/c■3 case is shown.

When the n-dose amount is as high as 5 x 10"/cm", the width of the depletion layer in the lightly doped drain region becomes small, the depletion layer does not spread over the entire region, and the depletion layer in the drain region becomes small. Among the regions, the region in contact with the gate insulating film is
Habo 0.2. becomes the length of therefore.

When the amount of overlap is 0.2- or more and the above region is completely overlapped, the maximum value of the lateral electric field strength becomes small as shown in FIG.

On the other hand, when the n-dose amount is as low as I When the amount of overlap is smaller than 0.4t1m and the region in contact with the gate insulating film of the depletion region of the low concentration drain region does not completely overlap,
As shown in FIG. 2, the maximum value of the lateral electric field strength becomes large, and if the entire region is overlapped with the gate electrode, the lateral electric field strength becomes small.

Also, according to the simulations conducted by the present inventors.

If the entire region of the depletion region of the drain region in contact with the gate insulating film is overlapped with the gate electrode, the maximum point of electric field strength will be located deep in the substrate. Figure 3 shows
The amount of overlap between the gate electrode and drain region,
FIG. 3 is a diagram showing the relationship between the maximum point of the lateral electric field strength and the depth from the substrate surface.

For example, as shown in Figure 3, the n-dose amount is lXl0''
/c♂, if the above overlap amount is set to 0.1- or more, the maximum point of electric field strength will be approximately 0.05 from the substrate surface.
It is located at a depth of IIm (50 nm) and is no longer near the surface of the substrate.

On the other hand, when the amount of overlap is less than 0.1 tm, the maximum point of electric field strength is near the surface of the substrate. Note that even if the n-dose amount is IXIO"/(!l",
By overlapping the gate electrode all the way to the heavily doped drain region, the maximum point of electric field strength can be located inside the substrate.

As described above, the amount of overlap between the gate electrode and the drain region is one of the key factors for relaxing the lateral electric field. However, in the conventional technology, the amount of overlap between the lightly doped drain region and the gate electrode cannot be changed arbitrarily because a self-alignment process is used.Especially when the impurity concentration in the lightly doped drain region is low, Since the lateral diffusion width of impurities is small, the amount of overlap between the gate electrode and the drain region is small.

On the other hand, when the impurity concentration is low, the width of the depletion layer in the drain region becomes large. As a result, a problem arises in that the lateral electric field strength becomes rather large. Even if the diffusion layer (low-concentration drain region) is extended by heat treatment to increase the amount of overlap, the impurity concentration will become lower due to diffusion, so the depletion layer width will conversely increase, and the gate electrode will cause the low-concentration drain region to expand. The depletion layer region in contact with the gate insulating film cannot overlap.

As explained above, if the source/drain regions are formed only by a self-alignment process as in the prior art, it is not possible to optimize the amount of overlap with the gate electrode and relax the electric field.

The purpose of the present invention is to optimally control the amount of overlap between the gate electrode and the source/drain region, thereby alleviating the lateral spreading electric field between the source and drain, thereby suppressing avalanche breakdown and the generation of hot carriers. Therefore, it is an object of the present invention to provide a semiconductor device that can achieve high breakdown voltage and high speed, and a method for manufacturing the same.

Another object of the present invention is to provide a semiconductor device and a method for manufacturing the same, in which the amount of overlap can be arbitrarily controlled.

[Means for solving problems]

In order to achieve the above object, a semiconductor device of the present invention includes a gate electrode provided on a semiconductor substrate with a gate insulating film interposed therebetween, and source/drain regions provided in a surface region of the semiconductor substrate on both sides of the gate electrode. In the semiconductor device, at least a region of the depleted region of the source/drain region that is in contact with the gate insulating film is covered (overlapped) by the gate electrode.

In addition, 1 for manufacturing a semiconductor device with such a configuration.
A method for manufacturing a semiconductor device according to the present invention includes: forming a first gate electrode on a semiconductor substrate via an insulating film; forming a second gate electrode on a sidewall of the first gate electrode; The method is characterized by comprising a step of doping impurities into surface regions of the semiconductor substrate on both sides of the gate electrode to form source/drain regions.

One of the features of the present invention is that the first gate electrode.

The second gate electrode is electrically connected and has the same potential.

A second layer for effectively overlapping a region of the depletion region of the drain region that is in contact with the gate insulating film.
In one embodiment in which a gate electrode is formed on the side wall of the first gate electrode, an insulating film is formed on the side wall of the gate electrode by using the side wall stepped portion of the gate electrode in the manufacturing process of a conventional LDD type MOS transistor. (sidewall spacers) using a process similar to that used to form sidewall spacers.

That is, after depositing a conductive film on the entire surface of the first gate electrode to form the second gate electrode by CVD,
By performing anisotropic dry etching on the entire surface, the conductive film is left on the side wall of the first gate electrode having a one-step difference. Therefore, the second gate electrode is formed in self-alignment with the first gate electrode. Of course, the first gate electrode and the second gate electrode are also electrically connected and have the same potential.

After that, an insulating film for a spacer is formed on the sidewalls of the second gate electrode. The sidewall insulating film can be formed by a method similar to that used in conventional LDD structures, that is, by CVD and anisotropic etching, or by another embodiment of the present invention. Here, the second gate electrode is formed by thermally oxidizing the surface portion of the second gate electrode formed on the side wall of the first gate electrode.

[Effect]

The first gate electrode has the function of turning on and off the source/drain region (in the LDD structure, the low concentration source/drain region formed in self-alignment with the first gate electrode). do. That is, the first gate electrode functions as a gate electrode of a normal MOS transistor.

The second gate electrode, which is formed so as to overlap the region in contact with the gate insulating film of the depleted region of the source/drain region, serves to alleviate the lateral electric field applied to the depleted region of the drain region.

The second gate electrode also serves to increase the transfer conductance in the depletion region. Furthermore, conventional LD
This prevents hot carrier injection into the insulating film on the side walls of the gate electrode, which was a problem with the D structure.

In addition, since the potential near the substrate surface of the lightly doped drain region can be controlled by the second gate electrode, characteristic deterioration due to hot carriers that is inherent to LDDs, that is, the pinch-off phenomenon of the lightly doped source and drain due to captured hot carriers, is suppressed. can.

Now, if the depletion region in contact with the gate insulating film in the drain region is overlapped by the gate electrode in this way, the above effect can be obtained, but if this amount of overlap becomes large, conversely, the depletion region between the gate and the source/drain A problem arises in which parasitic capacitance increases. However, the present invention can also solve this problem. That is, in order to minimize the parasitic capacitance, the length of the second gate electrode, the amount of deposition of the conductive film for the second gate electrode, and the amount of overetching of the conductive film can be controlled independently. ).

Alternatively, by controlling the thickness of the spacer insulating film formed on the side walls of the second gate electrode, the amount of deposition of the insulating film, the amount of overetching of the insulating film, or the amount of oxidation of the second gate electrode, The amount of overlap and parasitic capacitance between the gate electrode and source/drain regions can be optimized.

Due to the above effects, high-voltage, high-reliability, and high-speed fine M
An OS transistor can be realized.

〔Example〕

Example 1 FIG. 1 is a cross-sectional view of a MOS transistor according to a first example of the present invention.

In the figure, 8 is a p-type Si substrate, 1 is a first gate electrode, 2 is a gate oxide film, 3 is an n-type low concentration source/drain region, 4 is an n-type high concentration source/drain region, 5 is the first
6 is a second gate electrode formed on the side wall of the first gate electrode 1; 7 is an insulating film formed on the top of the gate electrode 1;
is an insulating film (sidewall spacer) formed on the sidewall of the second gate electrode 2.

In this embodiment, the region in contact with the gate insulating film 2 of the depletion region generated when voltage is applied to the lightly doped drain region 3 is
They are formed so as to be overlapped by the second gate electrode 146. Therefore, as explained using FIG. 2, the lateral spreading electric field strength between the source and drain becomes small, and the electric field between the source and drain can be relaxed.

Avalanche breakdown can be suppressed, generation of hot carriers can be suppressed, and hot carriers can be prevented from being injected into areas other than the gate electrode. therefore.

It is possible to prevent characteristic deterioration such as a decrease in drain breakdown voltage and fluctuation in threshold voltage due to avalanche breakdown, and improve device reliability.

Further, as explained using FIG. 3, the maximum point of the lateral spread electric field strength is located inside the substrate. Therefore, hot carriers generated deep in the drain are
This makes it difficult for hot carriers to be injected into the gate oxide film 2, and even if hot carriers are injected into the gate oxide film 2 and captured, the capture location exists under the gate electrode.
It is possible to suppress the pinch-off phenomenon of the lightly doped drain region 3 due to trapped charges, and prevent a decrease in transfer conductance.

Furthermore, according to this embodiment, in the depleted region of the lightly doped drain region 3, charges are induced on the substrate surface due to the overlap of the region with the gate electrode, resulting in the effect that the transfer conductance increases. .

Next, a method for manufacturing the LDD type MOS transistor of this example will be explained.

First, a thin gate oxide film 2 is formed on a p-type Si substrate 8, and then a conductive first gate electrode 1 is formed on the gate oxide film 2 by a CVD method, and an S io film, a Si
, an insulating film 5 made of N4 film or the like is formed. This first gate electrode 1 is made of polycrystalline Si doped with conductive impurities.
Or ′ is silicide.

It may be a metal such as tungsten (W) or aluminum, or a composite film of these films.

Next, using the first gate electrode 1 and the insulating film 5 as masks, the p-type Si substrate 8 is doped with n-type impurities to form n-type low concentration source/drain regions in self-alignment with the first gate electrode 1. Next, a conductive film of polycrystalline Si, silicide, etc. doped with conductive impurities at a high concentration is deposited over the entire surface.

Thereafter, the conductive film is anisotropically etched to leave the second gate electrode 6 only on the sidewalls of the first gate electrode 1. Therefore, after depositing an insulating film such as SiO*Ill on the entire surface again, this layer is anisotropically etched to form a sidewall insulating film 7 covering the second gate electrode 6. In this state, the n-type impurity (that is, the impurity of the same conductivity type as the low concentration source/drain region 3) is doped again at a high concentration to form the n-type high concentration source/drain region in self-alignment with the insulating film 7. form 4.

In the example of this manufacturing method, impurities were doped into the conductive film for forming the second gate electrode 6 before anisotropic etching. After remaining, impurities may be doped.

In this embodiment, the second gate electrode d is used to overlap the lightly doped source/drain region 3. Also,
The amount of overlap can be controlled by the deposited film thickness for the second gate electrode 6 and the amount of overetching of the conductive film (ie, the length of the second gate electrode 6). Note that depending on the deposited film thickness of the insulating film 7 on the side wall of the second gate electrode 6 (that is, the formation position of the high concentration source/drain region 4), the low concentration source/drain region 4 can be formed independently of the amount of overlap.
The length of the drain region can be controlled.

As a result, while keeping the dynamic channel length between the lightly doped source and drain regions 3 constant, the amount of gate/drain overlap and the length of the lightly doped source and drain regions 3 can be changed independently. I can do it.

Therefore, the length of the lightly doped drain region 3 is optimized so that the depletion layer of the lightly doped drain region 3 extends sufficiently but does not reach the highly doped drain region 4 during operation with a normal power supply voltage of 5V. In this state, the depletion region in contact with the gate oxide film 2 of the low concentration drain region 3 can be completely overlapped with the second gate electrode 60. For example, if the n- dose is 5X10'''/C2 In this case, as shown in FIG. 2, the depletion layer width is approximately 0.2t1m.

The length of the low concentration drain region 3 is set to 0.27a* or more, and the overlap amount is set to 0.2. It can be done.

In this embodiment, since the drain lateral electric field can be relaxed while the effective channel length remains constant, the drain breakdown voltage can be improved. Furthermore, the amount of gate/drain overlap can be limited to the depleted region in contact with the gate insulating film of the lightly doped drain region 3, and can be prevented from reaching the highly doped drain region 4. Therefore, the problem of increased gate/drain parasitic capacitance due to unnecessary overlap can also be solved.

Although this embodiment has been described using an n-channel MOS transistor as an example, similar effects can be obtained in the case of a p-channel MOS transistor.

Example 2 FIGS. 4(a) to 4(c) show Mo of the second example of the present invention.
FIG. 3 is a cross-sectional view of the manufacturing process of the S transistor.

This embodiment differs from the first embodiment in the method of forming the insulating film formed on the sidewall of the second gate electrode.

In the first embodiment described above, the sidewall insulating film of the second gate electrode was deposited by the CVD method, but in this embodiment, the surface portion of the second gate electrode formed on the sidewall of the first gate electrode was deposited. Formed by oxidation. The steps will be explained below in order.

First, as shown in FIG. 4(a), a first gate electrode 1 and an insulating film 5 are deposited by CVD on a gate oxide film 2 formed on a Si-based Fi8.

Next, these films are dry-etched using a photoresist film as a mask to process them into the shape of the gate electrode.
Using first gate electrode 1 and insulating film 5 as masks, impurities are doped to form lightly doped source/drain regions 3 in self-alignment with gate oxide film 1 .

Subsequently, a polycrystalline S1 film is uniformly deposited over the entire surface of the wafer by low pressure CVD. After this, the polycrystalline S1 film is
), doped with conductive impurities such as arsenic (As). Thereafter, the polycrystalline Si film is etched by anisotropic etching, leaving the second gate electrode 6 only on the side walls of the first gate electrode 1, as shown in FIG. 4(b).

Next, selective oxidation was performed using the phenomenon that polycrystalline SL containing a high concentration of impurities has a high oxidation rate, as shown in Figure 4 (
As shown in c), an insulating film (oxide film) 7 is formed on the sidewalls of the second gate electrode 6. Next, highly doped source/drain regions 4 are formed in self-alignment with the insulating film 7.

According to this embodiment, the sidewall insulating film 7 of the second gate electrode 6
can be formed by an oxide film with uniform film quality, and the fourth
As shown in Figure (c), the effect of increasing the thickness of the gate oxide film 2 at the end of the second gate electrode 6 is produced. As described above, when the gate oxide film 2 becomes thicker at the end of the gate electrode, the fringe electric field between the second gate electrode 6 and the heavily doped source/drain region 4 is relaxed. For this reason.

The effect is that the electric field concentration at the gate end is relaxed, and the lateral electric field strength can be further relaxed.

Note that in the above manufacturing process, after the second gate electrode 6 is formed on the side wall of the first gate electrode 1, the electrode 6 may be doped with a high concentration of impurity.

At this time, the conductivity type of the impurity to be doped is
If the conductivity type is the same as that of the drain region 4, the highly doped source/drain regions 4 can be formed at the same time. The insulating film 7 will be formed after this. Now, also in this example,
The amount of overlap and the length of the lightly doped drain region 3 can be changed arbitrarily.

Embodiment 3 FIG. 5 is a cross-sectional view of a MOS transistor according to a third embodiment of the present invention. In this embodiment, an SD (single drain (S) i
This is an example in which a structure is adopted. In the following drawings, the same reference numerals as in FIG. 1 indicate the same parts as in FIG. 1.

Also in this example, the gate electrode (1 or 6) is
Since the depletion region of the high concentration source/drain region 4 is formed so as to overlap at least the region in contact with the gate oxide film 2, the lateral electric field between the source and drain can be relaxed, and the same effect as in the first embodiment can be obtained. can be played.

Embodiment 4 FIG. 6 is a cross-sectional view of a MOS transistor according to a fourth embodiment of the present invention. This embodiment uses an SD structure instead of the LDD structure of the embodiment shown in FIG. 4(c). This is an example of the case.

Embodiment 5 FIG. 7 is a cross-sectional view of a MOS transistor according to a fifth embodiment of the present invention. In this embodiment, a DDD (double diffused drain) structure is used instead of the LDD structure of the embodiment shown in FIG. (Double D 1ffused D
In this embodiment, which is an embodiment in which a rain)) structure is adopted, a gently sloped diffusion layer 71 is formed so as to surround the highly doped source/drain diffusion layer 4.

Embodiment 6 FIG. 8 is a cross-sectional view of a MOS transistor according to a sixth embodiment of the present invention. In this embodiment, a DDD'a structure is used instead of the LDD structure of the embodiment shown in FIG. This is an example of the case.

In the embodiments shown in FIGS. 6, 7, and 8, the spreading electric field between the source and drain is alleviated by overlapping the depletion region in contact with the gate oxide film in the source/drain region with the gate electrode. can.

Embodiment 7 FIG. 9 is a cross-sectional view of a MOS transistor according to a seventh embodiment of the present invention. In the DDD structure of the embodiment shown in FIGS. 7 and 8, the highly doped source/drain region 4 is doped with impurities using the first gate electrode 1 as a mask. However, in this example, the highly doped source/drain regions 4 are formed in self-alignment with the second gate electrode 6 by doping with impurities using the second gate electrode 6 as a mask. According to this embodiment, which is an embodiment in which the depletion layer is formed in a similar manner, the depletion layer that spreads in the region of the gently sloped diffusion layer 71 is completely overlapped by the gate electrode. , gently sloped diffusion layer 7
As the length of 1 becomes longer, the electric field relaxation in this region becomes even more significant.

Embodiment 8 FIG. 10 is a sectional view of a MOS transistor according to an eighth embodiment of the present invention. According to this embodiment, which is an embodiment in which the highly doped source/drain region 4 is formed in a self-aligned manner with the sidewall oxide film 7 of the second gate electrode 6 in the structure of the embodiment shown in FIG. , the gate electrode completely overlaps the gently sloped diffusion layer 7, and the gate electrode completely overlaps the gently sloped diffusion layer 7.
1 is longer than in Example 7, the spreading electric field between the source and drain can be relaxed.

Embodiment 9 FIG. 11 is a cross-sectional view of a MOS transistor according to a ninth embodiment of the present invention. In this embodiment, a heavily doped source/drain region 4 is formed on a Si substrate 8 on which a gate oxide film 2 is formed. In the case of an LDD structure formed deeper than the surface of
This is an example in which they overlap to the point where they are joined to the drain region 4.

According to this embodiment, since the second gate electrode 6 completely overlaps the depletion region in contact with the gate oxide film 2 of the low concentration source/drain region 3, the spreading electric field between the source and drain is relaxed. be done. Furthermore, in addition to this effect, since the highly doped source/drain regions 4 are located deep in the substrate, the current path during operation can be located deep in the substrate. Therefore, it becomes less susceptible to the influence of hot carriers captured in the gate oxide film 2 and the sidewall insulating film 7, and the highly doped source/drain regions 4 with high potential
is located deep in the substrate, the maximum point of the lateral electric field strength is also located deep in the substrate, and the relaxation of the electric field becomes more significant.

Embodiment 10 FIG. 12 is a cross-sectional view of a MOS transistor according to a tenth embodiment of the present invention. This embodiment differs from the embodiment of FIG. 11 in that the sidewall oxide film 7 of the second gate electrode 6 is This embodiment, which is an embodiment in which the second gate electrode 6 is formed by the method shown in the embodiment of FIG. is obtained.

Example 11 FIGS. 13(a) to 13(c) are process cross-sectional views showing a MOS transistor according to an eleventh example of the present invention.

A method of manufacturing the MOS transistor of this example will be explained.

First, as shown in FIG. 13(a), a gate oxide film 2 is formed on the surface of an n-type or Si substrate 8 doped with n-type impurities. On top of this, a polycrystalline 5i doped with conductive impurities at a high concentration is used to form a first gate electrode.
Depositing ljJ, a silicide film, a metal film such as W, or a composite film of these films.1 Next, an insulating film 5 is deposited on the conductive film, and then the conductive film and the insulating film are removed by photo-etching. The film 5 is patterned and the first
A gate electrode 11 is formed. However, at this time.

As shown in FIG. 13(a), the conductive film is left by the thickness indicated by a. 'Next, using the first gate electrode 11 and the insulating film 5 as masks, ions of impurities of a conductivity type different from that of the substrate 8, that is, n-type, are implanted into the surface region of the Si substrate 8 to form the low concentration source/drain regions 3. form. Here, the energy for ion implantation is optimized to a value that allows the ions to be implanted into the Si substrate 8 through a film having a thickness a. Note that by leaving the film thickness a, it is possible to prevent damage to the gate oxide film 2 and the substrate 8 during the etching process for patterning the first gate electrode 11.

However, on the other hand, if the film thickness a becomes large, ions will not be implanted during ion implantation, making it difficult to form low concentration source/drain regions. A problem arises in that the vertical step difference becomes large. Therefore, the film thickness a is preferably about 20 to 50 nm.

Next, as shown in FIG. 13(b), a conductive film 60 for forming a second gate electrode is deposited over the entire surface. The layer is formed of a polycrystalline S1 film doped with conductive impurities, a silicide film, a metal film such as W, or a composite film of these films. Therefore, the first gate electrode 11
It may be the same material as or a different material.

Thereafter, as shown in FIG. 13(Q), the conductive film 60 is anisotropically etched to form the second gate electrode 6.
is processed so that it remains on the side wall of the first gate electrode 11.
Next, the remaining film having a thickness a is etched using the second gate electrode 6 as a mask. Of course, the remaining film having a thickness a may be etched while over-etching the second gate electrode 6.

Subsequently, the second gate electrode 6 and the first gate electrode 1
An insulating film 7 is formed on the side wall of the 8-thick portion of the insulating film 7. Next, a highly doped source/drain region 4 of the same conductivity type as the lightly doped source/drain region 3, that is, an n-type, is coated with an insulating film 7.
form in a self-consistent manner.

According to this embodiment, the same effects as those of the above-mentioned embodiments can be obtained, and in addition, damage to the gate oxide film 2 and the Si substrate 8 caused by etching the first gate electrode can be removed. Moreover, since the remaining film having a film thickness of a is thin, in the state shown in FIG. 13(e) in which a portion of the film thickness of 8 is etched, there is no vertical step on the gate side wall portion, resulting in a gentle slope.

If the vertical step becomes large, a problem arises in that etching residual liquid is generated at the step in the subsequent multilayer wiring process.

Therefore, this embodiment also addresses this problem.

In the above explanations, emphasis has been placed on the relationship between the depletion layer width and the impurity concentration, but as is well known, the depletion layer width varies depending on the power supply voltage as well as the impurity concentration. Therefore, in consideration of the power supply voltage to be applied to an actual LSI and the impurity concentration of the lightly doped drain region, the depletion layer width of the lightly doped drain region is clarified and the depletion layer region in contact with the gate insulating film is completely overlapped. do it.

〔Effect of the invention〕

According to the present invention, since at least the depleted region of the drain region in contact with the gate insulating film can be overlapped with the gate electrode, the lateral electric field between the source and the drain can be relaxed.

Moreover, since the amount of overlap between the gate electrode and the drain region can be controlled arbitrarily and can be limited to the depleted region, it is possible to avoid the problem of an increase in parasitic capacitance due to an unnecessarily large amount of overlap. . Furthermore, when the present invention is applied to an LDD type MoS transistor, the above-mentioned overlap amount and the length of the lightly doped drain region are respectively adjusted while keeping the effective channel length between the lightly doped source and drain regions constant. Can be changed independently.

As a result, the electric field strength can be relaxed from 70% to about 50%, avalanche breakdown can be prevented, and a submicron device with high breakdown voltage can be realized.

In addition, by minimizing parasitic capacitance and overlapping the depletion region with the gate electrode, the transfer conductance can be increased to about twice that of a conventional LDD.
High-speed devices can be realized.

Furthermore, due to the structure of the present invention, the maximum point of the lateral electric field strength is located inside the gate electrode and inside the substrate, making it difficult for photocarriers generated at the drain to be injected into the gate insulating film. It also has the effect of suppressing characteristic deterioration due to the generation of hot carriers, reducing the deterioration of transfer conductance from 1/1G to 1/10 compared to conventional LDDs.
It can be set to about 0.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a MOS transistor according to the first embodiment of the present invention, FIG. 2 is a diagram showing the relationship between gate/drain overlap amount and lateral electric field strength, and FIG. 3 is a diagram showing the relationship between gate/drain overlap amount and lateral electric field strength. A diagram showing the relationship between the amount of overlap and the position of the point where the maximum electric field strength occurs. FIGS. 4(a) to 4(c) are sectional views of the manufacturing process of the second MOS transistor of the present invention, and FIGS. The figures are cross-sectional views of MOS transistors according to third to tenth embodiments of the present invention, and FIGS. 13(a) to (Q) are cross-sectional views of the manufacturing process of MOS transistors according to the eleventh embodiment of the present invention. 1.11...First gate electrode 2...Gate insulating film 3...Low concentration source/drain region 4...High concentration source/drain region 6...Second gate electrode 7...・Insulating film 8...Si substrate attorney Junnosuke Nakamura Figure 1 Figure 2 Figure 3 Gate throat over-knob amount (μm) Figure 6 Figure 6 71: Warm bite fF! Sauce Doshi 4 Sauce Chain Work 5 Figure 10 Figure 12 Figure 8: Silicone Cooking

Claims (1)

[Claims] 1. A semiconductor device having at least a gate electrode provided on a semiconductor substrate via a gate insulating film, and source/drain regions provided in a surface region of the semiconductor substrate on both sides of the gate electrode, A semiconductor device, wherein at least a region of the depleted region of the source/drain region that is in contact with the gate insulating film is covered with the gate electrode. 2. The semiconductor device according to claim 1, wherein at least the drain region of the source/drain regions consists of a low concentration region and a high concentration region in a direction away from the gate electrode. 3. A step of forming a first gate electrode on a semiconductor substrate via an insulating film, a step of forming a second gate electrode on the side wall of the first gate electrode, and a step of forming the semiconductor on both sides of the gate electrode. 1. A method of manufacturing a semiconductor device, comprising the step of doping impurities into a surface region of a substrate to form source/drain regions. 4. To form the second gate electrode, after depositing a conductive film for forming the electrode over the entire surface, anisotropic etching is performed to form the second gate electrode on the sidewall of the first gate electrode. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the semiconductor device is formed with a remaining gate electrode. 5. The method of manufacturing a semiconductor device according to claim 3, further comprising the step of forming an insulating film on the side wall of the second gate electrode using a CVD method or a thermal oxidation method. 6. The first gate electrode is composed of a thick part and a thin part, and above the thin part of the first gate electrode,
4. The method of manufacturing a semiconductor device according to claim 3, further comprising providing the second gate electrode on the sidewall of the thick portion. 7. After forming low concentration source/drain regions by impurity doping using the first gate electrode as a mask, forming the second gate electrode, and then forming an insulating film on the sidewalls of the second gate electrode. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the high concentration source/drain regions are formed by doping with impurities using the insulating film as a mask.