JPH0334550A - Mos transistor - Google Patents

Abstract

PURPOSE:To accurately control, to a desired value, an overlap size of a gate electrode with an n-type diffusion region as a source-drain region of a low impurity concentration by providing the following: conductive spacers formed on both side faces in a length direction of the gate electrode; insulating spacers formed outside the individual conductive spacers. CONSTITUTION:A gate insulating film 12 and a gate electrode 13 which is composed of polycrystalline silicon doped with phosphorus are formed on a p-type semiconductor substrate 11. Then, an n-type impurity-introduced region 14a is formed; a heat treatment is executed to form an n-type diffusion region 14. Then, a polycrystalline silicon film 15 doped with phosphorus is formed by a vapor growth method; an anisotropic reactive ion etching operation of this film is executed to form polycrystalline silicon spacers 16 on side faces of the gate electrode 13. Then, silicon oxide spacers 17 are formed by a vapor growth method ot silicon oxide and by an anisotropic reactive ion etching operation, then, an n-type impurity-introduced region 18a is formed by making use of the gate electrode 13, the polycrystalline silicon spacers 16 and the silicon oxide spacers 17 as a mask for ion implantation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to MOS transistors, and in particular, the present invention relates to MOS transistors.
The present invention relates to a MOS transistor in which a train region is provided to relax the electric field near the drain so that the threshold voltage and gm do not change even after long-term use.

[Prior Art] Conventionally, as this type of MOS transistor, the one shown in FIG. 3 has been used. As shown in the figure, in the surface region of the p-type semiconductor substrate 31, an n+ type diffusion region 38 and an n- type diffusion region 34, which constitute source/drain regions, are formed. is gate insulation WA
A gate electrode 33 having a silicon oxide spacer 37 is formed on the side surface of the gate electrode 32 via the gate electrode 32 .

A MOS transistor having this structure is manufactured as follows. First, a gate electrode 33 is formed on a p-type semiconductor substrate 31 via a gate insulating film 32, and an n-type impurity is doped using this gate electrode 33 as a mask to form an n-type diffusion region 34. A silicon oxide spacer 37 is formed on the side surface of the gate electrode 33, and an n1 type diffusion region 38 is formed by doping with an n-type impurity using the gate electrode 33 and the silicon oxide spacer 37 as a mask.

[Problems to be Solved by the Invention] In the above-mentioned conventional type MOS transistor, the overlap size between the n-type diffusion region and the gate electrode is within a certain range, that is, within a range of approximately 0.2 to 0.3 μm. It is known that it is advantageous to increase gm and increase the current supply capability by ensuring that the gm is constant. However, in conventional MOS transistors, this overlap size is determined only by the heat treatment conditions after ion implantation, and therefore it is difficult to keep the overlap within the above range. Therefore, conventional transistors have drawbacks such as insufficient current supply capability and variations in characteristics.

[Means for Solving the Problems] A MOS transistor according to the present invention includes a gate electrode formed on a gate insulating film on a p-type semiconductor substrate, and a conductive spacer provided on a longitudinal side surface of the gate electrode. and,
an insulating spacer provided on an outer side surface of the conductive spacer; an n-type diffusion region formed in a surface region of the p-type semiconductor substrate in a self-aligned manner with respect to the gate electrode; and an n+ type diffusion region formed in a surface region of a p-type semiconductor substrate in self-alignment with the insulating spacer.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1(g) is a cross-sectional view showing one embodiment of the present invention, and FIGS. 1(a) to (f) are cross-sectional views for explaining the manufacturing process thereof. In order to form the MOS transistors and transistors shown in FIG. 1 (g), first, as shown in FIG. Forming the electrode 13 Next, as shown in FIG. 1(b), using the gate electrode 13 as a mask for ion implantation, n-type impurities such as phosphorus and arsenic are implanted at IX10'2 to IX1014/cnl.
The n-type impurity introduced into the n-type impurity introduction region 14a is activated by introducing the n-type impurity into the n-type impurity introduction region 14a, and then performing heat treatment at 900° C. or higher to form the n-type impurity introduction region 14a. ) As shown in FIG. 1(d), a phosphorus-doped polycrystalline silicon film 15 is formed by vapor phase epitaxy, and an anisotropic A reactive ion etching process is performed to form a polycrystalline silicon spacer 16 on the side surface of the gate electrode 13 as shown in FIG. 1(e).
), the silicon oxide spacer 17 is formed by a silicon oxide vapor phase growth method and anisotropic reactive ion etching, and then the gate electrode 13, the polycrystalline silicon spacer 16 and the silicon oxide spacer 17 are formed by ion etching. Arsenic or phosphorus as a mask for implantation
The n-type impurity doped region 18a is formed by doping to about 1015 to I.times.1016/cffI. lastly,
Heat treatment is performed to activate the impurity in the n-type impurity introduction region 18a, forming the n-medium diffusion region 18, as shown in FIG. 1(g).
Obtain the transistor shown in .

In this embodiment, the gate electrode f113 and the polycrystalline silicon spacer 16 constitute a new gate electrode, and the thickness of the polycrystalline silicon spacer 16 can be precisely controlled, and the n-type diffusion region can be Since the heat treatment during formation can be completed in a short time, according to the present invention, the overlap dimension between the newly formed gate electrode and the n-type diffusion region can be controlled to a desired value. Therefore, according to the present invention, it is possible to provide a transistor with a large current supply capability with little variation.

FIG. 2 is a sectional view showing another embodiment of the present invention,
In the figure, parts that are the same as those in the embodiment of FIG. 1 are given reference numbers having the same last digit. The difference between this embodiment and the previous embodiment is that the gate voltage f! The point is that a silicon oxide pA 29 is formed on 23. To manufacture the transistor of this embodiment, a silicon oxide film 29 is previously provided on the gate electrode 23 in a process step corresponding to FIG. 1(a), and the silicon oxide film 29 is shown in FIG. All you have to do is carry out the various steps. According to this embodiment, since the film thickness of the gate electrode 23 is not reduced when forming the spacers 26 and 27, a more reliable transistor can be provided.

In the above embodiments, the n-type diffusion region was formed to be deeper than the n" type diffusion region, but even if this was changed and the n-type diffusion region was formed to be shallower, good.

[Effects of the Invention] As explained above, according to the present invention, the gate electrode and
Since the overlap dimension with the n-type diffusion region, which is the source/drain region with low impurity concentration, can be precisely controlled to a desired value, it is possible to provide a transistor with high current supply capability and little variation in characteristics. .

[Brief explanation of drawings]

FIG. 1(g) and FIG. 2 are sectional views showing embodiments of the present invention, and FIGS. 1(a) to 1(f) are sectional views of FIG.
FIG. 3 is a sectional view showing a conventional example. 11.21.31...p-type semiconductor substrate, 12.22
．． 32...Gate insulating film, 13.23.33...
・Gate electrode, 14.24.34...n-type diffusion region, 14a...n-type impurity introduction region, 15...
Polycrystalline silicon film, 16.26... Polycrystalline silicon spacer, 17.27.37... Silicon oxide spacer, 18.28.38... N+ type diffusion region,
18a...N-type impurity introduced region, 29...Silicon oxide film.

Claims (1)

[Claims] Two first second conductivity type regions with high impurity concentration formed at a predetermined interval in a surface region of a first conductivity type semiconductor substrate, and opposing sides of the two first second conductivity type regions. on the semiconductor substrate between a second second conductivity type region with a low impurity concentration formed adjacent to each of the first second conductivity type regions and the two first second conductivity type regions; a gate electrode formed through a gate insulating film, conductive spacers formed on both longitudinal sides of the gate electrode, and insulating spacers formed on the outside of each conductive spacer. A MOS transistor comprising: a pn junction formed by the second second conductivity type region and the semiconductor substrate; a portion exposed on the surface of the semiconductor substrate is present under the gate electrode.