JPS62241375A - Manufacture of semiconductor integrated circuit device - Google Patents
Manufacture of semiconductor integrated circuit deviceInfo
- Publication number
- JPS62241375A JPS62241375A JP8361586A JP8361586A JPS62241375A JP S62241375 A JPS62241375 A JP S62241375A JP 8361586 A JP8361586 A JP 8361586A JP 8361586 A JP8361586 A JP 8361586A JP S62241375 A JPS62241375 A JP S62241375A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- film
- drain
- electrode wiring
- shaped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000004065 semiconductor Substances 0.000 title claims description 4
- 238000000034 method Methods 0.000 claims abstract description 20
- 238000009792 diffusion process Methods 0.000 claims abstract description 7
- 238000009279 wet oxidation reaction Methods 0.000 claims abstract description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052785 arsenic Inorganic materials 0.000 abstract description 3
- 238000005468 ion implantation Methods 0.000 abstract description 3
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 3
- 239000011574 phosphorus Substances 0.000 abstract description 3
- 238000001259 photo etching Methods 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 239000012535 impurity Substances 0.000 abstract 2
- -1 Arsenic ions Chemical class 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000007796 conventional method Methods 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000002250 progressing effect Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 235000015067 sauces Nutrition 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、Ｌ Ｄ Ｄ （Ｌｉｇｈｔｌｙ Ｄｏｐｓｄ
Ｄｒａｉｎ ）構造を持つＭＯＳ型トランジスタを構
成要素とする半導体集積回路装置に関し、ＭＯＳＯ８型
トランジスタＤＤ構造の形成方法に関する。[Detailed Description of the Invention] [Industrial Field of Application] The present invention is based on the LDD (Lightly Dopsd
The present invention relates to a semiconductor integrated circuit device having a MOS type transistor having a MOS transistor structure as a component, and relates to a method for forming a MOSO8 type transistor DD structure.
本発明は、ゲート電極配線を形成した後、ソース、ドレ
インに薄くかつ浅くドーピングをおこない、その後、ゲ
ート電極配線のサイドに酸化膜を約０．１μ属はど形成
した後、又、ソース、ドレインに、濃くドーピングして
拡散層を形成してＬＤＤ構造を形成するＩ、ＤＩ）構造
の形成方法であ、る。In the present invention, after forming the gate electrode wiring, the source and drain are doped thinly and shallowly, and after that, an oxide film is formed on the side of the gate electrode wiring to a thickness of about 0.1μ, and then the source and drain are doped. This is a method for forming a structure (I, DI) in which an LDD structure is formed by heavily doping and forming a diffusion layer.
ＭＯＳ−工Ｃの高集積化は年々進み、２年で約２倍のス
ピードで進んでいる。それにつれて、微細化も、２年に
１回のｖｉｌＪ合で進んでいて、現在、さかんに量産さ
れているプロセスは、チャンネル長が２μｍのプロセス
であり、開発されたのは約２年前である。現在、開発さ
れているのは１〜１．２μｍプロセスであり、今後、鍛
産化されていく事になる。チャンネル長が２μｍまでは
問題にならなかったが、１．５μｍ前後以下からホク・
ト工レフトロンのゲート酸化膜への注入によるｖｔｈの
シフトが大きな問題になってきた。特に、チャンネル長
が１〜１，５μ溝のプロセスでは、大きな問題となり、
トランジスタの構造自体を変更せざるを得なくなってき
た。すなわち、ドレインのゲート近傍の電界をかんわし
て、ホットエレクトロンの注入量を少なくする方法が検
討され、その結、％ ＩＩ Ｄ Ｄ構造が採用されるに
いたっている。The integration of MOS-C is progressing year by year, and the rate is about doubling every two years. Along with this, miniaturization is progressing at a biennial rate, and the process currently being mass-produced has a channel length of 2 μm, which was developed about two years ago. be. What is currently being developed is a 1-1.2 μm process, which will be used for forged production in the future. This was not a problem when the channel length was up to 2 μm, but from around 1.5 μm or less, it became difficult.
A shift in vth due to the injection of lefttron into the gate oxide film has become a major problem. In particular, this becomes a big problem in processes with channel lengths of 1 to 1.5 μm.
It has become necessary to change the structure of the transistor itself. That is, a method of reducing the amount of hot electron injection by controlling the electric field near the gate of the drain has been studied, and as a result, the % II DD structure has been adopted.
第４図〜第６図に、最も一般的な従来方法であるＬＤＤ
構造の製造方法を示し、従来技術について以下に説明す
る。Figures 4 to 6 show the most common conventional method, LDD.
A method of manufacturing the structure is presented and the prior art is described below.
第４図に示す様に、Ｐ型基板１１上にフィールド酸化膜
１２を部分的に形成し、さらにゲート酸化膜１３を形成
した後、ゲート電極膜を形成して、ホトエツチング工程
をへてゲート電極配線１４を形成する。第５図に示すよ
うに、その上から簿く、かつ浅く、リンをイオン打込み
でドーピングしＮ型拡散層１５を形成しｂ後、その上に
気相中から８１０．膜１６をデボジシ冒ンして形成する
。さらに、第６図に示すように、リアクテプイオン二ッ
チャーで異方性エツチングをおこない、ゲート電極膜Ｉ
Ｍ１４のサイドにＳｉＯ□膜を残し、さらにその上から
、濃く砒素をイオン打込みして、図のようにＮ 拡散層
を形成する。このようにしてＬＤＤ構造のトランジスタ
を形成する方法が一般的であるが、量産上は大きな問題
点がある。As shown in FIG. 4, a field oxide film 12 is partially formed on a P-type substrate 11, a gate oxide film 13 is further formed, a gate electrode film is formed, and the gate electrode is formed through a photo-etching process. Wiring 14 is formed. As shown in FIG. 5, an N-type diffusion layer 15 is formed by doping phosphorus by ion implantation from above, and then 810.degree. The film 16 is formed by debossing. Furthermore, as shown in FIG.
A SiO□ film is left on the side of M14, and arsenic is ion-implanted from above to form an N 2 diffusion layer as shown in the figure. Although this method of forming LDD structure transistors is common, there are major problems in mass production.
一つは、気相中からデボジシ層ンして形成するＳｉＯ，
［の膜厚がウェハー内、外ともばらつき、ゲート電極配
線のサイドに残る膜厚のバラツキのもとになる。又、リ
アクテプイオンエッチング工程でも、ウェハー内でエツ
チング速度がばらつき、サイドに残る膜厚のバラツキの
要因となっている。このサイドの膜厚のバラツキによっ
て、トランジスタの特性がばらつくのと、ソース、ドレ
インの拡散層及びゲート電極がエツチングによってダメ
ージを受けやすい。One is SiO, which is formed by depositing a layer from the gas phase.
The film thickness varies both inside and outside the wafer, causing variation in the film thickness remaining on the sides of the gate electrode wiring. Furthermore, in the react step ion etching process, the etching rate varies within the wafer, causing variation in the film thickness remaining on the sides. This variation in film thickness on the sides causes variations in transistor characteristics, and the source and drain diffusion layers and gate electrodes are susceptible to damage by etching.
本発明は、上記したようなゲート電極のサイドに残る膜
厚のバラツキをなくシ、ウェハー内ノトランジスタ特性
のバラツキをなくすのと、ソース、ドレイン及びゲート
電極の受けるダメージをなくシ、シいては歩留向上、量
産性向上を目的とするものである。The present invention eliminates variations in film thickness remaining on the sides of the gate electrode as described above, eliminates variations in transistor characteristics within a wafer, and eliminates damage to the source, drain, and gate electrodes. The purpose is to improve yield and mass productivity.
本発明による問題点の解決手段は、ゲート電極配線を形
成した後、ソース、ドレインに薄くかつ浅くドーピング
をおこない、その後、低温ウェット酸化によりゲート電
極のサイドに厚い酸化膜を均一に形成した後、ソース。The solution to the problem according to the present invention is to dope the source and drain thinly and shallowly after forming the gate electrode wiring, and then uniformly form a thick oxide film on the sides of the gate electrode by low-temperature wet oxidation. sauce.
ドレインに濃くドーピングして拡散層を形成し、均一な
特性を持つＬＤＤ構造のトランジスタを形成する方法で
ある。In this method, the drain is heavily doped to form a diffusion layer, thereby forming an LDD structure transistor with uniform characteristics.
第１図〜第３図に本発明の方法によるＬＤＤ構造の製造
工程断面図を示し、以下に本発明の説明をおこなう。1 to 3 show cross-sectional views of the manufacturing process of an LDD structure according to the method of the present invention, and the present invention will be explained below.
第１図に示す様に、Ｐを基板１上にフィールド酸化膜２
を部分的に形成し、さらにゲート酸化膜３を形成した後
、ゲート電極膜を形成して、ホトエッチングエ［’へて
ゲート電極配線４を形成する。第２図に示すように、そ
の上から薄く、かつ浅く、リンをイオン打込みでドーピ
ングし、Ｎ型拡散ＰｆＩｓを形成する。その後、７５０
℃〜９５０℃程度の濃度でウェット酸化し、ゲート電極
配線４のサイドに厚（８１０，膜６を形成する。As shown in FIG. 1, P is applied to a field oxide film 2 on a substrate 1.
After partially forming a gate oxide film 3 and further forming a gate oxide film 3, a gate electrode film is formed and a photoetching process is performed to form a gate electrode wiring 4. As shown in FIG. 2, phosphorus is doped thereon thinly and shallowly by ion implantation to form N-type diffused PfIs. After that, 750
Wet oxidation is performed at a concentration of approximately .degree.
さらに第３図に示す様に、その上から濃く砒素をイオン
打込みして、ＩＪＤ′Ｄ構造のトランジスタを形成する
。Further, as shown in FIG. 3, arsenic is ion-implanted from above to form a transistor with an IJD'D structure.
以上のような本発明の方法によると、ゲー）？［極のサ
イドに残る酸化膜の膜厚のバラツキがほとんどなく、ウ
ェハー内のトランジスタ特性のバラツキもほとんどない
。又、ウェハー間のコントロールもよういである。又、
従来方法のように、ソース、ドレイン及びゲー）［極の
受けるダメージもなく、歩留向上、Ｍ産性向上の達成し
やすいプロセスである。According to the method of the present invention as described above, game)? [There is almost no variation in the thickness of the oxide film remaining on the side of the pole, and there is also almost no variation in transistor characteristics within the wafer. Also, wafer-to-wafer control is better. or,
Unlike the conventional method, there is no damage to the source, drain, and gate electrodes, and it is an easy process to improve yield and M productivity.
本発明の例では、Ｎチャンネルトランジスタの例を示し
たが、Ｐチャンネルトランジスタでも同様であり、相補
型のＭＯＳ−工Ｃでも同様であるIn the example of the present invention, an example of an N-channel transistor is shown, but the same applies to a P-channel transistor, and the same applies to a complementary MOS-C.
第１図〜第３図は本発明の方法による工程順の断面略図
である。
第４図〜第６図は従来の方法による工程順の断面略図で
ある。
以 上FIGS. 1 to 3 are schematic cross-sectional views of the process steps according to the method of the present invention. FIGS. 4 to 6 are schematic cross-sectional views of the steps of the conventional method. that's all
Claims (1)
る半導体集積回路装置の製造方法において、ゲート電極
を形成した後、ソース、ドレインにライトドープをおこ
ない、その後、ウエット酸化で該ゲート電極のサイドに
酸化膜を形成した後、ソース、ドレインに濃いドープを
して拡散層を形成してＬＤＤ構造を形成する事を特徴と
する半導体集積回路装置の製造方法。In a method for manufacturing a semiconductor integrated circuit device having a MOS transistor with an LDD structure as a component, after forming a gate electrode, the source and drain are lightly doped, and then an oxide film is formed on the side of the gate electrode by wet oxidation. 1. A method for manufacturing a semiconductor integrated circuit device, which comprises forming an LDD structure by doping the source and drain heavily and forming a diffusion layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8361586A JPS62241375A (en) | 1986-04-11 | 1986-04-11 | Manufacture of semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8361586A JPS62241375A (en) | 1986-04-11 | 1986-04-11 | Manufacture of semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62241375A true JPS62241375A (en) | 1987-10-22 |
Family
ID=13807391
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8361586A Pending JPS62241375A (en) | 1986-04-11 | 1986-04-11 | Manufacture of semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62241375A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3935411A1 (en) * | 1988-10-24 | 1990-04-26 | Mitsubishi Electric Corp | FIELD EFFECT SEMICONDUCTOR DEVICE OR FIELD EFFECT TRANSISTOR AND METHOD FOR THEIR OR THEIR PRODUCTION |
| DE3940540A1 (en) * | 1988-12-08 | 1990-06-13 | Mitsubishi Electric Corp | LDD-MOS DEVICE WITH A COMPONENT INSULATION AREA WITH AN ELECTROSTATIC SHIELDING ELECTRODE |
| US6180957B1 (en) | 1993-07-26 | 2001-01-30 | Seiko Epson Corporation | Thin-film semiconductor device, and display system using the same |
-
1986
- 1986-04-11 JP JP8361586A patent/JPS62241375A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3935411A1 (en) * | 1988-10-24 | 1990-04-26 | Mitsubishi Electric Corp | FIELD EFFECT SEMICONDUCTOR DEVICE OR FIELD EFFECT TRANSISTOR AND METHOD FOR THEIR OR THEIR PRODUCTION |
| DE3940540A1 (en) * | 1988-12-08 | 1990-06-13 | Mitsubishi Electric Corp | LDD-MOS DEVICE WITH A COMPONENT INSULATION AREA WITH AN ELECTROSTATIC SHIELDING ELECTRODE |
| US4998161A (en) * | 1988-12-08 | 1991-03-05 | Mitsubishi Denki Kabushiki Kaisha | LDD MOS device having an element separation region having an electrostatic screening electrode |
| US6180957B1 (en) | 1993-07-26 | 2001-01-30 | Seiko Epson Corporation | Thin-film semiconductor device, and display system using the same |
| US6808965B1 (en) | 1993-07-26 | 2004-10-26 | Seiko Epson Corporation | Methodology for fabricating a thin film transistor, including an LDD region, from amorphous semiconductor film deposited at 530° C. or less using low pressure chemical vapor deposition |
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