JPS63177471A - Mos-type semiconductor device - Google Patents

Abstract

PURPOSE:To enhance the controllability of the effective channel length and to prevent a punch-through phenomenon from occurring at a miniaturized MOS transistor by a method wherein a source-drain region is formed on a semiconductor substrate and only on both side-walls of a gate electrode. CONSTITUTION:A gate insulating film 3 and a gate electrode 4 are formed on one main face of a semiconductor substrate 1; impurity regions 5, 6 whose conductivity type is opposite to that of the semiconductor substrate 1 are formed on the semiconductor substrate 1 and only on both sides of the gate electrode 4. For example, after a gate oxide film 3 and a gate electrode 4 have been formed, an oxide film 7 is coated only on the periphery of the gate electrode 4, and polysilicon is then deposited. This polysilicon film is to contain phosphorus or arsenic. Then, said polysilicon film is left only on the side walls of the gate electrode 4 in the channellength direction by using an etching method or the like; a source 5 and a drain 6 are formed. In addition, impurities are diffused into silicon from the source 5 and the drain 6 during a subsequent heat-treatment process so that shallow junction regions 8, 9 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a MOS type semiconductor device, and particularly to a new structure for miniaturization thereof.

[Prior Art] □ A conventional semiconductor device of this type is shown in FIG. Figure 3 shows n
1 is a cross-sectional view showing a channel type MOS transistor (abbreviated as n-MOST), and a conventional manufacturing method will be briefly explained using this cross-sectional view. First, p-type high resistivity, for example 10
~30Ω・cm active region 102 of silicon substrate 101
Next, boron B is ion-implanted into the channel region to control the threshold voltage of the n-MOST. Next, a gate oxide film 1.3, a polysilicon electrode and a silicide electrode which will become the gate are formed. Subsequently, the n-type source region 1.5 and drain region 106 are treated with arsenic (As) or phosphorus (P).
Formed by ion implantation.

[Problem that the invention seeks to solve]

Such prior art structures have several drawbacks. One of them is that as the gate length becomes smaller, the distance between the source region 105 and the drain region 106 formed by a self-alignment method becomes smaller. Therefore, when a voltage is applied to the drain, the depletion layer generated from the drain region 106 extends particularly on the undoped substrate side, that is, the low concentration region, and the end of this depletion layer reaches the source region, causing a punch-through phenomenon. occurs. The second drawback is that since the source/drain regions are formed by ion implantation and heat treatment, the bonding portion is also diffused in the gate length direction, making the effective channel length shorter than the polysilicon length of the gate electrode.
The drawback of fine transistors is that they have poor controllability.

This invention was made to solve the problems of the conventional ones as described above, and it is possible to improve the controllability of the effective channel length in miniaturized MOS transistors, and
The object of the present invention is to obtain a MOS type semiconductor device that can suppress the punch-through phenomenon.

[Means for solving problems]

The MOS type semiconductor device according to the present invention has source/drain regions formed only on both side walls of a gate electrode on a semiconductor substrate.

[Effect]

In this invention, since the source/drain regions are formed on the semiconductor substrate and only on both side walls of the gate electrode, the length of the gate electrode becomes the effective channel length, and the low concentration impurity region under the gate channel The extension of the depletion layer from the drain due to the drop in potential at the source is difficult to reach the source, and the punch-through phenomenon can be suppressed.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1(a) shows an n-MO according to an embodiment of the present invention.
FIG. 1 is a cross-sectional view showing the structure of ST in the channel length direction; FIG. 1) is a cross-sectional view showing the structure in the channel width direction.

A method for manufacturing this n-MO8T will be explained.

After forming the gate oxide M*3 and the gate electrode 4, an oxide film 7 is formed only around the gate electrode 4.

Next, the polysilicon is debossed. This polysilicon film is
It may contain phosphorus (CP) and arsenic (As), or it may contain the above impurities after forming a non-doped polysilicon film. Next, the polysilicon is left only on the side walls of the gate electrode 4 in the channel length direction by etching or the like, and a source 5° drain 6 is formed. Further, by heat treatment in a post-process, impurities are diffused into the silicon from the source/drain to form a shallow junction region 8.9.

In this way, in this example, the source and drain are formed on both side walls of the gate electrode, so when a voltage is applied to the drain, the depletion layer extending from the drain deep in the channel region The distance it takes to reach the point is longer than before, and the punch-through phenomenon can be suppressed. The effective channel length can also be controlled by the patterning accuracy of the gate electrode.

FIG. 2 is a sectional view showing the structure of an n-MOST according to a second embodiment of the present invention.

In this example, the formation of the gate electrode and the surrounding oxide film are the same as in FIG.
In T, source 15. Drain 16 has a high concentration of arsenic (
It is formed by selective epitaxial growth of a silicon epitaxial layer containing As) or phosphorus (P).

〔Effect of the invention〕

As described above, according to the present invention, in the MOS type semiconductor device, the source/drain regions are formed on the semiconductor substrate and only on both side walls of the gate electrode.
The effect of reducing the potential in the deep region of the channel region due to the application of drain voltage increases the distance that the depletion layer extends from the drain to the source, suppressing the punch-through phenomenon, and obtaining a highly accurate effective channel length. There is.

[Brief explanation of the drawing]

FIG. 1(a) shows n-M○S according to an embodiment of the present invention.
Cross-sectional view in the channel length direction showing the structure of T, Figure 1(b)
is a sectional view in the channel width direction of the above embodiment, FIG. 2 is a sectional view showing the structure of an n-MOST according to a second embodiment of the present invention, and FIG. 3 is a sectional view showing the structure of a conventional n-MOST. It is. In the figure, 1.101 is a silicon substrate, 102 is an ion implantation region for threshold voltage control, and 3.7° 103.10
7 is an oxide film, 4,104 is a gate electrode, 5.15.10
5 is a source, and 6, 16.106 is a drain. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (3)

[Claims] (1) In a MOS semiconductor device, a gate insulating film and a gate electrode are formed on one main surface of a semiconductor substrate, and an impurity region of a conductivity type opposite to that of the semiconductor substrate is formed on the semiconductor substrate and at the gate electrode. A MOS type semiconductor device characterized in that the MOS type semiconductor device is formed only on both side wall portions of the MOS type semiconductor device. (2) The MOS type semiconductor device according to claim 1, wherein the impurity regions on both sides of the gate electrode are formed by doping polysilicon with phosphorus or arsenic. (3) The MOS semiconductor according to claim 1, wherein the impurity regions on both sides of the gate electrode are formed by selective epitaxial growth of a silicon epitaxial layer containing a high concentration of arsenic or phosphorus. Device.