JPS6115369A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent the kink phenomenon in a region of low drain voltage by a method wherein a source region of the second conductivity type is provided under a source region of the first conductivity type, and this second source region is located in the first source region to the drain side. CONSTITUTION:An insulator layer 22 and an active layer 23 are formed on a substrate 20. The active layer 23 is composed of a drain region 30, an active region 24, the first source region 32, and the second source region 28. The drain region 30 is opposed to the first and second source regions across the active region 24. The end surface of the second source region 28 on the active region 24 side is formed more distantly from the drain region 30 than the end surface of the first source region 32 on the active region 24 side. Such a construction can eliminate the kink phenomenon in the current-voltage characteristic at the low drain region and the decrease in the drain-source withstand voltage due to the parasitic bi-polar effect at the high drain voltage region.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a semiconductor device formed on an insulator and a method for manufacturing the same. The present invention relates to a semiconductor device with high source-to-source breakdown voltage and a method for manufacturing the same.

[Prior art]

FIG. 1 shows a conventional general structure of a semiconductor device formed on an insulator. Note that FIG. 1(a) is a plan view of the active layer inside the semiconductor device, and FIG. 1(b) is a sectional view of the semiconductor device.

In the figure, 2 is an insulating substrate, 4 is an active region made of a p-type semiconductor, 6 is a gate insulating film, 8 is a gate electrode, and lO is n
12 is a drain region made of an n-type semiconductor, 14 is a source electrode, 16 is a drain electrode, and the active region is 4° sonis region 10. drain region 12
An active layer 18 is formed.

This semiconductor device is used by grounding the source electrode 14, applying a positive drain voltage to the drain electrode 16, and applying a positive gate voltage to the gate electrode 8.

A depletion layer is generated near the drain region of the active region 4, but as the drain voltage is increased, the electric field within the depletion layer becomes stronger and a weak avalanche phenomenon occurs. That is, the speed of electrons flowing as a drain current increases, and the probability of generation of electron-hole pairs when these electrons collide with lattice atoms in the depletion layer increases. The electrons generated at this time flow into the n-type drain region 12, but some of the holes are injected into the n-type source region 10, and the other part remains temporarily in the active region 4.

The retention of holes in the active region 4 means that the potential of the active region 4 becomes higher, which lowers the threshold voltage of the device and causes an increase in the drain current. That is, a first kink appears as indicated by arrow A in the current-voltage characteristic diagram of FIG. This kink phenomenon appears as distortion when a signal is amplified by this semiconductor device.

If the drain voltage is further increased, the avalanche phenomenon becomes even more significant, the amount of holes generated increases, and the potential of the active region 4 continues to rise.

When the potential of the active region 4 becomes equal to or higher than the sealing voltage at the pn junction between the source region 1o and the active region 4, a large amount of holes in the active region 4 are injected into the source region 1o. This simultaneously causes activation 613! from the source region 10! This increases the back injection of electrons into i4, and the electrons reach the drain region, leading to the generation of a parasitic bipolar effect.

The occurrence of the parasitic bipolar effect appears as a second kink as shown by arrow B in the current-voltage characteristic diagram of FIG. 2, resulting in a significant decrease in the drain-source breakdown voltage.

Therefore, in order to eliminate the holes generated in the active region that cause the kink, it has been conventionally considered to add a region of the same conductivity type as the active region to the source region.

That is, by configuring the source region from an n-type source region 1° and a p-type source region 19 as shown in the cross-sectional view and active layer plan layout in FIG. This is intended to prevent the potential of the active region 4 from increasing by absorbing it in the source region 19.

However, in this semiconductor device, the surfaces of the n-type source region 1o and the p-type source region 19, which face the drain region 12, are arranged at almost the same position with respect to the drain region 12. It is difficult to capture all the holes generated in the depletion layer of the active region 4,
It is difficult to sufficiently prevent a portion of it from being implanted into the n-type source region 10.

Therefore, it was not possible to completely suppress the potential rise in the active region 4, and it was not possible to sufficiently suppress the deterioration of the drain-source breakdown voltage due to distortion during signal amplification and parasitic bipolar operation.

[Summary of the invention]

The present invention has been made to solve the above problems in 48 steps,
The aim is to completely eliminate the kink phenomenon in current-voltage characteristics, thereby providing a semiconductor device that exhibits good signal amplification characteristics and has a sufficiently high drain-source breakdown voltage. It's about doing.

In order to achieve such an object, the present invention provides a second conductivity type source region a below the first conductivity type source region, and sets the position of the surface of the second conductivity type source region facing the drain region to The first conductivity type source region is located closer to the drain region than the surface facing the drain region.

Hereinafter, the present invention will be described in detail along with examples.

〔Example〕

FIG. 4 shows an embodiment of a semiconductor device according to the present invention, in which FIG. 4(b) is a cross-sectional view and FIG. 4(a) is a plan view of the active layer inside the device.

An insulating layer 22 is formed on one side of the semiconductor substrate 20, and an active layer 23 is further formed thereon.

The active layer 23 includes a drain region 30 . made of an n-type high impurity concentration semiconductor. Active region 24 made of p-type semiconductor. It is composed of a first source region 32 made of a p-type high impurity concentration semiconductor and a second source region 28 made of an n-type high impurity concentration semiconductor.

Drain region 30 faces lower layer portion 32a of first source region 32 and second source region 28 with active region 24 in between.

The first source region 32 includes a lower layer portion 32a and an upper layer portion 32.
b, and the upper layer portion 32b is formed only above the outer end of the lower layer portion 32a.

The second source region 28 is formed on the first source region lower layer portion 32a and sandwiched between the first source region upper layer portion 32b and the active region 24.

Further, the end surface of the second source region 28 on the active region 24 side is located farther from the drain region 30 than the end surface of the first source region 32 on the active region 24 side, and The distance Ll to the region 30 is approximately 2/2 of the distance L2 between the second source region 28 and the drain region 30.
It is 3.

A gate insulating film 26 is formed on the active region 24, and a gate electrode 34 is further formed on it.

Further, a drain electrode 38 is formed on the drain region 3o, and the upper layer portion 32b of the first source region 32 and the second
A source electrode 36 is formed on the source region 28 .

Next, the operation of the semiconductor device configured as described above will be explained.

This device is operated by grounding the source electrode 36 and the semiconductor substrate 2°-, and applying a positive voltage to the gate electrode 34 and drain electrode 38.

When the voltage of the drain electrode 38 is increased, the electric field in the depletion layer generated near the drain region 3o of the active region 24 becomes stronger. Therefore, the probability of generating electron-hole pairs when electrons flowing as a drain current collide with lattice atoms in the depletion layer increases. The truth that occurred at this time was
Since a positive voltage is applied to the gate electrode, the vicinity of the interface between the active region 24 and the insulating layer 22 is diffused along this interface toward the source region.

On the other hand, in the source region, a first source W region 32 made of a p-type semiconductor is provided near the interface between the active region 24 and the insulating layer 22, so that the first source W region 32 made of a p-type semiconductor is generated in the active region 24 and diffused toward the source region. The holes are absorbed into the first source region 32. In particular, the first source region 32 is the second source region 2
8 protrudes toward the drain region 30, almost all of the holes generated in the active region 24 are captured in the first source region 32 before being lost to the second source region 28.

Therefore, the potential rise in the active region 24 is almost eliminated, and a kink phenomenon in the low drain voltage region due to a decrease in the threshold voltage and a decrease in the drain-source breakdown voltage due to the parasitic bipolar effect in the high drain voltage region do not occur. (
Become.

Note that in this embodiment, the distance L1 between the first source region 32 and the drain region 30 is approximately 2/3 of the distance L2 between the second source region 28 and the drain region 30;
The first source region 32 until Ll becomes about 1/2 of L2.
can be made to protrude in the direction of the drain region 3o. In order to efficiently absorb holes generated in the active region 24, it is preferable to shorten Ll, but conversely, the protrusion of the first source region 32 toward the drain region 30 causes the active region 2
Since it limits the spread of the depletion layer in 4,
It is desirable to select the optimal relationship between Ll and L2 according to the application conditions of this device.

Further, the insulating layer 22 may be a so-called semi-insulating layer.

Next, an embodiment of the method for manufacturing a semiconductor device of the present invention will be described with reference to FIG. Figure 5<a), (b).

(c), (e), and (f) are cross-sectional views of the semiconductor device during the manufacturing process.

First, about 1018 oxygen ions are implanted into the semiconductor substrate 20 at a predetermined energy by ion implantation.
After implanting crA, heat treatment is performed at a predetermined temperature for a predetermined time to form an insulating layer 22 having a predetermined depth and a predetermined thickness (FIG. 5(a)). As a result, the active layer 23 separated by the insulating layer 22 is formed on the upper surface of the semiconductor substrate 20.

Next, an active layer 23 formed on the upper surface of the semiconductor substrate 20
The gate insulating film 26 is formed on the active layer 23 by a method such as thermal oxidation.
)).

Next, a mask is made leaving a portion that is to become the lower part 32a of the first source region, and p-type impurities are implanted with a predetermined energy by ion implantation, thereby forming the interface between the active layer 23 and the insulating layer 22. A lower layer portion 32a of the first source region made of a p-type high impurity concentration semiconductor is formed nearby (
Figure 5(C)).

Furthermore, a mask is made leaving a portion that is to become the upper part 32b of the first source region, and p-type impurities are implanted using the same ion implantation method to form the upper part 32b of the first source region and the lower part 32a of the first source region. Together, they form a source region 32 having a hook-shaped cross section (FIG. 5(d)).

Next, a semiconductor layer is deposited to a predetermined thickness on the gate insulating film 26, and then etched to a desired size to form a material for the gate electrode. Furthermore, by using a mask to cover the first source region upper layer portion 32b and implanting n-type impurities by ion implantation, the second source region 28. Similarly, a drain region 30 made of an n-type high impurity concentration semiconductor and a low resistance gate electrode 34 made of an n-type semiconductor are formed. Note that the active layer 2
3, the first source region 32. By forming the second source region 28 and drain region 30, the remaining portion of the active layer 23 below the gate electrode 34 becomes the active region 24 (FIG. 5(e)).

Thereafter, the entire upper surface or insulator layer 22. An insulating film 40 is formed by a deposition method so as to cover the gate insulating film 26 and the gate electrode 34, and a portion of the upper surface of the first source region upper layer 32b, the upper surface of the second source region 28, and the upper surface of the drain region 30 is exposed. A contact hole is formed by etching as shown in FIG. Electrode material is deposited in this contact hole and shaped into desired dimensions and shapes by etching to form a source electrode 36 and a drain region 38 (FIG. 5(f)).

Although mask processing is used to form the first and second source regions and drain regions, predetermined impurities may be partially and selectively implanted into each region.

Further, the step of forming the active layer 23 on a part of the insulating layer 22 (FIG. 5(a)) does not necessarily need to be performed by the ion implantation method as in the above embodiment; Other known methods of formation may also be used.

〔Effect of the invention〕

As described above, according to the semiconductor device of the present invention, the second conductivity type source region is provided below the first conductivity type source region, and the surface of the second conductivity type source region facing the drain region is Since the position is closer to the drain region than the surface of the first conductivity type source region facing the drain region, kink phenomenon in the current-voltage characteristics in the low drain voltage region and parasitic bipolar phenomenon in the high drain voltage region are avoided. The decrease in drain-source breakdown voltage caused by this effect can be completely eliminated.

That is, (1) this type of device is known to perform a high-speed switching operation, and in addition, it can amplify a signal with low distortion. (2) Noise accompanying the kink phenomenon can be removed, which is effective in reducing noise. (3) Holes (majority carriers) generated near the drain region in the active region are extracted without being injected into the second source region, reducing the drop in breakdown voltage between the drain and source due to the parasitic bipolar effect. There are various advantages such as a higher voltage value.

Further, according to the manufacturing method of the present invention, an excellent semiconductor device can be easily realized without using any special manufacturing process.

[Brief explanation of the drawing]

FIG. 1(a) is a plan view of the active layer inside a conventional semiconductor device, FIG. 1(b) is a sectional view of the semiconductor device, FIG. 2 is a current-voltage characteristic diagram, and FIG. 3(a) is a diagram of the current-voltage characteristics. FIG. 4(b) is a plan view of the active layer of another conventional semiconductor device; FIG. 4(b) is a cross-sectional view of the semiconductor device; FIG. FIG. 5 is a plan layout view, FIG. 5B is a cross-sectional view of the semiconductor device, and FIG. 5 is a cross-sectional view of the semiconductor device showing an embodiment of the semiconductor device manufacturing method of the present invention. 20... Semiconductor substrate, 22... Insulator layer, 23...
- Active layer, 24... Active region, 26... Gate insulating film, 28... Second source region, 30... Drain region, 32... First source region, 32a... First Source region upper layer portion, 32b...first source region lower layer portion, 3
4... Gate electrode, 36... Source electrode, 38...
・Drain electrode. Patent wholesaler Nippon Telegraph and Telephone Public Corporation

Claims (2)

[Claims] (1) A drain region made of a first conductivity type high impurity concentration semiconductor formed on an insulating layer or a semi-insulating layer, and a drain region formed on the insulating layer or semi-insulating layer, one end surface of which is a first source region made of a highly impurity-concentrated semiconductor of a second conductivity type and facing a lower layer of the region; a first source region located further from the drain region than the drain region facing surface of the first source region;
a second source region made of a conductive type high impurity concentration semiconductor; an active region formed between the drain region and the first and second source regions on the insulating layer or semi-insulating layer; A gate electrode formed on the active region with an insulating film interposed therebetween, a source electrode formed on the first and second source regions, and a drain electrode formed on the drain region. Characteristic semiconductor devices. (2) a step of forming an active layer of a second conductivity type to a predetermined size on an insulating layer or a semi-insulating layer; a step of forming an insulating film on the active layer; and one end of the active layer. forming a lower layer portion of the first source region made of a second conductivity type high impurity concentration semiconductor near the interface with the insulating layer or semi-insulating layer; forming a first source region upper layer made of a second conductivity type high impurity concentration semiconductor above the active layer; forming a gate electrode on the insulating film; A second source region made of a highly impurity-concentrated semiconductor of a first conductivity type is provided in the active layer in a portion above a portion of the lower layer portion of the first source region and one side end surface of which is in contact with the side end surface of the upper layer portion of the first source region. forming a drain region made of a first conductivity type high impurity concentration semiconductor at one end of the active layer and opposite to the first and second source regions; 2. A method of manufacturing a semiconductor device, the method comprising at least the step of forming a source electrode and a drain electrode on top of a source region and a drain region, respectively.