JPH06244428A - Mos device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent a MOS device from deteriorating in characteristics due to radioactive exposure or an increased channel length by using the same mask to introduce impurity for forming first and second regions and then forming a gate oxide and a gate, electrode at relatively low temperature. CONSTITUTION:A thick oxide layer 13 is grown on an n<-> silicon substrate that includes a deep, p' diffused layer 8. A thin oxide film 14 is formed with a mask remaining so that B<+> 15 may be implanted only into the thin oxide film. A p-type diffused base layer 3 is formed, and a resist mask 16 is formed. After B<+> 15 is implanted, the resist mask 16 is removed and p<+> layer 9 is formed through annealing. A resist mask 17 is formed, and it is used, together with the oxide layer 13, as a mask to implant As<+> 18. After the resist mask is removed, an n<+> source layer 4 is formed through annealing. The oxide layers 14 and 13 are removed. Then, a gate oxide 51 is formed and a polycrystalline silicon layer is formed for a gate electrode 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a MOS type semiconductor device used in outer space such as being mounted on a geostationary satellite or used in a nuclear facility.

[0002]

2. Description of the Related Art MOS type semiconductor devices include a power MOSFET that uses only carriers and an insulated gate bipolar transistor that uses conductivity modulation by two types of carriers, electrons and holes. The insulated gate bipolar transistor is also called an IGT or COMFET, but will be referred to as an IGBT hereinafter.

FIG. 2 shows a cross-sectional structure of a conventional power MOSFET. A p-type base layer 3 is selectively formed on the surface layer of an n ⁻ high resistance layer 1 which is adjacent to an n ⁺ layer 2 as a drain layer on one side. And the n ⁺ source layer 4 is selectively formed on the surface layer of the base layer 3. A gate electrode 6 is provided from the exposed surface of the n ⁻ layer 1 to the surface of the n ⁺ source layer 4 via a gate insulating film 51, and the source electrode 7 insulated from the gate electrode 6 and the insulating film 52 is a p-type. Base layer 3 and n ⁺
It makes a common contact with the source layer 4, but has a deep p
^{A +} diffusion layer 8 and a shallow p ⁺ diffusion layer 9 are formed. The drain electrode 10 is in contact with the n ⁺ drain layer 2. This MOSFET is usually manufactured by the following steps.

First, the n ⁺ drain layer 2 and the n ⁻ high resistance layer 1
A deep p ⁺ diffusion layer 8 and a shallow p ⁺ diffusion layer 9 are formed by impurity diffusion from the surface of the n ⁻ layer 1 of the semiconductor substrate made of. Next, after the gate electrode 6 is formed on the surface of the high resistance layer 1 via the gate insulating film 51, a window is opened in the gate electrode 6 by photolithography. The p-type base layer 3 is formed by diffusion using the gate electrode 6 having the window opened as a mask. After that, the gate electrode 6 is again used as a part of the mask to form the n ^{+ -type} source layer 4, the front surface is covered with the insulating film 52, and a window for connection is opened to form the source electrode 7 and the back surface n. ^The drain electrode 10 is formed in contact with the ⁺ layer 2.
The semiconductor element manufactured in this way has the gate electrode 6
When a positive voltage exceeding the threshold value is applied to the source electrode 7, a channel 11 is formed on the surface of the p-type base layer 3 directly below the gate insulating film 51, and a high resistance is obtained from the source layer 4 through the channel 11. A so-called switching element is brought into a conducting state by injecting electrons into a drain layer composed of the layer 1 and the low resistance layer 2, and is brought into a blocking state by biasing the gate electrode 6 at the same potential as the source electrode 7 or negatively. Have a function as.

FIG. 3 shows a conventional IGBT, n^-High resistance
Below the layer 1, n as a buffer layer is provided.⁺P through layer 2
⁺There is a drain layer 12, and the drain is in this drain layer 12.
The electrode 10 is in contact. This element is p⁺Drain layer 12
And n⁺Buffer layers 2 and n ^-Semi-conductor consisting of high resistance layer 1
Through the process similar to power MOSFET using the body substrate
Can be manufactured. IGBT is power MOSFET
The difference in operation from T is that the drain layer 12 is p⁺It is a layer
From the source layer 4 to the channels 11, n^-Layer 1, n⁺Bag
P through the layer 2⁺When electrons are injected into layer 12, this
In response to p⁺Drain layer 12 to n⁺Through the buffer layer 2
That's n^-Holes are injected into layer 1, n^-Layer 1 is conductivity modulated
Is a point that causes low resistance.

[0006]

SUMMARY OF THE INVENTION The MOSF shown in FIG.
When ET is used in an atmosphere in which a large amount of radiation exists, such as around a nuclear reactor, and is irradiated with radiation, the threshold voltage often changes, and the ET does not function as a switching element. The cause of the change in the threshold voltage will be described with reference to FIG.

The operating principle of the switch function of the MOSFET is that when a positive voltage is applied to the gate electrode 6 with respect to the source electrode 7, the gate insulating film 51 functions as a dielectric, and the p-type base layer 3 immediately below the gate insulating film 51 functions. A negative charge is induced on the surface.
When the voltage applied to the gate electrode 6 is further increased, the amount of negative charges induced on the surface of the p-type base layer 3 also increases, and finally the concentration of the induced negative charges exceeds the impurity concentration of the p-type base layer 3. And a channel 11 are formed, and electrons injected from the n ⁺ source layer 4 pass through the channel 11 and reach the high resistance layer 1
And to the n-type drain layer composed of the low resistance layer 2 and becomes conductive. On the other hand, when the gate electrode 6 is biased at the same potential as the source electrode 7 or negatively with respect to the source electrode, negative charges are not induced in the p-type base layer 3 and the gate electrode 6 enters a blocking state.

When the MOSFET 20 having such an operating principle is irradiated with the radiation 20, electrons and holes are induced in the gate insulating film 51. Among them, holes are especially the gate insulating film 51.
Trapped inside, a positive fixed charge 21 is formed.
Therefore, the negative charge 22 corresponding to the fixed charge 21 is induced in the p-type base layer 3, and the state is as if a positive charge was applied to the gate electrode. As a result, the threshold voltage of the voltage applied to the gate electrode 6 is lowered. For example, the fixed charge generated in the gate insulating film 51 may be changed depending on the irradiation condition that the absorbed dose is 10 ⁶ rad or more.
There is a problem that a large amount of 21 causes a conductive state even when the gate electrode and the source electrode have the same potential, and a phenomenon in which the breakdown voltage apparently disappears is caused, resulting in loss of the switching function.

As a measure against the fluctuation of the threshold voltage or the loss of the switching function due to the radiation of the MOS type element, the maximum temperature in the step of forming the gate insulating film 51 and the step after the gate insulating film is formed is about 900. Efforts are being made to reduce the amount of fixed charges generated in the gate insulating film by lowering the temperature below ℃. But,
In the current manufacturing process, the self-alignment method of forming the p-type base layer 3 and the n ⁺ source layer 4 using the gate electrode 6 as the same mask is adopted, and a high temperature is used for diffusion of the base layer 3 and annealing of the source layer 4. Efficient manufacturing is performed using process conditions for a short time. On the other hand, in order to improve radiation resistance, when the temperature of the gate insulating film forming step and subsequent steps are lowered, the gate insulating film 51 forming step, the p-type base layer 3 forming step, and the source layer are formed. 4 The heating or diffusion time during the forming step is much longer than that under normal high temperature conditions by several tens to several hundreds of times, resulting in an inefficient manufacturing process.

On the other hand, when the p-type base layer 3 and the source layer 4 are formed before the gate insulating film is formed, the resist is removed at the time of forming the p-type base layer in order to introduce impurities with a resist mask. Therefore, the self-alignment structure is not formed, and as a result, the channel length becomes long, and R
_This is a disadvantageous process in which the _{DS (on)} is increased and the electrical characteristics of the device are deteriorated.

This problem is the same in the IGBT and also in the element exposed to radiation for use in outer space. The object of the present invention is to solve the above-mentioned problems, and the diffusion or annealing process is performed at a high temperature in a short time. It is an object of the present invention to provide an efficient manufacturing method of a MOS semiconductor device, which prevents deterioration and does not cause deterioration of characteristics due to an increase in channel length.

[0012]

To achieve the above object, the present invention comprises a step of selectively forming a first region of a second conductivity type on a surface layer of a semiconductor layer of a first conductivity type, Forming a second region of the first conductivity type selectively on the surface layer of the semiconductor layer; forming a gate insulating film on the surface of the semiconductor layer; and forming a gate electrode on the gate insulating film Including a step, having a second region selectively formed in the surface layer of the first region, of the portion sandwiched between the exposed portion and the second region of the first conductivity type layer of the first region. In a method of manufacturing a MOS type semiconductor device having a gate electrode via a gate insulating film, a step of forming a first region and a second region is performed by introducing impurities using the same mask, and after the step, A step of forming a gate insulating film and a gate electrode is performed. Then, it is effective that the mask used for forming the first region and the second region is made of a thermal oxide film, or is formed by laminating films of different materials. Further, it is effective that the manufactured MOS type semiconductor device is used in an artificial satellite or a nuclear facility.

[0013]

In the MOSFET or the IGBT, the first region serving as the base layer and the second region serving as the source layer are formed by the self-alignment method using the same mask, and the edge of the second region sandwiching the channel formation region and the second region are formed. The edges of one region can be brought close to each other with high accuracy, the channel resistance becomes extremely small, and the on-resistance can be kept low. Further, since the gate insulating film is formed after the formation of the first and second regions, even if the diffusion or annealing process is performed at a high temperature, the maximum temperature in the film formation of the gate insulating film and the subsequent process can be suppressed to be low. The amount of fixed charges generated in the gate insulating film by irradiation can be reduced.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 (a) to 1 (i) show in sequence the steps of manufacturing an n-channel MOS type semiconductor device according to an embodiment of the present invention.
The same parts as those in FIG. 3 are designated by the same reference numerals. First, a thick oxide layer 13 is grown on the surface of the n ⁻ silicon substrate 1 on which the deep p ⁺ diffusion layer 8 has already been formed. And
A thin oxide film 14 is formed by photolithography and etching leaving the mask portion, and boron ions (B ⁺ ) 15
If B is implanted with an appropriate energy, B ⁺ is implanted only in the thin oxide film portion [FIG. Then, the p-type base layer 3 is formed by diffusion [FIG. After that, a resist mask 16 is formed by photolithography, and B ⁺ 15 is injected with appropriate energy [see the same figure.
(c)] Then, the resist mask 16 is peeled off and annealed to form the p ⁺ layer 9 [(d) in the figure]. After that, the resist mask 17 is formed again by photolithography,
Using the mask and the oxide layer mask 13, arsenic ions (As
⁺ ) 18 is injected with appropriate energy (Fig. (E)),
After removing the resist mask 17, the resist mask 17 is annealed to form the n ⁺ source layer 4 [FIG. Next, the oxide film 14 and the oxide layer mask 13 are removed by etching [FIG.
], A gate insulating film 51 is formed on the surface thereof (FIG. 2 (h))
]. Then, a polycrystalline silicon layer is formed thereon, photolithography and etching are performed to form a gate electrode 6, and an insulating film is formed and patterning is performed by photolithography and etching to form an insulating film 52 to form a cell. Complete the structure [Fig. (I)].

The material of the mask 13 is stable even at a high temperature when the base layer 3 is formed, and is unlikely to be cracked, deformed, or changed in film quality. Even when it is removed by etching in the step of 1 (g), it is relatively easy to use the buffered hydrofluoric acid solution, and the source layer 4 and the base layer 3 including the high impurity concentration regions 8 and 9 are used.
The thermally-oxidized silicon film is excellent in that it can be performed without etching the surface of the drain layer 2.

According to these steps, the length l of the channel region is less than half the manufacturing method using the resist mask, and the channel resistance is also reduced, so that R _{DS (on)} is also reduced. Further, compared with the manufacturing method in which the diffusion of the base layer 3, the annealing of the high impurity concentration layer 9, and the annealing of the source layer 4 are performed at a low temperature after the gate insulating film 51 is formed, the diffusion of the base layer 3 and the annealing of the source layer 4 are performed. Since the process can be performed at a high temperature, the process time can be shortened to a fraction of one to several hundreds, which is a very short time.

FIGS. 5 (a) to 5 (i) also show the n-channel M
A process of another embodiment for manufacturing an OS type semiconductor device is shown, and the same parts as those in FIGS. 1, 2 and 3 are designated by the same reference numerals. In this case, a thin oxide film 14 is formed on the n ^- silicon substrate 1, a mask layer 23 made of silicon oxide, polycrystalline silicon or silicon nitride is deposited thereon by a CVD method, and a window is opened by photolithography. Then, a mask pattern is formed, and B ⁺ 15 is injected with an appropriate energy [FIG. The figure after this
Formation of the base layer 3 in (b), formation of the resist mask 16 and implantation of B ⁺ 15 in the same figure (c), peeling of the resist mask 16 and formation of the p ⁺ layer 9 in the same figure (d), e) forming a resist mask and implanting As ⁺ 18, removing the resist mask 17 and forming the source layer 4 in FIG. 6F, removing the oxide film 14 and the mask layer 23 in FIG. The formation of the gate insulating film 51 in h), the formation of the gate electrode 6 in FIG. 1 (i), the formation and patterning of the insulating layer 52 are the same as in FIGS. 1 (b) to 1 (i).

As in the case of the above-described ones, the channel region length 1 is one half or less of the manufacturing method using only the resist mask, and the channel resistance is small, and R _{DS (on )} Becomes small, the diffusion of the base layer 3, the annealing of the high impurity concentration layer 9, or the annealing of the source layer 4 after the gate insulating film 51 is formed can be formed in an extremely short time compared with the manufacturing method in which the annealing is performed at a low temperature.

In the above-mentioned embodiments, only the n-channel element has been described, but it goes without saying that this can be applied to the p-channel element and to the MOS type semiconductor element other than the power MOSFET and the IGBT. .

[0020]

According to the present invention, a part of a MOS type semiconductor device is formed as a channel forming region directly under the gate electrode and a second region for supplying charges to the channel is formed by forming a gate electrode. By performing impurity introduction by a self-alignment method using a mask formed on the surface instead of using a mask, the step of forming those regions or forming a high impurity concentration layer for preventing latch-up is performed as a gate insulating film. Since it is performed before forming, it can be performed at a high temperature and the process time is shortened. And the gate insulating film is
Since it can be formed at a low temperature of 900 ℃ or less, and it is not exposed to the high temperature of 900 ℃ or higher in subsequent processes,
The amount of fixed charges generated in the gate insulating film during irradiation of radiation can be reduced, and a MOS-type semiconductor element having radiation resistance can be manufactured at low cost. Moreover, since the first and second regions can be formed by the self-alignment method, the positional relationship between the first and second regions is good, the channel length is short, and an element with low on-resistance can be obtained.

[Brief description of drawings]

FIG. 1 is a sectional view showing the steps of manufacturing a MOS type semiconductor device according to an embodiment of the present invention in the order of (a) to (i).

FIG. 2 is a sectional view showing the structure of a power MOSFET.

FIG. 3 is a sectional view showing the structure of the IGBT.

FIG. 4 is a cross-sectional view showing the behavior of a MOS type semiconductor device during radiation irradiation.

FIG. 5 is a cross-sectional view showing the steps of manufacturing a MOS type semiconductor device according to another embodiment of the present invention in the order of (a) to (i).

[Explanation of symbols]

1 n ^- silicon substrate 3 p-type base layer 4 n ⁺ source layer 51 gate insulating film 6 gate electrode 13 oxide layer mask 14 oxide film 15 boron ion 17 resist mask 18 arsenic ion 23 mask layer

Claims (5)

[Claims] 1. A step of selectively forming a first region of a second conductivity type on a surface layer of a semiconductor layer of a first conductivity type, and a step of selectively forming a second region of the first conductivity type on a surface layer of the semiconductor layer. Forming a region, forming a gate insulating film on the surface of the semiconductor layer,
A step of forming a gate electrode on the gate insulating film, having a second region selectively formed in the surface layer of the first region, and a first conductivity type layer of the first region and a second region. In a method of manufacturing a MOS type semiconductor device having a gate electrode with a gate insulating film interposed between a portion sandwiched by a region, a step of forming a first region and a second region A method of manufacturing a MOS type semiconductor device, which comprises performing a step of forming a gate insulating film and a gate electrode after the step of introducing. 2. The method for manufacturing a MOS type semiconductor device according to claim 1, wherein the mask used for forming the first region and the second region is made of a thermal oxide film. 3. The M according to claim 1, wherein the masks used for forming the first region and the second region are formed by laminating films of different materials.
A method for manufacturing an OS type semiconductor device. 4. The M according to claim 1, wherein the manufactured MOS type semiconductor device is used in an artificial satellite.
A method for manufacturing an OS type semiconductor device. 5. The method for manufacturing a MOS semiconductor device according to claim 1, wherein the manufactured MOS semiconductor device is used in a nuclear facility.