JPH0234937A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0234937A JPH0234937A JP18499088A JP18499088A JPH0234937A JP H0234937 A JPH0234937 A JP H0234937A JP 18499088 A JP18499088 A JP 18499088A JP 18499088 A JP18499088 A JP 18499088A JP H0234937 A JPH0234937 A JP H0234937A
- Authority
- JP
- Japan
- Prior art keywords
- region
- diffusion
- channel
- gate electrode
- silicon substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 238000009792 diffusion process Methods 0.000 claims abstract description 35
- 238000005468 ion implantation Methods 0.000 claims abstract description 10
- 239000011261 inert gas Substances 0.000 claims abstract description 9
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 7
- 239000012535 impurity Substances 0.000 claims abstract description 7
- 150000002500 ions Chemical class 0.000 claims abstract description 7
- 238000010438 heat treatment Methods 0.000 claims abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 12
- 229910052710 silicon Inorganic materials 0.000 abstract description 12
- 239000010703 silicon Substances 0.000 abstract description 12
- 239000000758 substrate Substances 0.000 abstract description 12
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052786 argon Inorganic materials 0.000 abstract description 3
- -1 proton 14 Substances 0.000 abstract description 2
- 108091006146 Channels Proteins 0.000 description 13
- 238000000206 photolithography Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- KAPYVWKEUSXLKC-UHFFFAOYSA-N [Sb].[Au] Chemical compound [Sb].[Au] KAPYVWKEUSXLKC-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、不活性ガスイオン注入歪を利用して、深いチ
ャネル拡散を形成してなる半導体装置の製造方法、詳し
くは、二重拡散自己整合型ＭＯ８ＦＥＴ （ＤＭＯ３Ｆ
ＥＴと称す）の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor device in which deep channel diffusion is formed using strain induced by inert gas ion implantation, and more specifically, a method for manufacturing a semiconductor device in which deep channel diffusion is formed using strain induced by inert gas ion implantation. MO8FET (DMO3F
ET).
従来の技術
近年、ＤＭＯ５ＦＥＴは、高速スイッチング電源の電圧
石や、固体リレー用半導体素子として広（利用されてい
る。BACKGROUND OF THE INVENTION In recent years, DMO5FETs have been widely used as voltage sources for high-speed switching power supplies and semiconductor elements for solid-state relays.
以下に従来のＤＭＯ８ＦＥＴについて説明する。The conventional DMO8FET will be explained below.
第２図は、Ｎチャネル形ＤＭＯ８ＦＥＴを示すもので、
２５はゲート、２８はソース電極、２９はドレイン電極
、２１はＮ型シリコン基体、２７はＮ型ソース拡散領域
、２６及び３０はＰ型チャネル拡散領域で、浅い部分と
、深い部分を示している。Figure 2 shows an N-channel type DMO8FET.
25 is a gate, 28 is a source electrode, 29 is a drain electrode, 21 is an N-type silicon substrate, 27 is an N-type source diffusion region, 26 and 30 are P-type channel diffusion regions, and a shallow portion and a deep portion are shown. .
以上のように構成されたＤＭＯ８ＦＥＴでは、シリコン
基体２１の上面の所定拡散領域２６と絶縁膜との界面に
電流通路となるべきチャネルが形成され、ゲート電極２
５で電流制御を行なう。−方、深いソース拡散領域３０
は拡散領域２６の電位をソース電極２８の電位と等しく
するための低抵抗体を供する役割を果している。In the DMO8FET configured as described above, a channel serving as a current path is formed at the interface between the predetermined diffusion region 26 on the upper surface of the silicon substrate 21 and the insulating film, and the gate electrode 2
5 performs current control. - side, deep source diffusion region 30
serves to provide a low resistance material for making the potential of the diffusion region 26 equal to the potential of the source electrode 28.
発明が解決しようとする課題
しかしながら、上記の従来の構成では、ソース拡散領域
２７が、浅い拡散領域２６と深い拡散領域３０の２領域
から構成されていることから、半導体装置の製作工程上
、少なくとも２回の不純物拡散のための夫々のフォトリ
ソグラフ、熱処理工程が必要となる欠点を有していた。Problems to be Solved by the Invention However, in the above-described conventional configuration, since the source diffusion region 27 is composed of two regions, the shallow diffusion region 26 and the deep diffusion region 30, at least This method has the disadvantage of requiring two photolithography and heat treatment steps for impurity diffusion.
本発明は上記従来の問題点を解決しようとするもので、
ソース拡散領域を１拡散で構成し、かつ、低抵抗領域を
１回の不純物拡散処理工程で形成してＤＭＯ８ＦＥＴを
提供することを目的とする。The present invention aims to solve the above conventional problems,
It is an object of the present invention to provide a DMO8FET in which a source diffusion region is formed by one diffusion and a low resistance region is formed in one impurity diffusion process.
課題を解決するための手段
この目的を達成するために、本発明のＤＭＯ８ＦＥＴは
、ＦＥＴ形成領域のシリコン基体表部にプロントあるい
はアルゴン等の不活性ガスイオンをイオン注入法で注入
し、その後にゲート電極形成。Means for Solving the Problems In order to achieve this object, the DMO8FET of the present invention is manufactured by implanting ion implantation or inert gas ions such as argon into the surface of the silicon substrate in the FET formation region, and then implanting ions of an inert gas such as argon. Electrode formation.
チャネル拡散領域形成し、ソース、ドレイン電極形成す
る構成を有している。It has a structure in which a channel diffusion region is formed and source and drain electrodes are formed.
作用
この構成によると、チャネル形成前の不活性ガス注入に
よって、シリコン基体表部近くの結晶域にイオン注入歪
もしくは、結晶の乱れが生ずる。Effect: According to this configuration, ion implantation strain or crystal disorder occurs in the crystal region near the surface of the silicon substrate due to inert gas injection before channel formation.
この歪もしくは乱れを残留せしめて、チャネルを形成す
る不純物をイオン注入法によって、注入しかつ熱処理す
ると、通常の結晶体中で拡散する速度以上に拡散する、
いわゆるエンハンスド拡散が顕著に行なわれる。その結
果、通常方法による拡散プロファイルと異なる、深くて
、不純物元素の積分量の多いチャネル領域が形成でき、
低抵抗領域を形成できる。If this strain or disorder remains and the impurity that forms the channel is implanted by ion implantation and heat treated, it will diffuse faster than it would diffuse in a normal crystal.
So-called enhanced diffusion takes place significantly. As a result, a deep channel region with a large integrated amount of impurity elements can be formed, which is different from the diffusion profile obtained by conventional methods.
A low resistance region can be formed.
実施例
以下、本発明の一実施例について、図面を参照しながら
説明する。第１図（ａ）〜（ｄ）は本発明の実施例にお
けるＮチャネル型ＤＭＯ３ＦＥＴの製作工程を工程順断
面図で示すものである。第１図において、１１はＮ型シ
リコン基体、１２はゲート酸化膜、１３はＦＥＴ領域外
のフィールド酸化膜、１４はイオン注入法によって打込
まれたプロトン、１５はポリシリコンを素材としたゲー
ト、１６はチャネル領域を形成するためのＰ型拡散領域
、１７はソースとなるＮ１型拡散領域、１８はアルミニ
ウムを素材としたソース電極、１９はＮ型シリコン基体
にオーム接触したドレイン電極である。以上のように構
成されたＤＭＯ３ＦＥＴの製作工程を用いて、本発明を
説明する。EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings. FIGS. 1(a) to 1(d) are sectional views showing the manufacturing process of an N-channel type DMO3FET in an embodiment of the present invention. In FIG. 1, 11 is an N-type silicon substrate, 12 is a gate oxide film, 13 is a field oxide film outside the FET area, 14 is a proton implanted by ion implantation, 15 is a gate made of polysilicon, 16 is a P-type diffusion region for forming a channel region, 17 is an N1-type diffusion region that becomes a source, 18 is a source electrode made of aluminum, and 19 is a drain electrode in ohmic contact with the N-type silicon substrate. The present invention will be explained using the manufacturing process of the DMO3FET configured as described above.
第１図（ａ）では、基体１１０片面に、約１μの酸化膜
を形成してのち、フィールド酸化膜１３を残してアクテ
ィブなＦＥＴ形成領域をフォトリソグラフィ技術で酸化
膜を選択エッチして、さらに約１０００Ａのゲート酸化
膜１２をつけ、同片面の全面にドーズ量約１０１６ｃｍ
−２のプロトンを約１００ｋｅＶでイオン注入する。第
１図（ｂ）では、約０．５μ厚のポリシリコンを７００
℃で、ＣＶＤ技術で形成して後、所望の領域にフォトリ
ソグラフィ技術で形成して、ゲート１５を設け、約１０
１３ｃｍ−２のポロンイオンを約１００ｋｅＶで注入し
、かつ１１５０℃で、４時間熱処理を施すと、約６μｍ
深さのチャネル領域１６がセルファライン形成される。In FIG. 1(a), an oxide film of about 1μ is formed on one side of the substrate 110, and then the active FET formation region is selectively etched using photolithography, leaving the field oxide film 13. A gate oxide film 12 of about 1000 A is applied, and a dose of about 1016 cm is applied to the entire surface of the same side.
-2 protons are ion-implanted at about 100 keV. In Figure 1(b), 700 μm of polysilicon with a thickness of approximately 0.5μ is used.
℃ by CVD technology, and then formed in a desired area by photolithography technology to provide a gate 15.
When 13 cm-2 of poron ions are implanted at about 100 keV and heat treated at 1150°C for 4 hours, it becomes about 6 μm.
A deep channel region 16 is self-lined.
同図（Ｃ）では、約５ Ｘ １０ ”ｃｍ−２のリンイ
オンをイオン注入し、１０００℃で３０分間熱処理する
と、約０．８μ深さのソース拡散領域１７が同じ（セル
ファライン形成される。同図（ｄ）では、ソース領域に
所望のコンタクトホールをフォトリソグラフィ技術によ
って開孔し、ソース、ゲート上にアルミニウム電極をフ
ォトリソグラフィ技術でパターン形成する。また基体１
１の他の片面に金アンチモン膜を約１μｍ真空蒸着して
ドレイン１９を形成する。In the same figure (C), when phosphorus ions of about 5 x 10'' cm-2 are implanted and heat treated at 1000°C for 30 minutes, a source diffusion region 17 with a depth of about 0.8 μm is formed in the same manner (self-alignment). In the same figure (d), a desired contact hole is formed in the source region by photolithography, and an aluminum electrode is patterned on the source and gate by photolithography.
A gold-antimony film is vacuum-deposited to a thickness of about 1 μm on the other side of the drain 19.
以上の実施例によれば、プロトンの比較的大量の注入に
よって生じたシリコン基体表部の歪によって、その後注
入されたボロンは、いわゆるエンハンスド拡散によって
、比較的短時間に深い拡散が出来ると共に、拡散プロフ
ァイルもがウス分布からずれて、１０”ａｍ−３領域が
比較的長く伸びたプロファイルでシート抵抗が下がる。According to the above embodiment, due to the strain on the surface of the silicon substrate caused by the implantation of a relatively large amount of protons, the subsequently implanted boron can be deeply diffused in a relatively short time by so-called enhanced diffusion. The profile also deviates from the Gaussian distribution, and the sheet resistance decreases with a profile in which the 10" am-3 region extends relatively long.
この時、もちろん、ゲート１５の下端にも同様な拡散プ
ロファイルが得られ、ＤＭＯ８ＦＥＴのしきい値電圧は
約２．５ｖとなった。At this time, of course, a similar diffusion profile was obtained at the lower end of the gate 15, and the threshold voltage of the DMO8FET was approximately 2.5V.
シリコン基体に２゜０Ωｃｍリンドープ材を用いた時、
ドレイン、ソース耐圧が１２０ｖとなり、いわゆるサイ
リスク現象は約０ 、２ Ａ ／ １ ｃｖａゲート幅
まで現れなかった。従って、本発明によるＰ型拡散領域
１６は、従来構造ＤＭＯ８ＦＥＴの浅い拡散領域２６、
および深い拡散領域３０の両方の役割を果たすことがで
きる。When using 2゜0Ωcm phosphorus doped material on the silicon substrate,
The drain and source breakdown voltages were 120V, and the so-called sirisk phenomenon did not appear until the gate width was approximately 0.2 A/1 cva. Therefore, the P-type diffusion region 16 according to the present invention is similar to the shallow diffusion region 26 of the conventional structure DMO8FET.
and a deep diffusion region 30.
また、本発明の製作工程は従来法に比べて、浅い拡散領
域２６の形成工程が省けるという効果もあって、工業的
には非常に有用である。Further, the manufacturing process of the present invention has the effect of omitting the step of forming the shallow diffusion region 26 compared to the conventional method, and is very useful industrially.
なお、本発明はシリコンを基体としたＮチャネルＤＭＯ
８ＦＥＴばかりでなく、短時間に深い拡散を行なって製
作する他のデバイスにも有効である。Note that the present invention is an N-channel DMO based on silicon.
This method is effective not only for 8FETs but also for other devices manufactured by performing deep diffusion in a short period of time.
発明の効果
以上のように、本発明によれば、ＤＭＯＳＦＥＴのＦＥ
Ｔ領域全面に先ず、プロトンなど不活性ガスイオンを注
入し、次にゲートマスクでもってチャネル層をイオン注
入によって不純物導入し、その後の熱処理によって、深
いチャネル層が容易に形成でき、サイリスタ現象の抑制
できた出力特性が得やすいという優れたＤＭＯＳＦＥＴ
を実現できる。Effects of the Invention As described above, according to the present invention, the FE of DMOSFET
First, inert gas ions such as protons are implanted into the entire T region, then impurities are introduced into the channel layer by ion implantation using a gate mask, and by subsequent heat treatment, a deep channel layer can be easily formed and the thyristor phenomenon can be suppressed. An excellent DMOSFET that allows you to easily obtain the desired output characteristics.
can be realized.
第１図は本発明の実施例におけるＤＭＯＳＦＥＴの製作
工程順断面図、第２図は従来のＤＭＯＳＦＥＴの断面構
造図である。
１１・・・・・・Ｎ型シリコン基体、１２・・・・・・
ゲート酸化膜、１５・・・・・・ゲート、１６・・・・
・・チャネル拡散領域、１８・・・・・・ソース電極、
１９・・・・・・ドレイン電極、３０・・・・・・深い
チャネル拡散領域、２８・・・・・・ドレイン電極。FIG. 1 is a sectional view of a DMOSFET according to an embodiment of the present invention in the order of manufacturing steps, and FIG. 2 is a sectional view of a conventional DMOSFET. 11...N-type silicon substrate, 12...
Gate oxide film, 15... Gate, 16...
...Channel diffusion region, 18...Source electrode,
19...Drain electrode, 30...Deep channel diffusion region, 28...Drain electrode.
Claims (1)
〜１０＾１＾７ｃｍ＾−＾２の量でイオン注入し、次に
前記領域にゲート電極を所望の形状に形成し、同ゲート
電極を不純物拡散のマスクとして、チャネル領域をイオ
ン注入と熱処理によって形成後、所望のソース領域形成
および電極形成を行なう工程をそなえたことを特徴とす
る半導体装置の製造方法。First, 10^1^1 inert gas ions are applied to the FET forming area.
Ion implantation is performed at a dose of ~10^1^7 cm^-^2, then a gate electrode is formed in the desired shape in the region, and the channel region is implanted by ion implantation and heat treatment using the gate electrode as a mask for impurity diffusion. 1. A method of manufacturing a semiconductor device, comprising the steps of forming a desired source region and an electrode after formation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18499088A JPH0234937A (en) | 1988-07-25 | 1988-07-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18499088A JPH0234937A (en) | 1988-07-25 | 1988-07-25 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0234937A true JPH0234937A (en) | 1990-02-05 |
Family
ID=16162863
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18499088A Pending JPH0234937A (en) | 1988-07-25 | 1988-07-25 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0234937A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5108935A (en) * | 1990-11-16 | 1992-04-28 | Texas Instruments Incorporated | Reduction of hot carrier effects in semiconductor devices by controlled scattering via the intentional introduction of impurities |
| US5322802A (en) * | 1993-01-25 | 1994-06-21 | North Carolina State University At Raleigh | Method of fabricating silicon carbide field effect transistor |
| US5759904A (en) * | 1996-11-06 | 1998-06-02 | Southwest Research Institute | Suppression of transient enhanced diffusion in ion implanted silicon |
| US5869377A (en) * | 1984-08-22 | 1999-02-09 | Mitsubishi Denki Kabushiki Kaisha | Method of fabrication LDD semiconductor device with amorphous regions |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5840864A (en) * | 1981-09-03 | 1983-03-09 | Nec Corp | Manufacture of semiconductor device |
| JPS5954222A (en) * | 1982-09-21 | 1984-03-29 | Toshiba Corp | Manufacture of semiconductor device |
| JPS6014435A (en) * | 1983-07-04 | 1985-01-25 | Nec Corp | Forming method of p type region |
| JPS62211955A (en) * | 1986-03-12 | 1987-09-17 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
-
1988
- 1988-07-25 JP JP18499088A patent/JPH0234937A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5840864A (en) * | 1981-09-03 | 1983-03-09 | Nec Corp | Manufacture of semiconductor device |
| JPS5954222A (en) * | 1982-09-21 | 1984-03-29 | Toshiba Corp | Manufacture of semiconductor device |
| JPS6014435A (en) * | 1983-07-04 | 1985-01-25 | Nec Corp | Forming method of p type region |
| JPS62211955A (en) * | 1986-03-12 | 1987-09-17 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5869377A (en) * | 1984-08-22 | 1999-02-09 | Mitsubishi Denki Kabushiki Kaisha | Method of fabrication LDD semiconductor device with amorphous regions |
| US5108935A (en) * | 1990-11-16 | 1992-04-28 | Texas Instruments Incorporated | Reduction of hot carrier effects in semiconductor devices by controlled scattering via the intentional introduction of impurities |
| US5322802A (en) * | 1993-01-25 | 1994-06-21 | North Carolina State University At Raleigh | Method of fabricating silicon carbide field effect transistor |
| US5759904A (en) * | 1996-11-06 | 1998-06-02 | Southwest Research Institute | Suppression of transient enhanced diffusion in ion implanted silicon |
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