JPH06268162A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device wherein an ordinary-breakdown-strength MOS transistor and a high-breakdown-strength strength MOS transistor which have been made fine are provided without increasing the number of mask working processes by a method wherein a layer whose impurity concentration is effectively low is formed around a high-breakdown-strength diffusion layer. CONSTITUTION:In a semiconductor device, an ordinary-breakdown-strength MOS transistor 30 and a high-breakdown-strength MOS transistor 11 are formed inside the same well 32 existing near the surface of a semiconductor substrate 10. In the semiconductor device, the well 32 is a heavily-doped diffusion region, and a high-breakdown-strength diffusion layer 12 in which impurities whose conductivity type is opposite to that of impurities in the well 32 and which constitutes one part of the high-breakdown- strength MOS transistor 11 is provided. Then, a layer 13 whose impurity concentration is effectively low is formed around the high-breakdown-strength diffusion layer 12. Thereby, the prdinary-breakdown-strength MOS transistor and the high-breakdown- strength MOS transistor which have been made fine inside the same high-concentration well can be formed without increasing the number of mask working processes and with good productivity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device that operates with two or more kinds of power supply voltages and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 4 is a schematic cross-sectional view showing a semiconductor device which is operated by two kinds of power supply voltages which have been conventionally used. In the figure, 10 denotes a semiconductor substrate. In the semiconductor substrate 10, a high-concentration impurity diffusion region (hereinafter referred to as a high-concentration well) 32 in which impurities are diffused at a high concentration and a low-concentration impurity diffusion region (hereinafter, referred to as a low-concentration well) in which impurities are diffused at a low concentration are formed. Note 39). On the high-concentration well 32 side, a thin gate oxide film 35 formed on the high-concentration well 32, a field oxide film 33 connected to both ends of the thin gate oxide film 35, and a thin gate oxide film 35. An impurity having a conductivity type opposite to that of the high-concentration well 32 is diffused at a high concentration, which is formed in a region below the gate electrode 34 and the thin gate oxide film 35 formed above the gate electrode 34 except the lower portion of the gate electrode 34. The normal breakdown voltage MOS transistor 30 including the high concentration diffusion layer 37 is formed.

On the other hand, on the side of the low-concentration well 39, the thick gate oxide film 3 formed substantially in the center of the low-concentration well 39.
6. Field oxide film 3 on the left and right of the thick gate oxide film 36
3, a thin oxide film 35 'formed in the active region (source or drain region) with the gate electrode 3 interposed therebetween, and a gate electrode 3 formed from the thick gate oxide film 36 to the field oxide film 33.
4. A high-concentration diffusion layer 37 formed under the thin oxide film 35 'and a high breakdown voltage formed around the high-concentration diffusion layer 37, in which impurities of the same conductivity type as the high-concentration diffusion layer 37 are diffused at a low concentration. A high breakdown voltage MOS transistor 31 composed of a diffusion layer 38 is formed, and this high breakdown voltage MOS transistor 31 operates at a high power supply voltage.

MO that operates with the above-mentioned two types of power supply voltages
When forming a semiconductor device having the S transistors 30 and 31, first, the high-concentration well 32 and the low-concentration well 39 are formed in two steps by using two different masks on the semiconductor substrate 10.

[0005]

As described above, in order to form a semiconductor device which operates with two kinds of power supply voltages by the above method, first, two different kinds of masks are used, and the concentration is applied to different regions in two steps. High concentration well 32 of different
Since the low-concentration well 39 has to be formed, there is a problem that the number of mask work steps is increased.

On the other hand, in order to avoid the increase in the number of mask work steps, only a low-concentration well is formed near the surface of the semiconductor substrate, and the normal-voltage MOS transistor and the high-voltage MOS transistor are provided in the low-concentration well. Kind of M
A method of forming an OS transistor is also conceivable, but in this case, a channel area of a normally-breakdown-voltage MOS transistor must be increased, so that a size larger than a predetermined size is required, and there is a problem that there is a limit to miniaturization thereof. It was

The present invention has been made in view of the above problems, and can be achieved without increasing the number of mask work steps.
Moreover, it is an object of the present invention to provide a semiconductor device having a miniaturized normal withstand voltage MOS transistor and a high withstand voltage MOS transistor, and a method for manufacturing the same.

[0008]

To achieve the above object, a semiconductor device according to the present invention is a semiconductor device in which a normal breakdown voltage MOS transistor and a high breakdown voltage MOS transistor are formed in the same well existing near the surface of a semiconductor substrate. In the device, the well is a high-concentration impurity diffusion region, and is provided with a high breakdown voltage diffusion layer in which an impurity having a conductivity type opposite to that of the well is diffused to form a part of the high breakdown voltage MOS transistor. It is characterized in that a layer having a low impurity concentration is effectively formed around the breakdown voltage diffusion layer.

Further, in the above-described method for manufacturing a semiconductor device according to the present invention, a step of implanting and diffusing an impurity in a semiconductor substrate to form a high concentration impurity diffusion region (hereinafter referred to as a high concentration well), and the high concentration Impurities of the opposite conductivity type to those in the high-concentration well are implanted twice into predetermined portions of the well at different energies to effectively reduce the impurity concentration in the high-voltage diffusion layer and its periphery (hereinafter referred to as “impurity-low concentration layer”). It is characterized by including the process of forming).

[0010]

According to the above semiconductor device, a layer (impurity low concentration layer) where the impurity concentration of the well is effectively low is locally formed around the high breakdown voltage diffusion layer forming the high voltage MOS transistor. Is applied, the impurity low-concentration layer becomes a depletion layer, and the breakdown voltage of the high breakdown voltage MOS transistor becomes sufficiently high, so that it is possible to form a miniaturized normal breakdown voltage MOS transistor and high breakdown voltage MOS transistor in the same well. Become.

Further, according to the method of manufacturing a semiconductor device described above, only one type of mask is used to form a well, and the implantation of impurities for forming the low impurity concentration layer is performed by using the high breakdown voltage diffusion layer. It is possible to use the mask installed for forming the structure as it is, and the miniaturized normal breakdown voltage MOS transistor and high breakdown voltage MOS transistor are formed in the same well without increasing the number of mask work steps.

[0012]

Embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings. It should be noted that components having the same functions as those of the conventional example are designated by the same reference numerals.

FIG. 1 is a sectional view schematically showing a semiconductor device according to an embodiment, and in the drawing, 10 denotes a semiconductor substrate. In the vicinity of the surface of the semiconductor substrate 10, the high concentration well 3
In the high concentration well 32, the normal breakdown voltage MOS transistor 30 and the high breakdown voltage MOS transistor 11 are formed.

The normal breakdown voltage MOS transistor 30 has a thin gate oxide film 35 formed on the high-concentration well 32, a field oxide film 33 formed at both ends of the thin gate oxide film 35, and a thin gate oxide film 35. High-concentration diffusion in which impurities of the opposite conductivity type to the high-concentration well 32 are diffused and are formed in a region below the gate electrode 34a and the thin gate oxide film 35 formed above the gate electrode 34, except under the gate electrode 34. It is composed of layer 37.

On the other hand, the high breakdown voltage MOS transistor 11 is constructed as follows with the normal breakdown voltage MOS transistor 30 and the wide field oxide film 33 being separated from each other. That is, the high-breakdown-voltage MOS transistor 11 has a thick gate oxide film 36 formed on the high-concentration well 32 in a substantially central portion of the formation region of the high-breakdown-voltage MOS transistor 11, and field oxidation is performed on the left and right sides of the thick gate oxide film 36. A thin oxide film 35 ′ formed in the active region (source or drain region) with the film 33 interposed therebetween, a gate electrode 34 b formed from the thick gate oxide film 36 to the field oxide film 33,
High-concentration diffusion layer 3 formed under the thin oxide film 35 '
7. A high breakdown voltage diffusion layer 12 formed around the lower side of the high concentration diffusion layer 37, in which impurities of the same conductivity type as the high concentration diffusion layer 37 are diffused at a low concentration, and around the lower side of the high breakdown voltage diffusion layer 12. It is configured to include a low-impurity concentration layer 13 that is locally formed and has an effective low impurity concentration.

Thus, the presence of the impurity low-concentration layer 13 locally around the lower side of the high breakdown voltage diffusion layer 12 raises the withstand voltage and allows the high breakdown voltage MOS transistor to sufficiently perform its function. You can

Next, a method of manufacturing the semiconductor device according to the embodiment having the above structure will be described with reference to the drawings. 2 (a)-
7E is a cross-sectional view schematically showing the manufacturing process of the semiconductor device according to the example. FIG.

First, a p-type dopant such as B (boron) is implanted at a density of about 8.0 × 10 ¹² cm ^-2 near the surface of the n-type semiconductor substrate 10 made of silicon having a specific resistance of 4 to 8 Ωcm, Thereafter, a high temperature diffusion process is performed by heat treatment at about 1200 ° C. to form a p-type high concentration well 32 having a depth of about 3.5 μm, and a thermal oxidation process is further performed on the surface of the substrate 10 to form a thin thermal oxide film. 14 (FIG. 2)
(A)).

Next, except for the region where the high breakdown voltage diffusion layer 12 is formed, it is covered with a photoresist 15 by photolithography, and an n-type dopant such as P (phosphorus) is selectively applied to a portion not covered with the photoresist 15. 180 keV
And a density of about 1.0 × 10 ¹³ cm ⁻² to form a high breakdown voltage diffusion layer 12 (FIG. 2B).

Further, as shown in FIG. 2 (c), the same photoresist 15 is used, and P is equal to about 800 keV with a higher energy and a density of about 3 × 10 ¹² cm ^-2 as compared with the previous step. The n-type dopant is injected to effectively form a layer 13 having a low impurity concentration (low impurity concentration layer) 13 around the high breakdown voltage diffusion layer 12.

Next, after removing the photoresist 15,
The semiconductor substrate 10 is subjected to a wet oxidation process at 1000 ° C. by a selective oxidation method so that the field oxide film 33 has a thickness of about 6000.
Growth to a thickness of about Å, then a thin gate oxide film 3
5. Grow thin oxide layer 35 'and thick gate oxide layer 36. The heat treatment in the selective oxidation at 1000 ° C. also serves as the diffusion of the high breakdown voltage diffusion layer 12 and the low impurity concentration layer 13, and this heat treatment locally forms a low concentration impurity layer around the lower side of the high breakdown voltage diffusion layer 12. 13 is formed (Fig. 2
(D)).

Next, the gate electrode 3 is formed on the thin gate oxide film 35 and the thick gate oxide film 36 formed in the above process.
4a and 34b are formed, and the gate electrodes 34a and 34b are formed.
And using the field oxide film 33 as a mask, As (arsenic)
An n-type dopant such as the above is implanted at an energy of about 80 keV and a density of about 5.0 × 10 ¹⁵ cm ⁻² to form a high concentration diffusion layer 37 (FIG. 2E).

The high withstand voltage MOS transistor 11 and the normal withstand voltage MOS which are operated by two kinds of power supply voltages by the above steps
The transistors 30 can be formed in the same high-concentration well 32, and the normal breakdown voltage MOS transistor 30 can be formed.
Can be miniaturized, and high breakdown voltage MO can be achieved.
High breakdown voltage of the S transistor 11 can be ensured.

FIG. 3 shows the relationship between the depth direction from the semiconductor substrate surface and the impurity concentration in the following portions of the semiconductor device of the embodiment shown in FIG. 1 and the conventional semiconductor device shown in FIG. It is a graph. A is a high breakdown voltage M in the embodiment
A portion of the OS transistor 11 where the high-concentration diffusion layer 37 exists, B is the normal breakdown voltage MOS transistor 3 in the embodiment.
0 indicates a portion where the high concentration diffusion layer 37 exists, and C indicates a value in the portion where the high concentration diffusion layer 37 of the high breakdown voltage MOS transistor 31 exists in the conventional semiconductor device.

The profile of the impurity concentration from the high breakdown voltage diffusion layer 12 below the high concentration diffusion layer 37 of A to the high concentration well 32 has a conductivity opposite to that of the low concentration well 39 around the high breakdown voltage diffusion layer 38 (FIG. 4). There is a portion (impurity low-concentration layer 13) in which the impurity concentration is lower by one digit or more than the profile of the impurity concentration of C in which the ion of the type is not implanted, and the MOS transistor 11 having a higher breakdown voltage is formed. It can be seen that it is formed.

Actually, when the breakdown voltage of the high breakdown voltage MOS transistor 11 according to the embodiment was measured, it was proved that a high breakdown voltage MOS transistor was formed, which was 80 V or more.

In the semiconductor device of the present invention, the semiconductor substrate may be either n-type or p-type, and the high-concentration well is an n-type or p-type semiconductor in which impurities of a conductivity type opposite to that of the semiconductor substrate are diffused. is there. The impurity concentration of the high-concentration well is preferably about 5 × 10 ¹⁶ to 1 × 10 ¹⁷ cm ^−3, and the impurity low-concentration layer formed around the high-voltage diffusion layer is 1 × 10 ^{15 to} 5 × 10. It is preferable that the concentration is about ¹⁵ cm ^−3, which is lower than the high concentration well by about 1 to 2 digits.

In the method of manufacturing a semiconductor device described above, when the impurities in the high-concentration well and the impurities of the opposite conductivity type are implanted twice at predetermined locations in the high-concentration well, the first time is used. It is preferable to inject at an energy of about 150 to 180 keV and a density of about 1 × 10 ^{12 to} 3 × 10 ¹² cm ⁻² , and 700 to 900 ke for the second time.
It is preferable to implant with an energy of about V and a density of about 2 × 10 ^{13 to} 3 × 10 ¹³ cm ⁻² .

[0029]

As described above in detail, the semiconductor device according to the present invention is a semiconductor device in which a normal breakdown voltage MOS transistor and a high breakdown voltage MOS transistor are formed in the same well near the surface of a semiconductor substrate. , The well is a high-concentration impurity diffusion region, and an impurity having a conductivity type opposite to that of the impurity in the well is diffused so that the high breakdown voltage MO is obtained.
A high breakdown voltage diffusion layer forming a part of the S-transistor,
A layer having a low impurity concentration is effectively formed around the high breakdown voltage diffusion layer, the breakdown voltage of the high breakdown voltage MOS transistor is sufficiently high, and the normal breakdown voltage M is miniaturized in the same well.
A semiconductor device in which an OS transistor and a high breakdown voltage MOS transistor are formed can be provided.

In the method of manufacturing a semiconductor described above, a step of injecting and diffusing an impurity into a semiconductor substrate to form a high concentration well, and an impurity in the high concentration well at a predetermined position of the high concentration well. And a step of injecting impurities of opposite conductivity type twice at different energies to form a high breakdown voltage diffusion layer and a low impurity concentration layer around the diffusion layer, and increase productivity without increasing the number of mask work steps. The miniaturized normal breakdown voltage MOS transistor and the miniaturized breakdown voltage MOS transistor can be formed in the same well.

[Brief description of drawings]

FIG. 1 is a sectional view schematically showing a semiconductor device of the present invention according to an embodiment.

[1 of FIG. 2] and

2A to 2E are cross-sectional views schematically showing the manufacturing process of the semiconductor device according to the example.

3 is a graph showing the impurity concentration in the depth direction from the surface of the semiconductor substrate at a predetermined portion of the semiconductor device of the embodiment shown in FIG. 1 and the conventional semiconductor device shown in FIG.

FIG. 4 is a schematic cross-sectional view showing a conventional semiconductor device.

[Explanation of symbols]

 10 semiconductor substrate 11 high breakdown voltage MOS transistor 12 high breakdown voltage diffusion layer 13 low impurity concentration layer 30 normal breakdown voltage MOS transistor 32 high concentration well 33 field oxide film 34, 34a, 34b gate electrode 35 gate oxide film 35 'thin oxide film 36 thick gate Oxide film 37 High concentration diffusion layer 38 High breakdown voltage diffusion layer 39 Low concentration well

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location 8617-4M H01L 21/265 Z 9054-4M 29/78 301 S

Claims (2)

[Claims] 1. In a semiconductor device in which a normal breakdown voltage MOS transistor and a high breakdown voltage MOS transistor are formed in the same well existing near the surface of a semiconductor substrate, the well is a high concentration impurity diffusion region, and The high breakdown voltage MOS is formed by diffusing an impurity of a conductivity type opposite to that of the impurity.
A semiconductor device comprising a high breakdown voltage diffusion layer forming a part of a transistor, and a layer having a low impurity concentration being effectively formed around the high breakdown voltage diffusion layer. 2. A step of implanting and diffusing an impurity into a semiconductor substrate to form a high concentration impurity diffusion region, and a conductivity type opposite to that of the impurity in the high concentration impurity diffusion region at a predetermined position of the high concentration impurity diffusion region. 2. A step of implanting impurities twice with different energies to effectively form a high breakdown voltage diffusion layer and a layer having a low impurity concentration in the periphery thereof.
A method for manufacturing a semiconductor device as described above.