JPH04151875A - Double diffusion type mos transistor - Google Patents
Double diffusion type mos transistorInfo
- Publication number
- JPH04151875A JPH04151875A JP2277158A JP27715890A JPH04151875A JP H04151875 A JPH04151875 A JP H04151875A JP 2277158 A JP2277158 A JP 2277158A JP 27715890 A JP27715890 A JP 27715890A JP H04151875 A JPH04151875 A JP H04151875A
- Authority
- JP
- Japan
- Prior art keywords
- base region
- region
- mos transistor
- conductivity type
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009792 diffusion process Methods 0.000 title abstract description 12
- 239000000758 substrate Substances 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000012535 impurity Substances 0.000 abstract description 13
- 230000003071 parasitic effect Effects 0.000 abstract description 6
- 230000001133 acceleration Effects 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 230000007423 decrease Effects 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、第１導電型半導体基板上に形成された、上記
基板と同導電型のドレイン、ソース領域と、上記ソース
領域の周囲に形成された第２導電型のべ一ヌ領域とを有
する二重拡散型ＭＯＳ）ランジスタに関するものである
。Detailed Description of the Invention <Industrial Application Field> The present invention provides drain and source regions formed on a first conductivity type semiconductor substrate and having the same conductivity type as the substrate, and drain and source regions formed around the source region. The present invention relates to a double diffusion type MOS transistor having a second conductivity type base region.
〈従来の技術〉
従来の技術を用いた二重拡散型ＭＯ３）ランジヌタの構
造例を第４図に示す。図に於いて、■は第１導電型半導
体基板、２は第１導電型ドレイン領域（不純物拡散Ｎ）
、３は第２導電型ベース領域（不純物拡散層）、４は第
１導電型ソース領域（不純物拡散層）、５はフィールド
酸化膜（ロコス膜）、６はゲート酸化膜、７はゲート電
極、８は層間絶縁膜、９はドレイン電極、１０はソース
電極である。<Prior art> An example of the structure of a double diffusion type MO3) lunge nut using a conventional technology is shown in FIG. In the figure, ■ is the first conductivity type semiconductor substrate, 2 is the first conductivity type drain region (impurity diffusion N)
, 3 is a second conductivity type base region (impurity diffusion layer), 4 is a first conductivity type source region (impurity diffusion layer), 5 is a field oxide film (LOCOS film), 6 is a gate oxide film, 7 is a gate electrode, 8 is an interlayer insulating film, 9 is a drain electrode, and 10 is a source electrode.
上記に於いて、ベース領域３の不純物濃度は該トランジ
スタの閾値を決定するため、所望の値を得るためには比
較的低濃度（〜１０ｃｍ）で形成する。しかし、とのベ
ース領域３の抵抗値が高いと、ベース領域３の電位はソ
ース領域４のそれに比べ、部分的に置い領域を生じ、第
５図に示す寄生バイポーラトランジスタ１１がオン状態
になる。In the above, since the impurity concentration of the base region 3 determines the threshold value of the transistor, it is formed at a relatively low concentration (~10 cm) in order to obtain a desired value. However, if the resistance value of the base region 3 is high, the potential of the base region 3 is partially lower than that of the source region 4, and the parasitic bipolar transistor 11 shown in FIG. 5 is turned on.
〈発明が解決しようとする課題〉
前述のように、従来の技術では、寄生パイボーラトラン
ジヌタ１１がオン状態となるため、二重拡散型ＭＯ３＋
−ランジヌク動作時の耐圧が低下する（第６図）。<Problems to be Solved by the Invention> As described above, in the conventional technology, since the parasitic pibora transistor 11 is in the on state, the double diffusion type MO3+
- The withstand voltage during lunge operation decreases (Fig. 6).
本発明は上記問題点全解決する手段を提供するものであ
る。The present invention provides means for solving all of the above problems.
〈課題を解決するための手段〉
ソース領域下方のベース領域部分に、高加速エネルギ・
イオン注入装置を用いて、ベース領域と同導電型の不純
物を注入することにより、該ベース領域部分の抵抗を低
減する。<Means for solving the problem> High acceleration energy and
By implanting impurities of the same conductivity type as the base region using an ion implantation device, the resistance of the base region portion is reduced.
〈作 用〉
ソース領域下方のベース領域部分の低抵抗化により、寄
生パイポーラトランジスタの動作が抑ＩＪされ、二重拡
散５Ｍ０３）ランジヌタ動作時の耐圧低下が防止される
。高加速エネルギ・イオン注入技術により、ソース領域
下方ベース領域形成のみ低抵抗化するため、閾値を決定
するベース領域表面部分の不純物濃度を下げる必要がな
く、プロセスを複雑化せず、二重拡散型ＭＯ３）ランジ
スタの低入力電圧、高電源電圧動作全可能にする。<Function> By lowering the resistance of the base region below the source region, the operation of the parasitic bipolar transistor is suppressed, and a drop in breakdown voltage during double diffusion 5M03) range-input operation is prevented. High acceleration energy ion implantation technology lowers the resistance of only the base region below the source region, so there is no need to lower the impurity concentration on the surface of the base region, which determines the threshold, and the process is not complicated. MO3) Enables low input voltage and high power supply voltage operation of transistors.
〈実施例〉 以下、実施例に基づいて本発明の詳細な説明する。<Example> Hereinafter, the present invention will be described in detail based on examples.
第１図は本発明に係る二重拡散型ＭＯ３）ランジスタの
一実施例の構造を示す断面図である。FIG. 1 is a sectional view showing the structure of an embodiment of a double-diffused MO3 transistor according to the present invention.
従来のトランジスタと異なる点は、ソース領域直下のベ
ース領域部分が低抵抗化され、低抵抗ベース領域８１が
形成されている点である。その他の構成は、第４図のト
ランジスタと同一であるので、対応する部分には同一の
符号を符し、詳細な説明は省略する。The difference from conventional transistors is that the base region directly below the source region has a low resistance, forming a low resistance base region 81. The rest of the structure is the same as that of the transistor shown in FIG. 4, so corresponding parts are denoted by the same reference numerals and detailed explanation will be omitted.
以下、第２図全参照して製造方法について説明する。The manufacturing method will be described below with full reference to FIG.
通常のプロセスにより、Ｎ型Ｓｉ基板１に、ロコス酸化
（フィールド酸化膜５の形成）、グー１−電極（７）形
成、Ｐ型ベース拡散（ベース領域３の形成）ヲ行った後
、フォトリソグラフィー工程により、ベース領域内に低
抵抗領域を形成すべき箇所のみフォトレジスト１２に窓
開けし、ソース領域となる部分の下方のべ一ヌ領域部分
にピーク濃度をもつ様に、高加速エネルギ（〜ＩＭｅＶ
）でＰ型不純物（例えば、ボロン）をイオン注入する（
第２図（ａ））。After performing LOCOS oxidation (formation of field oxide film 5), formation of goo 1-electrode (7), and P-type base diffusion (formation of base region 3) on N-type Si substrate 1 using normal processes, photolithography is performed. Through the process, a window is opened in the photoresist 12 only at the location where a low resistance region is to be formed in the base region, and high acceleration energy (~ IMeV
) to ion-implant P-type impurities (e.g. boron) (
Figure 2(a)).
その後、Ｎ型不純物の導入により、ドレイン、ソース領
域２．４を形成し、層間絶縁膜８を堆積する（第２図（
ｂ））。以後、通常のプロセスを経て、第１図に示す構
造の二重拡散型ＭＯＳ）ランジスタが形成される。Thereafter, drain and source regions 2.4 are formed by introducing N-type impurities, and an interlayer insulating film 8 is deposited (see FIG. 2).
b)). Thereafter, a double diffusion type MOS transistor having the structure shown in FIG. 1 is formed through normal processes.
第３図は、第１図に於けるＡ−Ａ’部の深さ方向不純物
濃度プロファイルであり、Ｃ３はベース領域形成のため
に導入されたＰ型不純物の濃度プロファイル、Ｃ３１は
ベース領域部分的低抵抗化のために注入されたＰ型不純
物の濃度プロファイル、Ｃ４はソース領域形成のために
導入されたＮ型不純物の濃度プロファイルである。FIG. 3 is a depth direction impurity concentration profile of the A-A' section in FIG. C4 is the concentration profile of the P-type impurity implanted to lower the resistance, and C4 is the concentration profile of the N-type impurity implanted to form the source region.
〈発明の効果〉
以上詳細に説明したように、本発明の二重拡散ｆｆＭＯ
３）ランジスタによれば、ソース領域下方のベース領域
部分全低択抗化しているので、寄生バイポーラトランジ
スタの動作が抑制され、ＭＯＳトランジスタ動作時の耐
圧向上を達成することができるものである。<Effects of the Invention> As explained in detail above, the double diffusion ffMO of the present invention
3) According to the transistor, since the entire base region below the source region is made low resistance selective, the operation of the parasitic bipolar transistor is suppressed, and it is possible to achieve an improvement in the withstand voltage during the operation of the MOS transistor.
第１図は本発明の一実施例の断面図、第２図（ａ）及び
（ｂ）は同実施例の製造方法の説明に供する断面図、第
３図は同実施例に於ける深さ方向不純物濃度プロファイ
／Ｌ’に示す図、第４図は従来のトランジスタの断面図
、第５図は同トランジスタの等価回路図、第６図は同ト
ランジスタのＩ −Ｖ特性図である。
符号の説明
１：第１導電型半導体基板、 ２：第１導電型ドレイン
領域、 ３：第２導電型ベース領域、４：第１導電型ソ
ース領域、 ３１：低抵抗ベース領域。
代理人 弁理士 梅 １） 勝（他２名）Ａ′
第１図
ｗＸ３図
７ａ２図
第５図
第６図Fig. 1 is a sectional view of an embodiment of the present invention, Figs. 2(a) and (b) are sectional views for explaining the manufacturing method of the embodiment, and Fig. 3 is a depth diagram of the embodiment. 4 is a sectional view of a conventional transistor, FIG. 5 is an equivalent circuit diagram of the same transistor, and FIG. 6 is an I-V characteristic diagram of the same transistor. Explanation of symbols 1: First conductivity type semiconductor substrate, 2: First conductivity type drain region, 3: Second conductivity type base region, 4: First conductivity type source region, 31: Low resistance base region. Agent Patent attorney Ume 1) Katsu (and 2 others) A' Figure 1 wX3 Figure 7a2 Figure 5 Figure 6
Claims (1)
同導電型のドレイン、ソース領域と、上記ソース領域の
周囲に形成された第２導電型のベース領域とを有する二
重拡散型ＭＯＳトランジスタに於いて、 上記ソース領域下方のベース領域部分を低抵抗化したこ
とを特徴とする二重拡散型ＭＯＳトランジスタ。[Claims] 1. Drain and source regions formed on a first conductivity type semiconductor substrate and having the same conductivity type as the substrate, and a second conductivity type base region formed around the source region. A double-diffused MOS transistor comprising: a base region below the source region having a low resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2277158A JPH04151875A (en) | 1990-10-15 | 1990-10-15 | Double diffusion type mos transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2277158A JPH04151875A (en) | 1990-10-15 | 1990-10-15 | Double diffusion type mos transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04151875A true JPH04151875A (en) | 1992-05-25 |
Family
ID=17579612
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2277158A Pending JPH04151875A (en) | 1990-10-15 | 1990-10-15 | Double diffusion type mos transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04151875A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5701023A (en) * | 1994-08-03 | 1997-12-23 | National Semiconductor Corporation | Insulated gate semiconductor device typically having subsurface-peaked portion of body region for improved ruggedness |
| JP2001352070A (en) * | 2000-04-07 | 2001-12-21 | Denso Corp | Semiconductor device and method of manufacturing the same |
| JP2010212726A (en) * | 2000-04-07 | 2010-09-24 | Denso Corp | Semiconductor device and method of manufacturing the same |
-
1990
- 1990-10-15 JP JP2277158A patent/JPH04151875A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5701023A (en) * | 1994-08-03 | 1997-12-23 | National Semiconductor Corporation | Insulated gate semiconductor device typically having subsurface-peaked portion of body region for improved ruggedness |
| US5897355A (en) * | 1994-08-03 | 1999-04-27 | National Semiconductor Corporation | Method of manufacturing insulated gate semiconductor device to improve ruggedness |
| JP2001352070A (en) * | 2000-04-07 | 2001-12-21 | Denso Corp | Semiconductor device and method of manufacturing the same |
| JP2010212726A (en) * | 2000-04-07 | 2010-09-24 | Denso Corp | Semiconductor device and method of manufacturing the same |
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