JPH07249760A - Fabrication of semiconductor device - Google Patents

Abstract

PURPOSE:To realize a low threshold level without sacrifice of punch through voltage, in a DMOS device where a channel is formed based on the difference of diffusion length of double diffusion, by lowering the concentration at the surface part which determines the threshold level without lowering the concentration at the deep part of body thereby preventing the punch through. CONSTITUTION:After forming a body 4 by diffusion, impurities of opposite polarity are implanted using a same mask thus forming a p- compensated diffusion layer 5 where the concentration at the surface part is lowered to an extent causing no inversion of the body 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device.

[0002]

2. Description of the Related Art In recent years, attention has been paid to an intelligent power IC that incorporates a high voltage device, which is externally attached as a discrete device, into an IC chip of a logic circuit. Above all, DMOS devices, which can increase the breakdown voltage and suppress the channel resistance to a low level, have been actively used.

A general method of manufacturing an N-channel DMOS device will be described below with reference to FIGS. 6 (a) to 6 (c). After the gate oxide film 3 and the polysilicon film 2 are grown on the n ⁻ -type epitaxial layer 1 (or well or semiconductor substrate), the polysilicon film 2 is patterned by dry etching. After that, the photoresist film 11 and the polysilicon film 2 are formed on the source side.
A self-aligned p-type diffusion layer having a relatively thin impurity concentration is formed. This diffusion layer is hereinafter referred to as the body 4. Next, a p-type diffusion layer 8 having a high impurity concentration for making contact between the body 4 and the n-type diffusion layers 6 and 7 having a high impurity concentration serving as source / drain electrode outlets is formed. The sectional structure of the DMOS device formed by the above method is as shown in FIG.

The withstand voltage of a normal MOS transistor is determined by the withstand voltage of a junction between a diffusion layer having a high impurity concentration and a shallow drain diffusion layer and an epitaxial layer (or a well or a semiconductor substrate) which serves as a back gate, whereas that of a DMOS transistor. Since the breakdown voltage is determined by the junction between the epitaxial layer 1 (or well or semiconductor substrate) and the body 4 having a low impurity concentration and a deep depth, the DMOS transistor is more suitable for increasing the breakdown voltage. Further, the channel length of a normal MOS largely depends on the patterning accuracy of the polysilicon film of the gate electrode, but in the DMOS transistor, the channel length is determined by the difference in diffusion length from the same edge, and a short channel can be formed with high accuracy. , The on-resistance can be reduced. The same applies to the P-channel DMOS.

[0005]

The breakdown voltage between the source and drain of a transistor having an N-channel DMOS structure is defined as follows: the gate is ground, the source is at the same potential as the body, and the potential at ground and drain is raised to break down. The voltage is the breakdown voltage between the source and drain. At this time,
Epitaxial layer (or well or semiconductor substrate)
The junction between the and body is reverse biased, and the depletion layer spreads to both sides from the junction. To raise the breakdown voltage, it is better that the impurity concentration of the body is lower, but if it is too thin, the depletion layer on the body side spreads widely and reaches the diffusion layer where the impurity concentration of the source electrode is high, causing a punch-through breakdown. Therefore, the impurity concentration of the body can be reduced only to the extent that punch-through does not occur.
Along with that, the impurity concentration of the channel portion cannot be lowered, and the threshold value becomes high. That is, increasing the breakdown voltage and decreasing the threshold value conflict with each other.

The present invention solves the above problems.
A method of manufacturing a semiconductor device in which the impurity concentration of a body that causes punch-through is not lowered, but the impurity concentration of a surface portion that determines a threshold is lowered to realize a low threshold without lowering the punch-through withstand voltage. Is provided.

[0007]

In order to achieve this object, according to the present invention, after the diffusion layer of the body is formed, an impurity of the opposite type to the impurity injected for forming the body is implanted with the same mask. A structure in which the impurity concentration in the surface portion is lowered to the extent that the previously implanted body layer is not inverted is produced by compensation diffusion.

[0008]

According to the structure of the present invention, the impurity concentration in the deep portion of the body is so high that punch-through does not occur, and since the impurity concentration in the surface is low, the threshold value can be lowered. That is, the threshold value can be lowered while keeping the breakdown voltage high.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An N channel D which is an embodiment of the present invention will be described below.
A method of manufacturing a MOS device will be described with reference to FIGS.

As shown in FIG. 1, 40 to 40 are formed on the n ⁻ -type epitaxial layer 1 (or well or semiconductor substrate).
A gate oxide film 3 having a thickness of 100 nm is formed, and a polysilicon film 2 having a thickness of about 400 nm is grown on the gate oxide film 3. After patterning with the photoresist film 11, the polysilicon film 2 is patterned by dry etching. Next, the photoresist film for forming a body is patterned, and a p-type impurity is implanted into the source side. 15 in an inert atmosphere at a temperature of 1100 ° C
By driving in for 0 to 200 minutes, as shown in FIG. 2, the body 4 of about 1.5 to 2 μm is formed. Next, patterning is performed again using the same mask on which the body 4 is formed, and n-type impurities are implanted to such an extent that the p-type of the body 4 is not inverted. A p ⁻ compensation diffusion layer 5 whose concentration is thinned by compensation diffusion is formed. Then, as shown in Figure 4,
N-type diffusion layers 6 and 7 for attaching drain electrodes are formed by implantation. At this time, the body 4 and the source diffusion layer 6 are diffused from the same polysilicon film edge by self-alignment, and the difference in diffusion length becomes the channel portion 13.
Further, a p-type diffusion layer 8 that takes an electrode of the body is formed.
Then, after removing the photoresist film 11, FIG.
A field oxide film 12 is formed, and windows are selectively formed in the field oxide film 12 to form source and drain electrodes 9 and 10.

Although the N-channel DMOS device has been described in this embodiment, the present invention is also applicable to a P-channel DMOS device.

[0012]

According to the method of manufacturing a semiconductor device of the present invention, the impurity concentration in the deep portion of the body which is the breakdown portion 14 due to punch-through is high enough to prevent punch-through, and the threshold value is determined. Since the impurity concentration of the surface channel portion is low, the threshold value can be lowered. That is, the threshold value can be lowered without causing breakdown voltage deterioration.

[Brief description of drawings]

FIG. 1 is a process sectional view of an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a process cross-sectional view of an example of a method for manufacturing a semiconductor device of the present invention.

FIG. 3 is a process cross-sectional view of one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 4 is a process cross-sectional view of an example of a method for manufacturing a semiconductor device of the present invention.

FIG. 5 is a process cross-sectional view of one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 6 is a process sectional view of an example of a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

1 n ^{− type} epitaxial layer (or well or semiconductor substrate) 2 polysilicon film 3 gate oxide film 4 body 5 p ⁻ compensation diffusion layer 6 n type source diffusion layer 7 n type drain diffusion layer 8 p type diffusion layer 9 Source electrode 10 Drain electrode 11 Photoresist film 12 Field oxide film 14 Breakdown part by punch through

Claims (1)

[Claims] 1. A first conductivity type semiconductor substrate surface, a second conductivity type first surface using a polysilicon gate edge as a mask.
When a channel is formed by double diffusion in the order of the conductivity types, the second conductivity type impurity is diffused by diffusing the impurity of the first conductivity type having an increased impurity concentration in the vicinity of the surface of the diffusion layer of the second conductivity type forming the channel. Type impurity is compensated, and the effective concentration of the second conductivity type impurity in the vicinity of the surface is reduced.