JP2010212726A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the ESD surge tolerance of a lateral MOSFET (LDMOS). <P>SOLUTION: In the LDMOS, an n type region 6 is disposed surrounding an n+ type drain region 5 with a higher doping concentration than that of an n type substrate 1 while the concentration is higher closer to the n+ type drain region 5. A p+ type contact region 9 disposed adjacent to an n+ type source region 8 is made to enter under the n+ type source region 8. Thus, a parasitic transistor formed of n+ type source region 8, p type base region 7 and n type substrate 1 is made hard to turn on. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a lateral MOSFET (LDMOS) in which a source region and a drain region are arranged in a lateral direction of a semiconductor substrate.

  Generally, a power element has a configuration in which tens of thousands to hundreds of thousands of small LDMOSs are connected in parallel, and outputs are obtained by operating these LDMOSs simultaneously.

  However, when a large current is about to flow instantaneously, such as an ESD (electrostatic discharge) surge, not all LDMOSs flow a uniform current. There is a problem that the element breaks down and the wiring connected to the element is melted.

For this reason, improvement of ESD surge tolerance is demanded, and in particular, in an application field for automobiles, a high ESD surge tolerance of about 10 kV / mm ² is demanded. In order to improve the ESD surge resistance, conventionally, a method of adding an external element such as a capacitor outside the IC chip is employed. However, such a method inevitably increases the cost.

JP-A-4-151875 JP-A-4-273165 JP 11-330383 A

  An object of this invention is to provide the semiconductor device which can improve ESD surge tolerance in view of the said point.

  In order to achieve the above object, the present inventors have conducted the following studies.

  The non-uniformity of the current during the ESD surge is caused by, for example, variations in electrode resistance on the chip. That is, the closer to the wire bond portion, the smaller the wiring resistance and the easier the current flows, whereas the farther the wire bonding portion, the larger the wiring resistance and the less likely the current flows, causing non-uniform current.

  In consideration of such factors, a circuit in which the ESD surge generation circuit 50a shown in FIG. 13 is connected to the LDMOS chip 50b provided with the three-cell LDMOSs 51a, 51b, 51c, that is, the high-voltage generation circuit includes the three-cell LDMOS 51a. To 51c are connected, and resistors 52 and 53 corresponding to the wiring resistance corresponding to the distance from the wire bond portion are arranged between the drain terminals of the LDMOSs 51a to 51c.

  In the surge generation circuit 50a, when the switch 54 is turned on, power is supplied from the high voltage power supply 55 and the capacitor 56 is charged. When the switch 57 is turned on after the switch 54 is turned off, a current flows through each of the LDMOSs 51a to 51c of the three cells. At this time, since the L load 58 is included in the circuit, a large current flows through the LDMOSs 51a to 51c of the three cells.

  When simulation analysis was performed using such a circuit, the drain currents Id1, Id2, and Id3 of the MOSFETs 51a to 51c and the drain voltages Vd1, Vd2, and Vd3 of the MOSFETs 51a to 51c are expressed as shown in FIG. It was done.

  As can be seen from this figure, the drain current Id1 flowing in the LDMOS 51a directly connected to the power supply line has increased rapidly since the start of current concentration, whereas the power supply line via the resistors 52 and 53 has increased. The drain currents Id2 and Id3 flowing in the LDMOSs 51b and 51c connected to are reduced.

  As shown in FIG. 15, the current-voltage characteristic of the LDMOS has a negative resistance characteristic, and at the time of starting current concentration, the LDMOS 51a having a large current enters the negative resistance region as shown by the upward arrow in the figure. This is because the input positive feedback is applied to lower the drain voltage, but as shown by the downward arrow in the figure, the LDMOSs 51b and 51c are not in the negative resistance region, so that the drain current is lowered as the drain voltage is lowered.

  This negative resistance characteristic occurs because the drain current tends to increase and the source-drain voltage decreases despite the fact that the width of the depletion layer formed at the PN junction does not change. That is, the source-drain voltage corresponds to the integrated value of the electric field strength between the source and drain, but when the drain current becomes large, the electric field strength decreases, so the source-drain voltage decreases and the negative resistance It becomes a characteristic. When the change in the electric field strength distribution was examined for the case where the drain current was 20 A and the case where the drain current was 200 A by simulation, the results shown in FIGS. 16A and 16B were obtained. In addition, FIG. 17 shows the electric field strength at the AA ′ part in FIGS. 16 (a) and 16 (b). This result also shows that when the drain current increases, the source-drain voltage corresponding to the integrated value (area) of the electric field strength between the source and drain decreases, and negative resistance characteristics are generated.

  Since the current-voltage characteristics of the LDMOS have the negative resistance characteristics shown in FIG. 15, the resistance of the LDMOS 51a is in a negative state. Therefore, the voltage decreases as the current flows, and the current increases. On the other hand, the LDMOS 51b and 51c which are not in the negative resistance are in a positive state, so that the current decreases.

  For this reason, current concentration occurs in the LDMOS 51a, the LDMOS 51a is destroyed, and the wiring to which the LDMOS 51a is connected is blown.

  Therefore, the present inventors considered that if the negative resistance characteristic is improved, local current concentration can be prevented and the ESD surge resistance can be improved, and the negative resistance characteristic was improved.

  As described above, the negative resistance characteristic is generated because an attempt is made to increase the drain current despite the fact that the width of the depletion layer formed at the PN junction does not change. Therefore, it is considered that the negative resistance characteristic can be improved by adopting a structure in which the width of the depletion layer formed at the PN junction can be increased, that is, a structure in which the depletion layer is difficult to extend in the vicinity of the drain region.

  As a result of trial and error, the LDMOS shown in FIG. 18 was conceived as a structure satisfying the above conditions.

  The LDMOS has a structure in which a drain region is surrounded by an n-type region 6, and the n-type impurity concentration of the n-type region 6 increases with increasing proximity to the drain region 5 with the drain region 5 as a center. It has become.

For the LDMOS having such a structure, the concentration of the n-type region 6, specifically, the impurity concentration in the surface portion of the n-type region 6 (hereinafter referred to as the surface concentration) is changed to change the negative resistance characteristics. This was investigated by simulation analysis. The result is shown in FIG. However, in this simulation, the surface concentration of the n-type region 6 is within the range indicated by the hatched portion in FIG. 20, specifically, the surface concentration is 2 × 10 ¹⁷ from the surface concentration equivalent to the case where the n-type region 6 is not provided. The above analysis is performed as a diffusion condition that is changed within a range of about cm ^{−3 and} the depth of 2 μm from the substrate surface is 1/10 of the surface concentration.

  Looking at this result, it can be seen that there are two inflection points 1 and 2 in the negative resistance characteristic. One of these two inflection points 1 and 2 is considered to be caused by a parasitic transistor formed by the source region 8, the base region 7, and the drift region (n-type substrate 1) being turned on, while the other It is considered that the high electric field region is spread because the drain region 5 is reached.

  In order to analyze the factors of the two inflection points 1 and 2, as shown in FIG. 21, the LDMOS source region 8 shown in FIG. 18 is deleted to form a diode structure. The results shown in FIG. 22 were obtained.

  As is clear from this result, in the diode structure, only the inflection point 2 of the negative resistance characteristic exists. From this, it can be seen that the inflection point 1 of the two inflection points 1 and 2 occurred due to the parasitic transistor.

  Then, looking at the change of the remaining inflection point 2, it can be seen that the inflection point 2 increases as the surface concentration of the n-type region increases. That is, as the surface concentration is increased, the current value entering the negative resistance region increases, and it becomes difficult to enter the negative resistance region.

  Therefore, by increasing the surface concentration of the n-type region 6, it is possible to prevent a part of the LDMOS from entering the negative resistance region and causing a high current to flow locally, and to improve the ESD surge resistance. Become.

On the other hand, the remaining inflection point 2 is considered to occur because the high electric field region spreads to the drain region 5. In order to investigate how the high electric field region spreads, as shown in FIG. 23A, the surface concentration of the n-type region 6 is set to a predetermined value (here, 5 × 10 ¹⁶ cm ⁻³ ), and the drain current value is changed. The electric field strength distribution was investigated. As a result, the result shown in FIG. 23B was obtained. Note that the horizontal axis of the electric field intensity distribution in FIG. 23B corresponds to the horizontal direction of the diode structure shown in FIG.

  As can be seen from this figure, the high electric field region expands as the drain current increases. Therefore, in anticipation of a drain current that can be generated during an ESD surge, if the high electric field region reaches the drain region when the drain current is equal to or larger than that during the ESD surge (for example, 200 A), the ESD surge Even at times, some LDMOS can be prevented from entering the negative resistance region.

  As described above, by increasing the surface concentration of the n-type region, the current value when the LDMOS enters the negative resistance region can be increased, and the drain current is equivalent to that during the ESD surge. Alternatively, if the surface concentration of the n-type region is set so that the high electric field region reaches the drain region when it becomes larger, it is possible to prevent the LDMOS from entering the negative resistance region.

  Further, if the LDMOS has a structure in which the parasitic transistor is difficult to turn on, the inflection point 1 caused by the parasitic transistor can be improved, and the LDMOS can be prevented from entering the negative resistance region.

Accordingly, in the first aspect of the present invention, the substrate having the first conductive type semiconductor layer (1), the second conductive type base region (7) formed in the surface layer portion of the semiconductor layer, and the base region A first conductivity type source region (8) formed in the surface layer portion of the semiconductor layer, a first conductivity type drain region (5) disposed so as to be separated from the base region in the surface layer portion of the semiconductor layer, and a source region A base region located between the gate region and the drain region is defined as a channel region, a gate insulating film (10) formed on the channel region, a gate electrode (11) formed on the gate insulating film, and a source region And a drain electrode (14) connected to the drain region. The drain region is not configured to enter the lower part of the gate electrode, and further includes a semiconductor layer. Surface layer Is provided with a first conductivity type region (6) disposed between the drain region and the base region and surrounding the drain region, and the first conductivity type region has a higher concentration than the semiconductor layer. The first conductivity type region has a concentration of 5 × 10 ¹⁶ in the portion in contact with the drain region in the surface portion of the first conductivity type region. It is characterized by being 2 × 10 ¹⁷ cm ⁻³ .

  Thus, if the first conductivity type region formed between the drain region and the base region at a higher concentration than the semiconductor layer and having a higher concentration as it approaches the drain region, the LDMOS becomes a negative resistance region. The current value at the time of entering can be increased, and the ESD surge resistance can be improved.

Although the first conductivity type region and the base region may be in contact with each other, the concentration between the first conductivity type region and the base region is lower than that of the first conductivity type region as shown in claim 2. An area may exist. In this case, as shown in claim 3, the impurity concentration of the region having a lower concentration than the first conductivity type region is 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻³ .

  In the invention described in claim 4, the second conductivity type region (9) is provided so as to be in contact with the lower portion of the source region, and the second conductivity type region is configured to have a higher concentration than the base region. It is characterized by that.

  By providing the second conductivity type region having such a configuration, the parasitic transistor can be made difficult to turn on. This can prevent the LDMOS from entering the negative resistance region, and can further improve the ESD surge resistance.

  In this case, it is preferable to arrange the second conductivity type region so as to avoid the channel region.

  In the invention according to claim 6, the surface layer portion of the base region includes a second conductivity type contact region (9) disposed adjacent to the source region and connected to the source electrode together with the source region, The contact region is characterized in that it is formed at a higher concentration than the base region, and is configured to enter the lower part of the source region. In this way, the second conductivity type region described in claim 4 can be configured as a base contact region.

In the invention according to claim 8, the step of forming the first conductivity type region (6) in the surface layer portion of the semiconductor layer of the substrate having the first conductivity type semiconductor layer (1); Forming a LOCOS oxide film (4) partially opening on the semiconductor layer including the mold region and partially opening on the first conductivity type region and part of the semiconductor layer; and LOCOS oxidation of the semiconductor layer A step of forming a gate insulating film (10) in a portion where the film (4) is opened, a step of forming a gate electrode (11) on the gate insulating film including the LOCOS oxide film, and using the gate electrode as a mask, Forming a second conductivity type base region (7) in a surface layer portion of the semiconductor layer; forming a second conductivity type contact region (9) having a higher concentration in the base region than the base region; A source region (8) of the first conductivity type in the base region And forming a drain region (5) of a first conductivity type having a higher concentration than the first conductivity type region in the first conductivity type region, and on the gate electrode and including an interlayer above the substrate A step of forming an insulating film (12) and a source electrode (13) electrically connected to the source region and the contact region via the interlayer insulating film, and a drain electrically connected to the drain region Forming a first conductivity type region by performing ion implantation of the first conductivity type impurity, and setting the dose of the first conductivity type impurity to 1 × 10 ^14. a is cm ^-2 or less, it is characterized by setting the 2 × ¹⁰ 13 ^{cm -2} or more. By such a process, the semiconductor device shown in claim 6 or claim 7 can be manufactured.

In addition, by setting the dose of the first conductivity type impurity to 1 × 10 ¹⁴ cm ⁻² or less, the concentration of the first conductivity type region can be set to a level where the sustain characteristic is surely positive.

By setting the dose of the first conductivity type impurity to 2 × 10 ¹³ cm ⁻² or more, the depletion layer in which the concentration of the first conductivity type region extends in the first conductivity type region reaches the drain region. It can be done to the extent possible.

  The invention according to claim 9 is characterized in that the depth of the first conductivity type region is 2 to 4 μm. Thus, by setting the first conductivity type region to 2 μm or more, instability of the LOCOS oxide film interface due to the absorption of impurities into the LOCOS oxide film can be prevented. Further, by setting the first conductivity type region to 4 μm or less, it is possible to prevent an increase in on-resistance due to an increase in the source-drain spacing.

  The invention described in claim 10 is characterized in that the step of forming the first conductivity type region is performed prior to the step of forming the LOCOS oxide film. Thus, by forming the LOCOS oxide film after the formation of the first conductivity type region, heat at the time of forming the LOCOS oxide film can also be used for diffusion of the first conductivity type region.

The invention described in claim 11 is characterized in that the step of forming the contact region is performed after the step of forming the base region. By doing in this way, it can prevent that a contact region diffuses too much by the heat | fever at the time of formation of a base region. In the step of forming the contact region, for example, as shown in claim 12, the dose amount of the second conductivity type impurity is set to 2 × 10 ¹⁵ cm ⁻² or more. Further, as shown in claim 14, for example, the depth of the contact region is set to 1 μm or less.

  The invention according to claim 13 is characterized in that the step of forming the contact region is performed by high acceleration ion implantation. In this way, the contact region is formed at a position deeper than the surface of the semiconductor layer, and the effect that the concentration of the channel portion can be kept low even when the concentration of the first conductivity type region is increased is obtained.

  In the invention according to claim 15, in the case of forming the CMOS in the semiconductor layer of the substrate, the step of forming the well region of the first conductivity type disposed between the adjacent cells of the CMOS, It is characterized by sharing the forming process. In this way, the manufacturing process can be simplified by sharing the CMOS forming process.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

It is a figure which shows the cross-section of LDMOS in 1st Embodiment of this invention. It is a figure which shows the density | concentration profile in the AA 'part of FIG. It is a figure which shows the current-voltage characteristic at the time of breakdown of LDMOS shown in FIG. It is a figure when carrying out the simulation analysis of drain current and drain voltage using LDMOS shown in FIG. It is a figure which shows the manufacturing process of LDMOS shown in FIG. FIG. 6 is a diagram showing a manufacturing process of the LDMOS following FIG. 5. FIG. 7 is a diagram showing an LDMOS manufacturing process following FIG. 6; FIG. 8 is a diagram illustrating a manufacturing process of the LDMOS following FIG. 7. It is a figure which shows the cross-section of LDMOS shown in other embodiment. It is a figure which shows the cross-section of LDMOS shown in other embodiment. It is a figure which shows the cross-section of LDMOS shown in other embodiment. It is a figure which shows the cross-section of the MOS transistor formed with LDMOS shown in other embodiment. It is a circuit diagram assumed at the time of ESD surge. FIG. 14 is a diagram showing a simulation analysis of drain current and drain voltage using the circuit shown in FIG. 13. It is a figure for demonstrating the negative resistance characteristic of LDMOS. It is a figure when changing the electric current value and examining the change of electric field strength distribution. It is a figure which shows the electric field strength in the AA 'part of FIG. It is a figure which shows the cross-section of LDMOS which the present inventors considered. It is the figure which investigated the relationship between the density | concentration change of a n-type area | region, and a negative resistance characteristic. FIG. 20 is a diagram for explaining a range of concentration change in the n-type region shown in FIG. 19. It is a figure which shows the diode structure which deleted the source region from LDMOS shown in FIG. It is a figure which shows the negative resistance characteristic of the diode structure shown in FIG. It is a figure when electric field strength distribution is investigated by changing drain current value.

(First embodiment)
FIG. 1 shows a cross-sectional structure of an LDMOS to which an embodiment of the present invention is applied. The configuration of the LDMOS in this embodiment will be described below with reference to FIG.

  The LDMOS is formed on an SOI substrate in which an n-type substrate (semiconductor layer) 1 made of silicon and a p-type substrate 2 are bonded via an insulating film 3 made of a silicon oxide film.

The n-type substrate 1 has an impurity concentration of about 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻³ , and an insulating film 4 is formed on the surface of the n-type substrate 1. In the surface layer portion of the n-type substrate 1, an n + -type drain region 5 having a high concentration is formed so as to be in contact with the insulating film 4. An n-type region 6 is formed so as to surround this n + -type drain region 5. The n-type region 6 penetrates to the lower part of the insulating film 4 and is configured such that the concentration increases as the n + -type drain region 5 approaches the n + -type drain region 5.

  A p-type base region 7 is formed in the surface layer portion of the n-type substrate 1. This p-type region terminates near the end of the insulating film. The p-type base region 7 is partially deepened, and the deepened region functions as a deep base layer.

  An n + type source region 8 is formed on the surface layer portion of the p type base region 7 so as to be separated from the insulating film 4. Further, a p + type contact region 9 is formed on the surface layer portion of the p type base region 7 so as to be in contact with the n + type source region 8. The p + -type contact region 9 is arranged on the opposite side of the n + -type drain region 5 with the n + -type source region 8 interposed therebetween, and has a structure that penetrates to the lower layer portion of the n + -type source region 8.

  A gate insulating film 10 is disposed on the surface of the p-type base region 7 sandwiched between the n + -type source region 8 and the n + -type drain region 5 (insulating film). A gate electrode is formed on the gate insulating film 10. 11 is provided. With such a configuration, the surface layer portion of the p + -type base region 7 located below the gate electrode 11 is used as a channel region, and the MOS operation is performed using the n-type substrate 1 as an n-type drift region.

  An interlayer insulating film 12 is disposed so as to cover the gate electrode 11, and the source electrode 13 and the drain electrode 14 are patterned on the interlayer insulating film 12. The source electrode 13 is connected to the n + type source region 8 and the p + type contact region 9 through the contact hole formed in the interlayer insulating film 12, and the drain electrode 14 is connected to the n + type drain region 5.

  Although not shown, the SOI substrate surface is covered with a protective film or the like so as to cover the source electrode 13 and the drain electrode 14.

  Next, FIG. 2 shows a concentration profile in the AA ′ portion of FIG. 1, and the concentration relationship of each component of the LDMOS will be described.

As shown in FIG. 2, the n + type source region 8 and the n + type drain region 5 have a very high n type impurity concentration. In contrast, in the n-type region 6, the concentration is not as high as that of the n + -type source region 8 and the n + -type drain region 5, but the concentration is higher than that of the n-type substrate 1 and as it approaches the n + -type drain region 5 The n-type impurity concentration is increased in order. Specifically, the n-type region 6 has a concentration gradient so that the surface concentration in the portion of the n-type region 6 in contact with the n + -type drain region 5 is, for example, 5 × 10 ¹⁶ to 2 × 10 ¹⁷ cm ^−3. The configuration is

  That is, in the LDMOS of the present embodiment, the n-type region 6 having a higher concentration than the n-type substrate 1 is formed so as to surround the n + -type drain region 5, and the drain current is equal to or larger than that during the ESD surge. In this case, the high electric field region is configured to reach the n + -type drain region 5.

  In this way, by forming the n-type region 6 having a higher concentration than the n-type substrate 1 so as to surround the n + -type drain region 5, even if a large current drain current flows, the high electric field region is hardly expanded. In addition, the source-drain voltage corresponding to the integrated value of the electric field strength between the source and the drain can be kept high.

  For this reason, it is possible to prevent a decrease in the voltage between the source and the drain caused by the spread of the high electric field region generated during the ESD surge reaching the n + type drain region 5, and the current value when the LDMOS enters the negative resistance region can be reduced. Can be increased. Thereby, one of the two inflection points described above can be improved, and part of the LDMOS can be prevented from entering the negative resistance region even during an ESD surge.

  Further, the n-type region 6 is made thicker by adjusting the impurity concentration of the n-type region 6 so that the high electric field region reaches the n + -type drain region 5 when the drain current becomes equal to or larger than that during the ESD surge. Without exceeding, the current value when the LDMOS enters the negative resistance region can be increased.

  On the other hand, in the LDMOS in the present embodiment, the p + type contact region 9 is formed so as to enter the lower part of the n + type source region 8. More specifically, the p + -type contact region 9 enters the lower part of the n + -type source region 8 and does not enter the channel region. That is, when the channel region is formed, the p + type contact region 9 enters the lower part of the n + type source region 8 to the extent that the p + type contact region 9 has no influence.

  With such a configuration, a high-concentration p + type region is disposed between the n + type source region 8 and the p type base region 7, and the n + type source region 8, the p type base region 7, and n The NPN parasitic transistor formed by the mold substrate 1 (n-type drift region) can be made difficult to turn on.

  As a result, if the LDMOS has a structure that does not turn on the parasitic transistor, the inflection point caused by the parasitic transistor can be improved, and the LDMOS can be prevented from entering the negative resistance region.

  As a result of examining the current-voltage (Vd-Id) characteristics at the time of breakdown of the LDMOS having such a configuration, as shown in FIG. 3, the maximum value of the drain current Id that can be generated at the time of the ESD surge is 200 A or less. Assuming that, within this range, a characteristic that the voltage Vd does not decrease even when the drain current Id increases is obtained. That is, the characteristic that the current value entering the negative resistance region is about 200 A or more was obtained.

  Then, with respect to the LDMOS having the above configuration, a three-cell LDMOS was configured as shown in FIG. 13 and a simulation analysis was performed. As a result, the drain currents Id1, Id2, and Id3 of the LDMOSs 51a to 51c and the drains of the LDMOSs 51a to 51c The voltages Vd1, Vd2, and Vd3 are expressed as shown in FIG.

  As can be seen from this figure, the drain current Id1 flowing through the LDMOS 54a directly connected to the power supply line and the drain currents Id2 and Id3 flowing through the LDMOS 54b and 54c connected to the power supply line via the resistors 55 and 56 are substantially equal. In other words, only the drain current Id1 does not rise rapidly. Moreover, even if it sees drain voltage, it is not falling contrary to drain current Id1-Id3 rising.

  In this way, with the above configuration, the ESD surge withstand capability of the LDMOS can be improved.

  The LDMOS in this embodiment is different from the conventional LDMOS in that an n-type region 6 and a p + -type contact region 9 are formed. In these regions, impurities are ion-implanted on the surface of the n-type substrate 1. Or by solid phase diffusion. The n-type region 6 and the p + -type contact region 9 may be formed at any timing. However, since the n-type region 6 needs to be thermally diffused for a long time, the n-type drain region 5 and the n-type source are preferably used. It is better to form the region 8 before the p + type contact region 9.

  5 to 8 show an example of the manufacturing process of the LDMOS shown in this embodiment, and the manufacturing method of the LDMOS will be described based on these drawings. Here, a trench and the like for insulating and isolating the LDMOS from other element regions will be described with reference to the drawings.

[Step shown in FIG. 5A] First, an SOI substrate provided with an insulating film 3 such as an oxide film and an n-type epi layer (or n-type substrate) 1 on a p-type substrate 2 is prepared. Here, for example, the n-type epi layer 1 having an n-type impurity concentration of 1 × 10 ¹⁵ cm ⁻³ , a thickness of about 10 μm, and an oxide film 3 of about 2 μm is used.

  [Step shown in FIG. 5B] Photo-etching is performed on the n − type epi layer 1 to form a trench 20 reaching the insulating film 3. Then, the surface of the n − type epi layer 1 including the inner wall surface of the trench 20 is thermally oxidized, and the inner wall surface of the trench is covered with a thermal oxide film 21. Thereafter, a polysilicon film 22 is deposited so as to fill the inside of the trench 20, thereby forming an element isolation region by the trench 20.

[Step shown in FIG. 5C] After selectively ion-implanting p-type impurities, such as boron, into the outer peripheral region of the LDMOS, the n-type impurities are subsequently selectively applied to the surface layer portion of the n − -type epilayer 1. For example, phosphorus is ion-implanted in a dose range of 2 × 10 ¹³ to 1 × 10 ¹⁴ cm ⁻² . Thereby, the p-type impurity implantation layer 23 and the n-type impurity implantation layer 24 are formed.

At this time, since the dose amount of the n-type impurity is 1 × 10 ¹⁴ cm ⁻² or less, the sustain characteristic can be surely positive, and since it is 2 × 10 ¹³ cm ⁻² or more, FIG. It is possible to prevent the depletion layer extending in the n-type region 6 shown from reaching the n + -type drain layer 5.

  When forming a composite IC together with LDMOS in an SOI substrate, p-type impurity ion implantation for forming a P-well region in the CMOS portion of the composite IC is also performed during p-type impurity ion implantation in this step. Sharing.

  [Step shown in FIG. 6 (a)] Heat treatment is performed to thermally diffuse both the p-type impurity and the n-type impurity implanted in the step shown in FIG. 5 (c). Thereby, the impurities in the impurity implantation layers 23 and 24 are diffused, and the p-well region 25 and the n-type region 6 are formed. At this time, if the diffusion depth of the n-type impurity is reduced, the interface of the LOCOS oxide film becomes unstable due to the absorption of the impurities into the LOCOS oxide film 4 formed in a later step (see FIG. 6B), while if the depth is increased. It is preferable to set the diffusion depth to about 2 to 4 μm because the on-resistance is increased because the distance between the source and the drain must be set so as to allow the spread in the lateral direction. Since the breakdown voltage of the element is adjusted by the width of the n-type region 6, the width of the n-type region 6 is adjusted according to the required breakdown voltage.

  [Step shown in FIG. 6B] After forming an oxide film and a nitride film in order, an n + type drain region formed in a subsequent process (see FIGS. 7C and 8A) of the nitride film. 5 and the p-type base region 7 and a desired region such as the p-type well region 25 are removed, and then the n + -type drain region 5 and the p-type base region 7 are formed by a well-known LOCOS oxidation method in which thermal oxidation is performed. LOCOS oxide film 4 is formed between the two. Thereafter, the oxide film and the nitride film are removed. As described above, by performing the LOCOS oxide film formation after the n-type region 6 is formed, the heat at the time of forming the LOCOS oxide film can also be used for the diffusion of the n-type impurity.

  [Step shown in FIG. 6C] A gate oxide film 10 is formed between the LOCOS oxide films 4 by thermal oxidation or the like.

  [Step shown in FIG. 7A] After depositing a polysilicon film on the gate oxide film 10 and the LOCOS oxide film 4, the polysilicon film is patterned to form the gate electrode 11.

  [Step shown in FIG. 7B] Using the gate electrode 11 as a mask, boron, for example, is ion-implanted as a p-type impurity. Then, the p-type base region 7 is formed by thermally diffusing the implanted boron. At this time, it is preferable that the diffusion depth is about 2 μm, the diffusion temperature is 1000 ° C. or more, and the diffusion time is 2 hours or more.

[Step shown in FIG. 7C] Using the gate electrode 11 as a mask, for example, boron is ion-implanted as a p-type impurity in the source formation region. Then, p + type contact region 9 is formed by thermally diffusing the implanted boron. At this time, the dose amount of boron is 2 × 10 ¹⁵ cm ⁻² or more and 5 × 10 ¹⁵ cm ⁻² or less, the diffusion depth is 0.3 μm or more and 1 μm or less, and the surface concentration is about 1 × 10 ¹⁸ cm ^−3. Yes. Further, by selecting a temperature lower than the diffusion temperature at the time of forming the p-type base region 7 or a time shorter than the diffusion time, and selecting the mask width of the portion to be ion-implanted, the p-type impurity is introduced after the thermal diffusion. It does not reach below the gate electrode 11. Since this step is performed after the formation of the p-type base region 7, it is possible to prevent the p + -type contact region 9 from being excessively diffused by heat during the formation of the p-type base region 7.

  [Step shown in FIG. 8 (a)] Boron as a p-type impurity is ion-implanted into the surface layer portion of the p + type contact region 9 to form a higher concentration p + type region 9a. The n + type source region 8 and the n + type drain region 5 are formed by ion-implanting arsenic as an n-type impurity into a portion surrounding the p + type region 9a and the n-type region 6. At this time, the LOCOS oxide film 4 is used as a mask for the n + -type drain region 5, and the n + -type drain region 5 is formed in a self-aligned manner with respect to the LOCOS oxide film 4.

  [Step shown in FIG. 8B] After the interlayer insulating film 12 made of a BPSG film or the like is formed on the entire upper surface of the substrate including the gate electrode 11, the interlayer insulating film 12 is selectively removed to remove the n + type. Contact holes connected to the drain region 5, the p + type region 9 a and the n + type source region 8 are formed.

  [Step shown in FIG. 8C] After depositing an Al film on the interlayer insulating film 12, the Al film is patterned to electrically connect the p + type region 9a and the n + type source region 8 through the contact holes. The source electrode 13 connected to the n + type drain region 5 is formed, and the drain electrode 14 electrically connected to the n + type drain region 5 is formed.

  In this manner, an LDMOS capable of improving the ESD surge resistance as shown in FIG. 1 can be manufactured. Although the deep base layer shown in FIG. 1 is omitted in FIGS. 5 to 8, the width and range of ion implantation may be divided into two stages in the process shown in FIG.

(Other Embodiments) In the above embodiment, the case where the surface concentration is about 5 × 10 ¹⁶ to 2 × 10 ¹⁷ cm ⁻³ has been described as the concentration profile of the n-type region 6. If the n-type region 6 is at least higher in concentration than the n-type substrate 1 and increases in concentration as it approaches the n + -type drain region 5, the current value entering the negative resistance region is increased. it can.

  In the above embodiment, the p + -type contact region 9 is configured to enter the lower part of the n + -type source region 8. However, a p + -type region is formed separately from the p + -type contact region 9 and the n + -type source region is formed. If it arrange | positions so that the lower part of 8 may be contact | connected, the effect similar to the said embodiment can be acquired.

  In the above embodiment, the case where one embodiment of the present invention is applied to an SOI substrate in which an oxide film and an n-type epi layer are formed on a p-type substrate has been described. For example, FIG. As shown in FIG. 10, the present invention may be applied to the n-type epi layer 1 in which the buried n + -type layer 30 is formed in the portion located at the interface with the oxide film, and as shown in FIG. The present invention may be applied to a structure in which an n-type drift layer 31 having a higher concentration than that of the n-type epi layer 1 is formed in the upper layer portion.

  Further, high acceleration ion implantation is performed when the p + -type contact region 9 shown in FIG. 7C is formed, and a center range is provided at a portion of about 1 μm from the surface of the n-type epi layer 1 as shown in FIG. You may do it. In this way, even if the concentration of the p + -type contact region 9 is increased, the channel portion concentration can be kept low. It should be noted that when the p + -type contact region 9 is formed, ion implantation is preferably performed from the vertical direction.

  Furthermore, the LDMOS shown in the above embodiment is a P-channel MOS transistor as shown in FIG. 12, for example, a p + type source region 41 and a p + type in the surface layer portion of the n type layer 31 formed on the n type epi layer 1. A drain region 42 is formed, a gate electrode 44 is formed on the channel region with a gate oxide film 43 interposed between each p + type source region 41 and the p + type drain region 42, and an interlayer insulating film 45. May be formed together with the MOS transistor in which the source electrode 46 and the drain electrode 47 are formed. In this case, the formation process of the n-type region 6 provided in the LDMOS and the formation process of the n-type region 48 disposed between adjacent cells, specifically, between the source and drain of adjacent P-channel MOS transistors, Can be shared. Thereby, the manufacturing process can be simplified.

  In the above description, the n-channel type LDMOS has been described. Of course, the present invention can also be applied to a p-channel type LDMOS in which the conductivity type is inverted.

DESCRIPTION OF SYMBOLS 1 ... n-type substrate 2 ... p-type substrate 3 ... Insulating film 4 ... Insulating film 5 ... n + type drain region 6 ... n-type region 7 ... p-type base region 8 ... n + type source region 9 ... p + type contact region 10 ... Gate Insulating film 11 ... Gate electrode 12 ... Interlayer insulating film 13 ... Source electrode 14 ... Drain electrode

Claims (16)

A substrate having a semiconductor layer (1) of a first conductivity type;
A second conductivity type base region (7) formed in a surface layer portion of the semiconductor layer;
A first conductivity type source region (8) formed in a surface layer portion of the base region;
A drain region (5) of a first conductivity type disposed so as to be separated from the base region in a surface layer portion of the semiconductor layer;
A gate insulating film (10) formed on the channel region, wherein the base region located between the source region and the drain region is a channel region;
A gate electrode (11) formed on the gate insulating film;
A source electrode (13) connected to the source region;
A drain electrode (14) connected to the drain region,
The drain region is not configured to penetrate to the bottom of the gate electrode,
Further, the surface layer portion of the semiconductor layer includes a first conductivity type region (6) disposed between the drain region and the base region and disposed so as to surround the drain region,
The first conductivity type region is formed at a higher concentration than the semiconductor layer, and is configured to have a higher concentration as it approaches the drain region,
The semiconductor device according to claim 1, wherein the first conductivity type region has an impurity concentration of 5 × 10 ¹⁶ to 2 × 10 ¹⁷ cm ⁻³ in a portion of the first conductivity type region in contact with the drain region.   2. The semiconductor device according to claim 1, wherein a region having a lower concentration than the first conductivity type region exists between the first conductivity type region and the base region. 3. The semiconductor device according to claim 2, wherein an impurity concentration in a region having a concentration lower than that of the first conductivity type region is about 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻³ .   The second conductivity type region (9) is provided so as to be in contact with a lower portion of the source region, and the second conductivity type region is configured to have a higher concentration than the base region. 4. The semiconductor device according to any one of items 1 to 3.   The semiconductor device according to claim 4, wherein the second conductivity type region is disposed so as to avoid the channel region. The surface layer portion of the base region includes a second conductivity type contact region (9) disposed adjacent to the source region and connected to the source electrode together with the source region,
4. The semiconductor according to claim 1, wherein the contact region is formed at a higher concentration than the base region, and is configured to enter a lower part of the source region. 5. apparatus.   The semiconductor device according to claim 6, wherein the contact region is connected to the source electrode on a surface of the semiconductor layer opposite to the drain region across the source region. Forming a first conductivity type region (6) in a surface layer portion of the semiconductor layer of the substrate having the first conductivity type semiconductor layer (1);
Forming a LOCOS oxide film (4) partially opening on a part of the first conductivity type region and a part of the semiconductor layer on the semiconductor layer including the first conductivity type region; ,
Forming a gate insulating film (10) in a portion of the semiconductor layer where the LOCOS oxide film (4) is opened;
Forming a gate electrode (11) on the gate insulating film including the LOCOS oxide film;
Forming a second conductivity type base region (7) in a surface layer portion of the semiconductor layer using the gate electrode as a mask;
Forming a second conductivity type contact region (9) having a concentration higher than that of the base region in the base region;
A first conductivity type source region (8) is formed in the base region, and a first conductivity type drain region (5) having a higher concentration than the first conductivity type region is formed in the first conductivity type region. )
Forming an interlayer insulating film (12) on the substrate including the gate electrode; and
A source electrode (13) electrically connected to the source region and the contact region is formed through the interlayer insulating film, and a drain electrode (14) electrically connected to the drain region is formed. A process, and
The step of forming the first conductivity type region is performed by ion implantation of the first conductivity type impurity, and the dose amount of the first conductivity type impurity is 1 × 10 ¹⁴ cm ⁻² or less, and 2 × 10 ¹³ cm ^{−. A} method of manufacturing a semiconductor device, characterized in that it is set to ² or more   9. The method of manufacturing a semiconductor device according to claim 8, wherein the depth of the first conductivity type region is 2 to 4 [mu] m.   10. The method of manufacturing a semiconductor device according to claim 8, wherein the step of forming the first conductivity type region is performed before the step of forming the LOCOS oxide film.   The method for manufacturing a semiconductor device according to claim 8, wherein the step of forming the contact region is performed after the step of forming the base region. 12. The step of forming the contact region is performed by ion implantation of a second conductivity type impurity, and a dose amount of the second conductivity type impurity is set to 2 × 10 ¹⁵ cm ⁻² or more. The manufacturing method of the semiconductor device as described in any one of these.   13. The method of manufacturing a semiconductor device according to claim 12, wherein the step of forming the contact region is performed by high acceleration ion implantation.   13. The method of manufacturing a semiconductor device according to claim 8, wherein the depth of the contact region is 1 [mu] m or less.   When a CMOS is formed on the semiconductor layer of the substrate, a step of forming a first conductivity type well region disposed between adjacent cells of the CMOS and a step of forming the first conductivity type region are shared. The method of manufacturing a semiconductor device according to claim 8, wherein the method is a semiconductor device manufacturing method.   16. The semiconductor according to claim 8, wherein an SOI substrate in which the semiconductor layer is formed on a semiconductor substrate (2) via an insulating film (3) is used as the substrate. Device manufacturing method.

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