JP2003303960A - Vertical mos semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem wherein the on-resistance is large in the switching of an MOS transistor and power consumption becomes high, since parasitic junction FET resistance is high in the conventional vertical MOS transistor. <P>SOLUTION: In the MOS transistor 31, a gate electrode 48 is formed by a second trench 46. Then, a drain lead-out region is formed by a first trench 39 and a buried layer 38. Therefore, there are no parasitic junction FETs in an epitaxial layer 33 set to be the drain region of a lower region in a P- type diffusion region 44. As a result, parasitic resistance can be reduced, when the MOS transistor 31 is turned on, and the power consumption can be reduced. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has an object to reduce resistance at the time of switching in a vertical MOS semiconductor device and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, OA equipment is required to have low power consumption and high functionality. The vertical MOS transistor shown below as a conventional example is generally used as a motor driver IC for OA equipment such as a printer. And, it is researched and developed every day aiming at the above-mentioned development theme.

FIG. 11 shows a cross-sectional view of a conventional vertical N-channel MOS transistor 1.

As shown in the figure, an N-type epitaxial layer having a specific resistance of 0.1 to 3.5 Ω · cm and a thickness of 1.0 to 6.0 μm is formed on the P-type single crystal silicon substrate 2. 3 is formed. Then, the substrate 2 and the epitaxial layer 3 are N-doped by the P + type isolation region 4 penetrating them.
An island region 5 forming the channel type MOS transistor 1 is formed. Then, the substrate 2 and the epitaxial layer 3
An N + type buried layer 6 is formed between the and.

In the epitaxial layer 3, an N + type diffusion region 7 and a P− type diffusion region 8 are formed. The N + type diffusion region 7 is used as a drain extraction region, and an N ++ type diffusion region 9 is formed on the surface thereof. On the other hand, in the P− type diffusion region 8, an N + type diffusion region 10 and a P + type diffusion region 11 are formed. The N + type diffusion region 10 is used as a source region. The P + type diffusion region 11 has a function of making the P− type diffusion region 8 and the N + type diffusion region 10 have the same potential.

Then, the gate electrode 12, the insulating layer 13 and the like are formed on the surface of the epitaxial layer 3. Through the contact hole formed in the insulating layer 13, the drain electrode 1
6 and the source electrode 17 are formed, and N shown in FIG.
The channel type MOS transistor 1 is completed.

A conventional method of manufacturing the vertical N-channel MOS transistor 1 will be described with reference to FIGS.

First, as shown in FIG. 12, a P-type single crystal silicon substrate 2 is prepared, and on the substrate 2, for example, a specific resistance of 0.1 to 3.5 Ω · cm and a thickness of 1.0 to 6 are prepared. 0.0 μm N
A − type epitaxial layer 3 is formed. At this time, the N + type buried layer 6 and the first isolation region 18 of the P + type isolation region 4 are formed by the ion implantation method with the boundary surface between the substrate 2 and the epitaxial layer 3 interposed therebetween.

Next, as shown in FIG. 13, an N + type diffusion region 7 is formed in the epitaxial layer 3 by the ion implantation method, and the N + type diffusion region 7 and the N + type buried layer 6 are connected. Then, the LOCOS oxide film 20 is formed on the isolation region 4 of the epitaxial layer 3 and the like. After that, the gate electrode 12 is formed on the surface of the epitaxial layer 3 and the LOCOS oxide film 20 via the gate oxide film.

Next, as shown in FIG. 14, a P-type diffusion region 8 is formed in the epitaxial layer 3 through the gate electrode 12 by the ion implantation method. An N + type diffusion region 10 and a P + type diffusion region 11 are doubly diffused and formed on the surface of the diffusion region 8. At this time, the N ++ type diffusion region 9 is also formed on the surface of the N + type diffusion region 7.

Finally, the insulating layer 13, the drain electrode 16,
The source electrode 17 and the like are formed, and the vertical N-channel MOS transistor 1 shown in FIG. 11 is completed.

[0012]

As described above, in the conventional N-channel type MOS transistor 1, a voltage is applied to the gate electrode 12 and the P located below the gate electrode 12 is applied.
An N type channel is formed in the surface layer of the − type diffusion region 8 and driven. In the MOS transistor 1, the carrier is an electron, and the electron flows from the source region 12 to the N type channel region, the epitaxial layer 3, the N + type buried layer 6, the N + type diffusion region 7 and the N ++ type diffusion region 9. pass. That is, as shown in the figure, in the MOS transistor 1, the electrons move along the path shown by the dotted line, so that M
The OS transistor 1 operates.

However, as indicated by the dotted line, MO
In the S transistor 1, when electrons move, that is, when current flows from the drain electrode 16 to the source electrode 17,
Parasitic resistance occurs in the MOS transistor 1. The MOS transistor 1 is particularly affected by the parasitic junction FET resistance RJFET shown in the figure. Therefore, there is a problem that the parasitic resistance increases when the MOS transistor 1 is turned on.

Further, in the conventional N-channel MOS transistor 1, the N + type diffusion region 7 is used as the drain extraction region. Therefore, when diffusing the N + type diffusion region 7 from the surface of the epitaxial layer 3 to the N + type buried layer 6, the N + type diffusion region 7 also diffuses in the lateral direction. As a result, when forming the N + type diffusion region 7, it is necessary to consider the diffusion width in the lateral direction, and there is a problem that it is difficult to miniaturize the element size of the MOS transistor 1.

[0015]

The present invention has been made in view of the above-mentioned conventional problems, and is a vertical MO according to the present invention.
In the S semiconductor device, a semiconductor substrate of one conductivity type, an epitaxial layer of an opposite conductivity type laminated on at least the surface of the substrate, and a separation region of one conductivity type penetrating the epitaxial layer to form a plurality of island regions. A buried layer of opposite conductivity type formed between the substrate and the epitaxial layer in at least one of the island regions, a plurality of first trenches reaching the buried layer from the surface of the epitaxial layer, Reverse-conductivity-type polycrystalline silicon filled in the first trench to be a drain extraction region connected to the buried layer; a plurality of second trenches that do not reach the buried layer from the surface of the epitaxial layer; A gate oxide film covering the inner surface of the second trench and a gate oxide film formed by filling the second trench with polycrystalline silicon of an opposite conductivity type. Electrode, a diffusion region of one conductivity type which is a channel formation region provided on the side surface of the second trench, and a reverse conductivity which is a source region provided on the surface of the epitaxial layer adjacent to the second trench. Type diffusion region and the epitaxial layer which is located below the channel formation region and serves as a drain region. The drain region is led to the surface of the epitaxial layer at the drain extraction region through the buried layer. It is characterized by

In order to solve the above-mentioned problems, in the method of manufacturing a vertical MOS semiconductor device of the present invention, a semiconductor substrate of one conductivity type is prepared, impurities of opposite conductivity type are introduced into the surface of the substrate, and then, Depositing an epitaxial layer on a substrate, forming a buried layer so as to sandwich the boundary surface between the substrate and the epitaxial layer, and forming a first trench reaching the buried layer from the surface of the epitaxial layer, Filling the first trench with polycrystalline silicon doped with an impurity of opposite conductivity type; and forming a diffusion region of one conductivity type to be a channel formation region in the epitaxial layer, and then forming the diffusion region of one conductivity type. A step of forming a diffusion region of opposite conductivity type to be a source region so as to form a double diffusion structure, and a diffusion region of one conductivity type and a diffusion region from the surface of the epitaxial layer. Through the diffusion region of the opposite conductivity type,
A plurality of second trenches that do not reach the buried layer are formed, a gate oxide film that covers the inner surface of the second trenches is formed, and then polycrystalline silicon into which impurities of the opposite conductivity type are introduced is introduced into the second trenches. And a filling step.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a sectional view of a vertical N-channel MOS transistor 31.

As shown, on the P-type single crystal silicon substrate 32, for example, a specific resistance of 2.0 Ω · cm and a thickness of 3.
An N− type epitaxial layer 33 having a thickness of 0 to 7.0 μm is formed. An island region 35 is formed in the substrate 32 and the epitaxial layer 33 by a P + type isolation region 34 penetrating both. Although only the island region 35 is shown in the present embodiment, a plurality of other island regions are formed. For example, a plurality of vertical N-channel type MOS transistors, P-channel type MOS transistors, and NPN are similarly formed. Type transistor and the like are formed.

The isolation region 34 is composed of a first isolation region 36 which is vertically diffused from the surface of the substrate 32 and a second isolation region 37 which is diffused from the surface of the epitaxial layer 33. Then, the two are connected to separate the epitaxial layer 33 into a plurality of island regions. The structure of the vertical N-channel MOS transistor 31 according to the present invention will be described below.

As shown in the figure, an N + type buried layer 38 is formed between the substrate 32 and the epitaxial layer 33 so as to sandwich the boundary surface therebetween. In the N + type buried layer 38, the first layer formed from the surface of the epitaxial layer 33 is formed.
The trench 39 of has reached. In the present embodiment, the island region 35 shows a cross section divided into the first region 42 and the second region 43 by the first trench 39. Then, on the side surface in the first trench 39, a silicon oxide film 40 for the purpose of preventing diffusion of polysilicon to other regions.
Are covered. On the other hand, the silicon oxide film 40 on the bottom of the first trench 39 is removed. With this structure, the first trench 39 is filled with, for example, polycrystalline silicon (polysilicon) 41. Therefore, a structure in which the polysilicon 41 and the N + type buried layer 38 can be electrically connected to each other via the first trench 39 is realized. And, in this polysilicon 41,
A large amount of N-type impurities, for example, phosphorus (P) is introduced to form a high-concentration N-type region. This structure allows
As described above, the polycrystalline silicon 4 in the first trench 39 is
1 and the buried layer 38 form a drain extraction region of the MOS transistor 31 of the present invention.

In this embodiment, as described above, the epitaxial layer 33 on the buried layer 38 is formed in the first trench 39.
Is divided into a first area 42 and a second area 43. The regions 42 and 43 are the gate electrodes 4 respectively.
8, used as a formation region of a source region. Specifically, in the regions 42 and 43, P− type diffusion regions 44 to be channel forming regions are formed, respectively. In this diffusion region 44, an N + type diffusion region 45 to be a source region is formed by double diffusion. A plurality of second trenches 46 for forming the gate electrode 48 are formed at equal intervals from the surface of the epitaxial layer 33. The second trench 46 has the above-described P− type diffusion region 44 and N.
The N + type buried layer 38 is penetrated through the + type diffusion region 45.
It is formed with a depth that does not reach. The inside of the second trench 46 is different from the inside 39 of the first trench,
A substantially whole surface of the trench 46 is covered with a silicon oxide film 47. The second trench 46 is filled with, for example, polycrystalline silicon so as to cover the silicon oxide film 47. As in the case of the first trench 39, N-type impurities such as phosphorus (P) are introduced into the polycrystalline silicon. In this embodiment, this polycrystalline silicon is used as the gate electrode 48 and the silicon oxide film 47 is used as the gate oxide film.

An insulating layer 49 is formed on the surface of the epitaxial layer 33. A contact hole is formed in the insulating layer 49, and the drain electrode 50 and the source electrode 51 are formed of, for example, aluminum (Al) through the contact hole. At this time, the second
The gate electrode 48 in the trench 46 of the silicon oxide film 4 is
7 and the insulating layer 49 are insulated from the source electrode 51. As shown in the figure, a plurality of second trenches 46 are formed in the N + type diffusion region 45.
The source electrode 51 is formed of, for example, aluminum (Al) so as to cover the. That is, each area 42,
For each 43, one source electrode 51 is formed so as to collectively cover the plurality of gate electrodes 48. With this structure, the MOS transistor 31 as shown is completed.

Next, the operation of the MOS transistor 31 will be described.

As described above, in the MOS transistor 31 of the present invention, the high-concentration N type polysilicon 41 and the N + type buried layer 38 in the first trench 39 are used as the drain extraction region. The epitaxial layer 33 located below the P− type diffusion region 44 is used as a drain region, the P− type diffusion region 44 is used as a channel forming region, and the N + type diffusion region 45 is used as a source region. On the other hand, the drain electrode 50 contacts the polysilicon 41 in the first trench 39 from the surface opposite to the substrate 32, that is, from the element surface. Then, the polysilicon in the second trench 46 is used as the gate electrode 48. In addition, this gate electrode 48
And the source electrode 5 so as to cover the N + type diffusion region 45.
1 is in contact.

Then, a certain voltage is applied to the gate electrode 48 while the voltage is applied to the drain electrode 50 and the source electrode 51 so that the drain electrode 50 has a higher potential. As a result, electrons move to the MOS transistor 31 as shown by the dotted line in FIG.
That is, the current flows from the drain electrode 50 to the source electrode 51. At this time, as shown in the figure, the parasitic resistance is mainly R1 in the source region, R2 in the channel region, R3 in the drain region, and R4, R in the drain extraction region.
5 occurs. The sum of these resistances greatly affects the ON resistance of the MOS transistor 31 during switching.

That is, the MOS transistor 31 of the present invention
Then, a plurality of second trenches 46 are formed in the first and second regions 42 and 43 partitioned by the first trench 39, respectively. The gate electrode 48 is formed by depositing impurity-doped polysilicon in the second trench 46. That is, in the conventional MOS transistor 1 (see FIG. 11), the parasitic junction FET resistance RJFET (see FIG. 11) including the channel region and the epitaxial region is formed.
Therefore, when switching the MOS transistor 1, O
There is a problem that the N resistance is high and the power consumption is high. However, in the present invention, the parasitic junction FET is formed by forming the gate electrode 48 using the second trench 46.
The resistance can be eliminated. As a result, the ON resistance at the time of switching the MOS transistor 31 can be significantly improved, and at the same time, the power consumption of the MOS transistor 31 can be significantly improved.

Then, the MOS transistor 31 of the present invention
Then, the drain extraction region is formed by the first trench 39 together with the structure of the gate electrode 48 described above.
The drain electrode 50 is characterized in that the drain electrode 50 is brought into contact with the high-concentration N-type polysilicon 41 which is the drain extraction region from the device surface. Although only the island region 35 is described in the present embodiment, the MOS transistors 31 are similarly formed in the other plurality of island regions. That is, the drain electrode 50 is formed on the surface of the epitaxial layer 33 for each island region. Although not shown, in the present invention, by forming the drain electrodes 50 on the element surface, each drain electrode 50 can be connected to any wiring, and different voltages can be applied depending on the application. . As a result, various operations can be controlled with one chip, and it becomes possible to achieve multiple functions.

Further, in the MOS transistor 31 of the present invention, the high-concentration N-type polysilicon 41 in the first trench 39 and the N + -type buried layer 38 form a drain extraction region. Then, the first trench 39 having the silicon oxide film 40 formed on the side wall is used, and the high-concentration N-type polysilicon 41 serves as a drain extraction region. As a result, it is possible to suppress thermal diffusion of polysilicon and impurities laterally from the first trench 39 region. That is, according to the present invention, the width of the drain extraction region can be narrowed, so that the device size can be reduced. As a result, in the present invention, the diffusion region 7 in the conventional
(Refer to FIG. 11) The MOS transistor 3 is not deteriorated in terms of parasitic resistance as compared with the drain extraction region using the MOS transistor 3
It is possible to miniaturize one size.

Further, the MOS transistor 31 of the present invention is characterized in that the gate electrode 48 is formed using the second trench 46. That is, the gate electrode 12 (see FIG. 11) of the conventional MOS transistor 1 is formed on the surface of the epitaxial layer 3. Therefore, a region for forming the gate electrode 12 is required, which makes it difficult to miniaturize the device. However, in the present invention, the gate electrode 48 is formed in the epitaxial layer 33 by utilizing the second trench 46.
By forming the, it is possible to realize a great miniaturization of the device.

Although the first region 42 and the second region 43 have been described in the present embodiment, these regions can be formed in an arbitrary pattern according to the intended use.
Similar effects can be obtained. Besides, various modifications can be made without departing from the scope of the present invention.

Next, with reference to FIGS. 2 to 10, a method of manufacturing a vertical N-channel MOS transistor according to an embodiment of the present invention will be described below. In the following description, the same components as the components described in the structure of the MOS transistor shown in FIG. 1 are designated by the same reference numerals.

First, as shown in FIG. 2, a P-type single crystal silicon substrate 32 is prepared, and the surface of the substrate 32 is thermally oxidized to form a silicon oxide film on the entire surface, for example, 0.03 to 0.
It is formed to about 05 μm. After that, a photoresist having an opening in a portion where the buried layer 38 is to be formed is formed as a selection mask by a known photolithography technique. After that, an N-type impurity, for example, phosphorus (P) is introduced at an acceleration voltage of 20 to 65 keV and an introduction amount of 1.0 × 10 ^{13 to} 1.0 ×.
Ion implantation is performed at 10 ¹⁵ / cm ² and diffusion is performed.

Next, as shown in FIG. 3, an opening is formed on the silicon oxide film formed in FIG. 2 at a portion of the isolation region 34 where the first isolation region 36 is to be formed by a known photolithography technique. A photoresist is formed as a selective mask. Then, a P-type impurity, such as boron (B), is accelerated at an acceleration voltage of 60 to 100 keV, and the introduction amount is 1.0 ×
Ion implantation is performed at 10 ^{13 to} 1.0 × 10 ¹⁵ / cm ² and diffusion is performed. Then, the photoresist is removed. At this time,
The buried layer 38 is simultaneously diffused.

Next, as shown in FIG. 4, the silicon oxide film formed in FIG. 2 is completely removed, and the substrate 32 is placed on the susceptor of the epitaxial growth apparatus. Then, the substrate 32 is heated to a high temperature of, for example, about 1000 ° C. by heating the lamp, and SiH ₂ Cl ₂ gas and H ₂ are introduced into the reaction tube.
Introduce gas. Thereby, on the substrate 32, for example, a specific resistance of 2.0 Ω · cm or more and a thickness of 3.0 to 7.0 μm.
The epitaxial layer 33 of about m is grown. afterwards,
The surface of the epitaxial layer 33 is thermally oxidized to form a silicon oxide film, for example, about 0.03 to 0.05 μm.
After that, a photoresist having an opening in a portion of the isolation region 34 where the second isolation region 37 is to be formed is formed as a selection mask by a known photolithography technique.
Then, a P-type impurity, for example, boron (B) is accelerated at a voltage of 60 to 100 keV, and the introduction amount is 1.0 × 10 ^{13 to} 1.0 ×.
Ion implantation is performed at 10 ¹⁵ / cm ² and diffusion is performed. Then, the photoresist is removed.

Next, as shown in FIG. 5, a first trench 39 is formed in the epitaxial layer 33. In the cross section of the present embodiment, three first trenches 39 that divide the island region 35 into a first region 42 and a second region 43 are formed. First, a silicon nitride film (not shown) is deposited on the entire surface of the epitaxial layer 33. Then, the silicon nitride film is selectively removed by a known photolithography technique so that an opening is provided in a portion where the first trench 39 is formed. Then, for example, by dry etching, the first trench 39 reaching at least the N + type buried layer 38 is formed. Then, the surface of the epitaxial layer 33 is thermally oxidized to form the silicon oxide film 40 including the inside of the first trench 39. At this stage, the silicon oxide film 40 is also deposited on the bottom surface of the first trench 39.

Next, as shown in FIG. 6, the first trench 3 is formed.
The inside of 9 is filled with, for example, polysilicon introduced with N-type impurities. First, using the silicon nitride film used in FIG. 5 as a mask, the silicon oxide film 40 on the bottom surface of the first trench 39 is removed by dry etching. And
After removing the silicon nitride film, for example, polysilicon (polycrystalline silicon) 41 is deposited in the first trench 39. In this step, an N-type impurity such as phosphorus (P) is introduced at the same time when the polysilicon 41 is introduced into the first trench 39. The impurity concentration in the polysilicon 41 is 1.0 × 10 ^{18 to} 1.0 × 10.
^A large amount of impurities is introduced so that the amount becomes ²⁰ / cm ³ . Then, a uniform concentration distribution is obtained by using the heat diffusion process as a post process.

The manufacturing method of the present invention is characterized in that polysilicon 41 is deposited on the sidewall of the first trench 39 with the silicon oxide film 40 formed. In the conventional structure, the N + diffusion region 7 (see FIG. 11) was used. However, in this manufacturing method, it is difficult to miniaturize the device because diffusion in the lateral direction is also taken into consideration. However, in the present invention, the polysilicon 41 is deposited using the first trench 39 and with the silicon oxide film 40 formed on the side wall in the first trench 39. As a result, the lateral diffusion of the polysilicon 41 and the impurities in the polysilicon 41 can be suppressed. As a result, the manufacturing method can realize the miniaturization of the element without deteriorating in terms of the parasitic resistance in the polysilicon 41 which becomes the drain extraction region.

Next, as shown in FIG. 7, P-type diffusion regions 44 are formed in each of the first region 42 and the second region 43. First, the surfaces of the epitaxial layer 33 and the polysilicon 41 are thermally oxidized to form a silicon oxide film, for example,
The thickness is about 0.03 to 0.05 μm. After that, by a known photolithography technique, a photoresist having an opening in a portion where the P− type diffusion region 44 is formed is formed as a selection mask. Then, a P-type impurity such as boron (B) is ion-implanted at an acceleration voltage of 60 to 100 keV and an introduction amount of 1.0 × 10 ^{13 to} 1.0 × 10 ¹⁵ / cm ² , and diffused. Then, the photoresist is removed.

Next, as shown in FIG. 8, a photoresist having an opening in the portion where the N + type diffusion region 45 is to be formed is formed by a known photolithography technique as a selective mask. Then, an N-type impurity, for example, phosphorus (P) is added at an acceleration voltage of 20 to 65 keV and an introduction amount of 1.0 × 1
Ions are implanted at 0 ^{13 to} 1.0 × 10 ¹⁵ / cm ² and diffused. Then, the photoresist is removed. By this step, the P− type diffusion region 44 is also diffused, and a double diffusion structure of the P− type diffusion region 44 and the N + type diffusion region 45 is formed.

Next, as shown in FIG. 9, a second trench 46 is formed in each of the first region 42 and the second region 43. In the present embodiment, the P− type diffusion region 44 and the N +
Both of the N type diffusion regions 45 are penetrated and formed in the N + type diffusion regions 45 at equal intervals. First, for example, a silicon nitride film is selectively formed on the surface of the epitaxial layer 33 except for the region where the second trench 46 is formed. Then, for example, the second trench 4 is formed by dry etching.
6 is formed. After that, the surface of the epitaxial layer 33 is thermally oxidized to include the silicon oxide film 4 including the inside of the second trench 46.
Form 7. Then, after removing the silicon nitride film,
Polysilicon, for example, is deposited in the second trench 46. By this step, the inside of the second trench 46 is filled with polysilicon. Note that N-type impurities, for example, phosphorus (P), are introduced into the polysilicon in the second trench 46 as well as the polysilicon 41 in the first trench 39 at the time of deposition.

In the MOS transistor of the present invention, the polysilicon in the second trench 46 is used as the gate electrode 48, and the silicon oxide film 47 in the second trench 46 is used as the gate oxide film. On the other hand, the N + type diffusion region 45 is used as a source region, and the P− type diffusion region 44 is used as a channel formation region.

Next, as shown in FIG. 10, a BPSG (Boron Phospho) is formed as an insulating layer 49 on the entire surface of the silicon oxide film 47 formed in FIG. 9, for example.
Silicate Glass) film, SOG (Spin)
An On Glass) film or the like is deposited. After that, a contact hole for forming an external electrode is formed by a known photolithography technique. At this time, the second trench 46
The gate electrode 48 formed therein is completely covered with the silicon oxide film 47 and the insulating layer 49.

Finally, through the contact hole formed in the insulating layer 49, the drain electrode 5 made of, for example, Al
0 and the source electrode 51 are formed, and the vertical N-channel MOS transistor 31 shown in FIG. 1 is completed. still,
In the present embodiment, a plurality of gate electrodes 48 are formed in each of the first region 42 and the second region 43. Then, one source electrode 51 is formed for the plurality of gate electrodes 48 so as to cover the N + type diffusion region 45.

In the above-described embodiment, the vertical type N
Although the case where only the channel-type MOS transistor is formed has been described, a plurality of vertical N-channel-type MOS transistors, NPN transistors and the like are also formed simultaneously in the other island regions. Further, the same manufacturing method can be applied to a discrete vertical N-channel MOS transistor. Besides, various modifications can be made without departing from the scope of the present invention.

[0046]

According to the present invention, firstly, in the vertical MOS semiconductor device, the second trench is formed from the surface of the epitaxial layer, and the gate electrode is formed in the epitaxial layer. The drain extraction region is also characterized in that the drain electrode is formed on the device surface using the first trench. As a result, in the vertical MOS semiconductor device of the present invention, the parasitic junction FET resistance can be eliminated, and the ON resistance at the time of switching of the vertical MOS semiconductor device can be greatly improved. As a result, the power consumption of the vertical MOS semiconductor device can be significantly improved. Then, by forming the drain electrode on the device surface, a plurality of vertical MOSs formed in one chip are formed.
The structure makes it possible to apply different voltages to the drain electrode of the semiconductor device depending on the application. As a result, it is possible to realize multi-functionalization that can be used for various purposes with one chip.

Secondly, the vertical MOS semiconductor device of the present invention is characterized in that the gate electrode is formed in the epitaxial layer by using the second trench. In other words, it is possible to realize a large reduction in device size as compared with the conventional vertical MOS semiconductor device in which the gate electrode is formed on the surface of the epitaxial layer.

Thirdly, the method of manufacturing a vertical MOS semiconductor device of the present invention is characterized in that the first trench and the second trench are formed in separate steps. As a result, the depths of the first trench and the second trench can be formed to desired depths. As a result, the drain extraction region can be formed by the high-concentration N-type polysilicon and the N-type buried layer in the first trench.

Fourth, the method of manufacturing a vertical MOS semiconductor device of the present invention is characterized in that a silicon oxide film is formed on the side wall in the first trench. That is, the feature is that after the silicon oxide film is formed in the first trench, the silicon oxide film on the bottom surface of the first trench is removed. As a result, when polysilicon is formed in the first trench,
It is possible to suppress lateral diffusion of polysilicon. As a result, miniaturization of the vertical MOS semiconductor device can be realized.

[Brief description of drawings]

FIG. 1 is a cross-sectional view illustrating a vertical MOS semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view illustrating a method of manufacturing a vertical MOS semiconductor device according to the present invention.

FIG. 3 is a cross-sectional view illustrating the method of manufacturing the vertical MOS semiconductor device according to the present invention.

FIG. 4 is a cross-sectional view illustrating a method of manufacturing a vertical MOS semiconductor device according to the present invention.

FIG. 5 is a cross-sectional view illustrating a method of manufacturing a vertical MOS semiconductor device according to the present invention.

FIG. 6 is a cross-sectional view illustrating a method of manufacturing a vertical MOS semiconductor device according to the present invention.

FIG. 7 is a cross-sectional view illustrating a method of manufacturing a vertical MOS semiconductor device according to the present invention.

FIG. 8 is a sectional view illustrating a method of manufacturing a vertical MOS semiconductor device according to the present invention.

FIG. 9 is a cross-sectional view illustrating a method of manufacturing a vertical MOS semiconductor device according to the present invention.

FIG. 10 is a cross-sectional view illustrating a method of manufacturing a vertical MOS semiconductor device according to the present invention.

FIG. 11 is a cross-sectional view illustrating a conventional vertical MOS semiconductor device.

FIG. 12 is a cross-sectional view illustrating a conventional method of manufacturing a vertical MOS semiconductor device.

FIG. 13 is a cross-sectional view illustrating a conventional method of manufacturing a vertical MOS semiconductor device.

FIG. 14 is a cross-sectional view illustrating a conventional method of manufacturing a vertical MOS semiconductor device.

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Claims (14)

[Claims] 1. A semiconductor substrate of one conductivity type, a reverse conductivity type epitaxial layer laminated on at least the surface of the substrate, and a reverse conductivity type buried layer formed between the substrate and the epitaxial layer. A first trench reaching from the surface of the epitaxial layer to the buried layer; a polysilicon of a reverse conductivity type filled in the first trench, which is a drain extraction region connected to the buried layer; and the epitaxial layer A plurality of second trenches that do not reach the buried layer from the surface, a gate oxide film that covers the inner surface of the second trench, and the second trench are filled with reverse conductivity type polycrystalline silicon. Adjacent to the second trench, a gate electrode, a diffusion region of one conductivity type serving as a channel formation region provided on a side surface of the second trench, and the second trench. A diffusion region of the opposite conductivity type, which is provided on the surface of the epitaxial layer and serves as a source region, and the epitaxial layer, which is located below the channel formation region and serves as a drain region. A vertical MOS semiconductor device, characterized in that it is led out to the surface of the epitaxial layer in the drain take-out region through. 2. The vertical MOS according to claim 1, wherein an interlayer insulating layer is formed on a surface of the second trench, and a source electrode is formed so as to cover the interlayer insulating layer. Semiconductor device. 3. The vertical MOS semiconductor device according to claim 1, wherein a silicon oxide film is formed on a sidewall of the first trench. 4. An interlayer insulating layer is formed on the surface of the drain extraction region, and the drain electrode is in contact through a contact hole formed in the interlayer insulating layer. The vertical MOS semiconductor device according to claim 3. 5. The vertical MOS semiconductor device according to claim 1, wherein the channel region and the source region have a double diffusion structure. 6. A semiconductor substrate of one conductivity type, an epitaxial layer of the opposite conductivity type laminated on at least the surface of the substrate, and a separation region of one conductivity type penetrating the epitaxial layer to form a plurality of island regions. A buried layer of opposite conductivity type formed between the substrate and the epitaxial layer in at least one of the island regions, a plurality of first trenches reaching the buried layer from the surface of the epitaxial layer, Reverse-conductivity-type polycrystalline silicon filled in the first trench to be a drain extraction region connected to the buried layer; a plurality of second trenches that do not reach the buried layer from the surface of the epitaxial layer; A gate oxide film covering the inner surface of the second trench and a gate electrode formed by filling the second trench with polycrystalline silicon of an opposite conductivity type. A pole, a diffusion region of one conductivity type that is a channel formation region provided on the side surface of the second trench, and an opposite conductivity type that is a source region provided on the surface of the epitaxial layer adjacent to the second trench. A diffusion region and an epitaxial layer that is located below the channel formation region and serves as a drain region, and lead the drain region to the surface of the epitaxial layer at the drain extraction region through the buried layer. A vertical MOS semiconductor device characterized by: 7. The vertical MOS according to claim 6, wherein an interlayer insulating layer is formed on a surface of the second trench, and a source electrode is formed so as to cover the interlayer insulating layer. Semiconductor device. 8. The vertical MOS semiconductor device according to claim 6 or 7, wherein a silicon oxide film is formed on a sidewall of the first trench. 9. The drain electrode is in contact with the surface of the drain extraction region through a contact hole provided in an interlayer insulating layer, and a different voltage is applied to the drain electrode for each of the island regions. The vertical MOS semiconductor device according to any one of claims 6 to 8. 10. The vertical MOS semiconductor device according to claim 6, wherein the channel region and the source region have a double diffusion structure. 11. A semiconductor substrate of one conductivity type is prepared, impurities of the opposite conductivity type are introduced into the surface of the substrate, and an epitaxial layer is deposited on the substrate to form a boundary surface between the substrate and the epitaxial layer. Forming a buried layer so as to sandwich it, and forming a first trench reaching the buried layer from the surface of the epitaxial layer, and filling the first trench with polycrystalline silicon into which an impurity of opposite conductivity type is introduced. And a step of forming a diffusion region of one conductivity type that becomes a channel formation region in the epitaxial layer, and then forming a diffusion region with the diffusion region of one conductivity type and a diffusion region of opposite conductivity type that becomes a source region. And a step of forming a plurality of first conductive type diffusion regions and reverse conductivity type diffusion regions from the surface of the epitaxial layer, and not reaching the buried layer. Forming a second trench, forming a gate oxide film covering the inner surface of the second trench, and then filling the second trench with polycrystalline silicon into which an impurity of an opposite conductivity type has been introduced. A method of manufacturing a vertical MOS semiconductor device having the characteristics. 12. The polycrystalline silicon in the first trench is formed by covering substantially the entire surface of the first trench with a silicon oxide film and then opening at least a part of the silicon oxide film on the bottom surface of the first trench. The method of manufacturing a vertical MOS semiconductor device according to claim 11, wherein silicon and the buried layer are connected to form a drain extraction region. 13. The method for manufacturing a vertical MOS semiconductor device according to claim 11, wherein an interlayer insulating layer is formed on the surface of the second trench, and the source electrode is formed by covering the interlayer insulating layer. . 14. The interlayer insulating layer is formed on the surface of the polycrystalline silicon in the first trench, and the drain electrode is formed through a contact hole formed in the interlayer insulating layer. A method for manufacturing the vertical MOS semiconductor device described.