JP2002314066A - Mos semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device wherein high integration by fining an IC, ability improvement, lower consumption power or the like are required in a power MOS transistor, and to provide its manufac turing method. SOLUTION: In a power MOS transistor 31, a drain lead-out region 49 is formed in a surface of a drain region 41 fitting to the width of a contact hole 48. The drain region 41 is formed deep below a gate 40. As a result, it is possible to prevent contact between a P-type channel and the drain lead-out region 49, formation of a P-type channel by inversion of an epitaxial layer 35 below the gate 40 and the like on turning the power MOS transistor 31 off and to realize high integration, ability improvement, low consumption power or the like.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor in which a drain electrode region is formed of two layers of diffusion regions made of the same impurity having different impurity concentrations to improve the size and performance of the MOS transistor. The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, portable devices such as MDs and CDs have
There is a demand for higher integration, higher performance, lower power consumption, and the like due to miniaturization of C. A power MOS transistor shown below as a conventional example is generally used in mobile devices, for example, M
It is used as a battery-driven motor driver IC for D and CD. And they are researched and developed every day with the aim of the above development theme.

FIG. 12 is a cross-sectional view of an N-channel power MOS transistor 1 in a conventional Bi-CMOS process.

On a P- type single crystal silicon substrate 2, for example, a specific resistance of 0.1 to 3.5 Ω · cm and a thickness of 1.0 to
An epitaxial layer 5 of 6.0 μm is formed. An N channel M is formed in the substrate 2 and the epitaxial layer 5 by a P + type isolation region 6 completely penetrating both.
An island region forming the OS transistor 1 is formed.

The isolation region 6 is composed of a first isolation region 4 vertically diffused from the surface of the substrate 2 and a second isolation region 7 diffused from the surface of the epitaxial layer 5. Separate layer 5 into islands. Further, since the LOCOS oxide film 8 is formed on the P + type isolation region 6, isolation between elements is further achieved.

In the epitaxial layer 5, a P + type diffusion region 9, a P + type well region 12, an N ++ type drain region 11, and an N + type diffusion region 24 are formed so as to overlap the drain region 11. I have. In the P + type well region 12, an N ++ type source region 15, an N + type diffusion region 13 overlapping with the source region 15, and a P + type
A P ++ type diffusion region 17 is formed so as to overlap with the type diffusion region 9 and the P + type well region 12. With this structure, an N-channel power MOS transistor 1 is formed.

Here, the feature of the N + type diffusion region 13 is that it is formed between the N type channel and the N ++ type source region 15 so that a concentration gradient is formed with respect to the N ++ type source region 15. can do. As a result, the N-channel power MOS transistor 1
At the time of F, a depletion layer forming region when a reverse bias is applied to the N-channel power MOS transistor 1 is secured.
Further, by being formed so as to overlap with the N ++ type source region 15, the electric field concentrated at the end of the N ++ type source region 15 is reduced, and the hot carrier effect can be suppressed. ing.

A feature of the P ++ type diffusion region 17 is that, when a reverse current flows through the N-channel type power MOS transistor 1, the P ++ type diffusion region 17, P +
A PN bond is formed between the P-type region of the N-type well region 12 and the P + -type diffusion region 9 and the N + -type buried layer 3. As a result, a reverse current is applied to the substrate 2
To ground via N-channel power MOS
The structure protects the transistor 1.

Next, a manufacturing process of the power MOS transistor 1 in the Bi-CMOS process shown in FIG. 1 by a conventional manufacturing method will be described below with reference to FIGS.

First, as shown in FIG. 13, a P- type single-crystal silicon substrate 2 is prepared, the surface of the substrate 2 is thermally oxidized to form an oxide film, and an oxide film corresponding to the buried layer 3 is formed. Photo-etched to make a selective mask. And the substrate 2
Arsenic (As) forming the N + type buried layer 3 on the surface is diffused.

Next, as shown in FIG. 14, ion implantation of the first P + type buried layer 4 for forming the P + type isolation region 6 is performed. In FIG. 13, after removing all the oxide film used as the selection mask, the surface of the substrate 2 is thermally oxidized to form a silicon oxide film of, for example, about 0.01 to 0.20 μm, and P + is formed by a known photolithography technique. A photoresist having an opening at a portion where the mold burying layer 4 is to be formed is formed as a selection mask. Then, a P-type impurity, for example, boron (B) is ion-energy 10
0 to 200 keV, introduction amount 1.0 × 10 ^{13 to} 1.0 × 1
Ion implantation is performed at 0 ¹⁵ / cm ² . After that, the photoresist is removed.

Next, as shown in FIG. 15, after removing all the oxide film, the substrate 2 is placed on a susceptor of an epitaxial growth apparatus,
A high temperature of about 1000 ° C. is applied and SiH
By introducing ₂ Cl ₂ gas and H ₂ gas, an epitaxial layer 5 having a specific resistance of 0.1 to 3.5 Ω · cm and a thickness of about 1.0 to 6.0 μm is grown. Then, the surface of the epitaxial layer 5 is thermally oxidized to form a silicon oxide film of, for example, about 0.1 to 0.6 μm, and then the oxide film corresponding to the second P + type buried layer 7 is photo-etched. The selection mask is used. Then, a P-type impurity, for example, boron (B) is ion-implanted and diffused at an ion energy of 20 to 60 keV and an introduction amount of 3.0 × 10 ^{12 to} 3.0 × 10 ¹⁴ / cm ² . After that, the oxide film used as the mask is removed. At this time, the N + type buried layer 3 and the P + type buried layer 4 are simultaneously diffused.

Then, for example, a heat treatment is applied to the entire substrate 2 while forming an oxide film by steam oxidation at about 800 to 1200 ° C., and a LOCOS oxide film 8 is formed on the P + type isolation region 6. More element isolation is achieved. Here, the LOCOS oxide film 8 has, for example, a thickness of 0.1 mm.
It is formed to a thickness of about 5 to 1.0 μm. Next, a gate silicon oxide film, for example, having a thickness of 0.01 to 0.
The gate 10 is formed to a thickness of about 20 μm, polysilicon is formed on the oxide film, phosphorus (P) is diffused, and the polysilicon is etched. Then, gate 10
To form a gate oxide film. At this time, the P + type buried layers 4 and 7 are simultaneously diffused, and the P + type isolation regions 6 are connected.

Next, as shown in FIG. 16, a photoresist having an opening at a portion where a P + type diffusion region 9 is to be formed is formed on the silicon oxide film formed in FIG. 15 by a known photolithography technique. It is formed as a selection mask. Then, a P-type impurity, for example, boron (B) is ion energy of 20 to 65 keV, and the introduced amount is 1.0 × 1.
Ion implantation is performed at a rate of 0 ^{13 to} 1.0 × 10 ¹⁵ / cm ² . After that, the photoresist is removed.

Next, as shown in FIG. 17, a photoresist having an opening at a portion where a P + type well region 12 is formed is formed on the silicon oxide film formed in FIG. 15 by a known photolithography technique. It is formed as a selection mask. Then, a P-type impurity, for example, boron (B) is ion-implanted at an ion energy of 20 to 65 keV and an introduction amount of 1.0 × 10 ^{15 to} 1.0 × 10 ¹⁷ / cm ² . At this time, in the step of implanting boron (B) into the P + type well region 12, the position of the P + type well region 12 can be more accurately ionized by using the gate 10 in addition to the photoresist as a selective mask. An injection can be made. After that, the photoresist is removed.

Next, as shown in FIG. 18, on the silicon oxide film formed in FIG. 15, a photolithography technique is used in which openings are formed at portions where N + type diffusion regions 13 and 24 are formed by a known photolithography technique. A resist is formed as a selection mask. Then, an N-type impurity, for example, arsenic (As) is ion-implanted at an ion energy of 60 to 120 keV and a dose of 1.0 × 10 ^{15 to} 1.0 × 10 ¹⁷ / cm ² . At this time, as in the case of FIG. 17, in the step of ion-implanting arsenic (As) into the N + type diffusion regions 13 and 24, a selective mask is used to form the gate 10 in addition to the photoresist.
By using the LOCOS oxide film 8 and the LOCOS oxide film 8, the position of the N + type diffusion regions 13 and 24 can be more accurately ion-implanted. After that, the photoresist is removed. At this time, the P + type well region 12 is simultaneously diffused.

Next, as shown in FIG.
A sidewall is formed on the side surface of the gate 10 by using the D method. Then, on the surface of the N + type diffusion regions 13 and 24,
On the silicon oxide film formed in FIG. 15, an N ++ type drain region 1 is formed by a known photolithography technique.
A photoresist having an opening at a portion where the 1 and N ++ type source regions 15 are formed is formed as a selection mask. Then, an N-type impurity, for example, arsenic (As) is ion energy of 70 to 120 keV, and the amount of introduction is 1.0 ×
Ion implantation is performed at 10 ^{15 to} 1.0 × 10 ¹⁷ / cm ² . At this time, as in the case of FIG. 17, arsenic (As) is added to the N ++ type drain region 11 and the N ++ type source region 15.
In the step of ion-implanting, the position of the N ++ type drain region 11 and the N ++ type source region 15 can be more accurately ion-implanted by using the gate 10 and the LOCOS oxide film 8 in addition to the photoresist as a selection mask. It can be carried out. After that, the photoresist is removed. At this time, the N + type diffusion regions 13 and 24 are simultaneously diffused.

Next, as shown in FIG. 20, on the silicon oxide film and the gate 10 formed in FIG.
TEOS (Tetraethylorth) which is an insulating film
Oslicate) film 22 having a thickness of, for example, 0.01
About 0.2 μm, and then the silicon nitride film 23
Is formed, for example, in a thickness of about 0.01 to 0.2 μm.
Then, on the silicon nitride film 23, a BPSG (phosphor boron silicate glass) film 16, for example, having a thickness of 0.5 to
It is formed to a thickness of about 3.0 μm, and then SOG (Spin O
The surface is flattened by the (n Glass) film.

Thereafter, contact holes 18 and 19 are formed by etching. Then, a photoresist having an opening at a portion where the P ++ type diffusion region 17 is to be formed is formed as a selection mask by a known photolithography technique. Then, a P-type impurity, for example, boric boron (BF) is ion-implanted at an ion energy of 30 to 75 keV and an introduction amount of 1.0 × 10 ^{15 to} 1.0 × 10 ¹⁷ / cm ² . After that, the photoresist is removed. At this time, the N ++ type drain region 11 and source region 15
Are simultaneously diffused.

Thereafter, on the N ++ type drain region 11, the N ++ type source region 15, and the P ++ type diffusion region 17, an Al external electrode 20 is formed through contact holes 18 and 19 for electrical connection to the outside. , 21 are formed, and the power MOS transistor 1 in the Bi-CMOS process shown in FIG. 12 is completed.

[0021]

As described above, for example, in the conventional power MOS transistor 1 of the Bi-CMOS process, the drain region 11 is formed of an N ++ type high concentration impurity, and the periphery thereof is substantially the same. An N + type diffusion region 24 of the region was formed.

However, N +
Due to the structure in which the + type drain region 11 is formed,
When the power MOS transistor 1 is turned off, the following two problems occur.

The first problem is that when the power MOS transistor 1 is turned off, the source voltage or the drain voltage rises, so that the N− type epitaxial layer 5 is inverted, and the P− type channel layer is formed below the gate 10. It is formed. As a result, a leak current is generated at a portion where the P− type inverted channel layer and the N ++ type drain region 11 and the N + type diffusion region 24 are in contact, and the power M
There is a problem that the current leaks and the power consumption increases even when the OS transistor 1 is OFF.

The second problem is that when the power MOS transistor 1 is turned off, the source voltage or the drain voltage rises, so that the electric field between the drain region and the gate increases. However, since the N ++ type drain region 11 was formed adjacent to below the gate 10, the depletion layer could not be spread. For this reason, the generated electric field cannot be released, and a high electric field is applied to the silicon oxide film formed under the gate 10, which causes a problem in that the silicon oxide film undergoes characteristic fluctuation.

[0025]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems. In a MOS semiconductor device according to the present invention, a one-conductivity-type semiconductor substrate and a substrate laminated on the substrate surface are provided. A reverse conductivity type epitaxial layer, a one conductivity type isolation region penetrating the epitaxial layer to form an island region, and a LOCOS oxide film for isolating the island region formed on the isolation region from one element to another A MOS transistor of a reverse conductivity type channel formed in the island region; an insulating film formed on the LOCOS oxide film and the MOS transistor; and a contact hole formed in the insulating film. An external electrode; and a drain region of a reverse conductivity type of the MOS transistor, the first diffusion region having a higher impurity concentration and the contact hole having a higher impurity concentration. Wherein the width of the Le and the second diffusion region is substantially equal width is formed so as to overlap.

The MOS semiconductor device of the present invention is preferably
A structure in which one of the source region and the drain region is overlapped with a first diffusion region having a higher impurity concentration and a second diffusion region having a width substantially equal to the width of the contact hole having a higher impurity concentration. It is characterized by having. Thereby, the formation region of the second diffusion region having a high impurity concentration can be minimized, and it is possible to cope with the various problems described above.

In order to solve the above-mentioned problems, a method of manufacturing a MOS semiconductor device according to the present invention includes a step of preparing a semiconductor substrate of one conductivity type and a step of laminating an epitaxial layer of the opposite conductivity type on the substrate. Forming an island region by one conductivity type isolation region penetrating the epitaxial layer;
Forming a LOCOS oxide film on the isolation region;
In the island region, a reverse conductivity type first MOS transistor is a source region and a drain region of a MOS transistor having a reverse conductivity type.
Forming a diffusion region, and forming an insulating film on the epitaxial and LOCOS oxide films,
A contact hole is formed in the insulating film, and a reverse conductivity type drain region of the MOS transistor is ion-implanted with an impurity through the contact hole to form a second reverse conductivity type diffusion region in the first diffusion region. And a step of overlapping.

The method for manufacturing a MOS semiconductor device according to the present invention comprises:
Preferably, the step of forming the second diffusion region of the opposite conductivity type of the drain region of the opposite conductivity type of the MOS transistor is a step of ion-implanting an impurity through the contact hole. Has features. Thereby, the second reverse conductivity type diffusion region can be formed accurately in a portion where it is desired to be formed, so that an increase in the chip size of the MOS transistor can be prevented.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a sectional view of an N-channel type power MOS transistor 31 in a Bi-CMOS process.

On the P- type single crystal silicon substrate 32,
For example, specific resistance 0.1 to 3.5 Ω · cm, thickness 1.0 to
An epitaxial layer 35 of about 6.0 μm is formed. In the substrate 32 and the epitaxial layer 35, an island region for forming the N-channel MOS transistor 31 is formed by the P + type isolation region 36 completely penetrating both.

The isolation region 36 is composed of a first isolation region 34 diffused vertically from the surface of the substrate 32 and a second isolation region 37 diffused from the surface of the epitaxial layer 35. The layer 35 is separated into islands. On the P + type isolation region 36, the LO
By forming the COS oxide film 38, isolation between elements is further achieved.

Then, P +
A type diffusion region 39, a P + type well region 42, and an N− type drain region 41 are formed. The P + -type well region 42 has an N + + -type source region 45, an N + -type diffusion region 43 overlapping the source region 45, and a P + -type diffusion region 39 and a P + -type well region 42.
A ++ type diffusion region 47 is formed. On the surface of the N− type drain region 41, an N ++ type drain extraction region 49 is formed.

Here, the feature of the N + type diffusion region 43 is that it is formed between the N type channel and the N ++ type source region 45, so that a concentration gradient is formed with respect to the N ++ type source region 45. can do. As a result, the N-channel power MOS transistor 31
At the time of FF, N-channel type power MOS transistor 31
To secure a depletion layer forming region when a reverse bias is applied to the substrate. Further, the N ++ type source region 45 is formed so as to overlap with the N ++ type source region 45 so as to cover it.
The structure is such that the electric field concentrated at the end can be reduced and the hot carrier effect can be suppressed.

A feature of the P ++ type diffusion region 47 is that when a reverse current flows through the N-channel type power MOS transistor 31, the P ++ type diffusion region 47, P
The P-type region including the + -type well region 42 and the P + -type diffusion region 39 and the N + -type buried layer 33 form a PN bond. Thereby, the reverse current is grounded via the substrate 32, and the N-channel power MOS transistor 31 is protected.

Further, as a feature of the MOS semiconductor device of the present invention, an N ++ type drain extraction region 49 is formed on the surface of the N− type drain region 41 so as to be shallow in the depth direction in accordance with the width of the contact hole 48. That is being done. It is sufficient that the N ++ type drain extraction region 49 has a region enough to extract a current. As a result, the following effects can be obtained.

The first effect is that an N-channel type power MO
When the source voltage or the drain voltage rises when the S transistor 31 is turned off, the N − type epitaxial layer 35 is inverted, and this is seen when a P − type channel layer is formed below the gate 40. It is N ++
Type drain extraction region 49 is formed on the surface of the N − type drain region 41 with a minimum required space,
It has a structure in which the periphery of the N ++ type drain extraction region 49 overlaps the N− type drain region 41. Further, it has a structure in which the N − type drain region 41 is formed deep below the gate 40. This can prevent direct contact between the P− type inverted channel layer and the N ++ type drain lead region 49. Further, the P-type inversion forming region can be reduced. As a result, when the N ++ type drain lead region 49 comes into contact with the P− type inverted channel layer, the leakage current generated at that portion is greatly suppressed, and the N channel type power MOS transistor 31
The power consumption at the time of turning off can be greatly reduced.

The second effect is seen when the source voltage or the drain voltage rises when the power MOS transistor 31 is turned off, thereby increasing the electric field between the drain region and the gate. That is, the N ++ type drain extraction region 49 is formed in the minimum required space on the surface of the N− type drain region 41, and the N− type drain extraction region 49 is formed around the N ++ type drain extraction region 49.
It has a structure surrounded by. As a result, an N ++ type drain extraction region 49 is provided below and around the gate 40.
Since the N− type drain region 41 having a lower impurity concentration is formed deeper, a depletion layer forming region can be secured. As a result, an electric field generated by an increase in the source voltage or the drain voltage can be countered by forming a depletion layer. Then, the influence of the high electric field on the silicon oxide film formed below the gate 40 can be greatly reduced, and the effect of greatly reducing the characteristic fluctuation of the silicon oxide film can be obtained.

Here, specifically, in the first effect, a leak current was observed when the source or drain voltage was 7 V in the prior art. However, in the present invention, this source or drain voltage is reduced to 10 to 30 V. Can be improved. On the other hand, in the second effect, in the related art, when the drain-gate voltage is 20 V, a characteristic change is observed in the silicon oxide film formed under the gate. Can be improved to 25-45V.

In the first and second effects, the formation region of the N− type drain region 41
Each one can be further improved. But,
If one characteristic is significantly improved, the other characteristic will be degraded. Therefore, the formation region of the N− type drain region 41 is determined in consideration of the balance between the two characteristics.

The power MOS transistor 31 has contact holes 48, 5 and 5 for electrical connection to the outside.
The electrodes 50 and 52 are formed with the first electrode 1 interposed therebetween.

Next, the manufacturing process of the power MOS transistor 1 in the Bi-CMOS process shown in FIG. 1 will be described with reference to FIGS.
This will be described below with reference to FIG.

First, as shown in FIG. 2, a P-type single-crystal silicon substrate 32 is prepared, and the surface of the substrate 32 is thermally oxidized to form an oxide film, and an oxide film corresponding to the buried layer 33 is formed. Photo-etched to make a selective mask. Then, arsenic (A) forming an N + type buried layer 33 on the surface of the substrate 32 is formed.
s).

Next, as shown in FIG.
Of the first P + type buried layer 34 for forming the region 36
Perform ion implantation. Used as a selection mask in FIG.
After removing all the oxide film, the surface of the substrate 32 is thermally oxidized.
To a silicon oxide film of, for example, 0.01 to 0.20 μm
Formed to a degree of P + by a known photolithography technique.
An opening is provided in a portion where the mold buried layer 34 is formed.
A photoresist is formed as a selection mask. And
P-type impurities such as boron (B) are ion energy
100-200 keV, introduction amount 1.0 × 10¹³~ 1.0
× 10¹⁵/ Cm ^TwoIon implantation. After that,
Remove dist.

Next, as shown in FIG. 4, after removing the oxide film entirely, the substrate 32 is placed on a susceptor of the epitaxial growth apparatus, and a high temperature of, for example, about 1000 ° C. is applied to the substrate 32 by lamp heating. S in the reaction tube
By introducing iH ₂ Cl ₂ gas and H ₂ gas, an epitaxial layer 35 having a specific resistance of 0.1 to 3.5 Ω · cm and a thickness of about 1.0 to 6.0 μm is grown. Then, after a surface of the epitaxial layer 35 is thermally oxidized to form a silicon oxide film, for example, about 0.1 to 0.6 μm,
The oxide film corresponding to the P + type buried layer 37 is photo-etched to form a selective mask. Then, a P-type impurity, for example, boron (B) is ion-energy 20 to 65 ke.
V ions are implanted at a dose of 3.0 × 10 ^{12 to} 3.0 × 10 ¹⁴ / cm ² and diffused. After that, the oxide film used as the mask is removed. At this time, the N + type buried layer 33 and the P + type buried layer 34 are simultaneously diffused.

Then, for example, a heat treatment is applied to the entire substrate 32 while forming an oxide film by steam oxidation at about 800 to 1200 ° C., and a LOCO is formed on the P + type isolation region 36.
By forming the S oxide film 38, isolation between elements is further achieved. Here, the LOCOS oxide film 38 is formed to a thickness of, for example, about 0.5 to 1.0 μm. Next, the substrate 3
2, a gate silicon oxide film having a thickness of, for example, 0.0
The gate 40 is formed to a thickness of about 1 to 0.20 μm, polysilicon is formed on the oxide film, phosphorus (P) is diffused, and the polysilicon is etched. After that, a gate oxide film is formed on the gate 40. At this time, P +
The buried layers 34 and 37 of the mold are simultaneously diffused, and the P + type isolation region 36 is connected.

Next, as shown in FIG. 5, a photoresist having an opening at a portion where a P + type diffusion region 39 is formed is formed on the silicon oxide film formed in FIG. 4 by a known photolithography technique. It is formed as a selection mask. Then, a P-type impurity, for example, boron (B) is ion-energy 20 to 65 keV, and the introduced amount is 1.0 × 10 4.
Ion implantation is performed at ^{13 to} 1.0 × 10 ¹⁵ / cm ² . After that, the photoresist is removed.

Next, as shown in FIG. 6, on the silicon oxide film formed in FIG. 4, a photoresist having an opening at a portion where an N− type drain region 41 is to be formed by a known photolithography technique. Is formed as a selection mask. Then, an N-type impurity, for example, phosphorus (P) is ion-energy 25 to 70 keV, and the introduced amount is 1.0 × 1.
Ion implantation is performed at a rate of 0 ^{13 to} 1.0 × 10 ¹⁵ / cm ² . At this time, in the step of ion-implanting phosphorus (P) into the N − type drain region 41, the gate 40 and the LOCOS oxide film 38 are used as a selective mask in addition to the photoresist to form the N − type drain region 41. Can be more accurately ion-implanted. After that, the photoresist is removed. At this time, the P + type diffusion region 39 is simultaneously diffused.

Next, as shown in FIG. 7, a photoresist having an opening at a portion where a P + type well region 42 is to be formed is formed on the silicon oxide film formed in FIG. 4 by a known photolithography technique. It is formed as a selection mask. Then, a P-type impurity, for example, boron (B) is ion energy of 20 to 65 keV, and the introduced amount is 1.0 × 1.
Ion implantation is performed at 0 ^{15 to} 1.0 × 10 ¹⁷ / cm ² . At this time, as in the case of FIG. 6, in the step of implanting boron (B) into the P + type well region 42, the gate 40 is used in addition to the photoresist by using a selective mask, so that P
Ion implantation can be performed more accurately at the position of the + well region 42. After that, the photoresist is removed. At this time, the N− type drain region 41 is simultaneously diffused.

Next, as shown in FIG. 8, a photoresist having an opening at a portion where an N + type diffusion region 43 is to be formed is formed on the silicon oxide film formed in FIG. 4 by a known photolithography technique. It is formed as a selection mask. Then, an N-type impurity, for example, arsenic (As) is ion energy of 60 to 120 keV, and the introduced amount is 1.0 × 1.
Ion implantation is performed at 0 ^{15 to} 1.0 × 10 ¹⁷ / cm ² . At this time, as in the case of FIG. 6, in the step of implanting arsenic (As) into the N + type diffusion region 43, the gate 40 is used in addition to the photoresist as a selective mask, so that the N +
Ion implantation can be performed more accurately at the position of the diffusion region 43 of the mold. After that, the photoresist is removed. At this time, the P + type well region 42 is simultaneously diffused.

Next, as shown in FIG.
A sidewall is formed on the side surface of the gate 40 by using the method. Then, on the surface of the N ++ type diffusion region 43, a photoresist having an opening at a portion where the N ++ type source region 45 is formed on the silicon oxide film formed in FIG. 4 by a known photolithography technique is selected. It is formed as a mask. Then, an N-type impurity, for example, arsenic (As) is ion-implanted at an ion energy of 70 to 120 keV and an introduced amount of 1.0 × 10 ^{15 to} 1.0 × 10 ¹⁷ / cm ² . At this time, as in the case of FIG. 6, in the step of implanting arsenic (As) into the N ++ type source region 45, the N ++ type source region is formed by using the gate 40 in addition to the photoresist as a selective mask. The ion implantation can be performed more accurately at the position 45. After that, the photoresist is removed. At this time, the N + type diffusion region 43
Are simultaneously diffused.

Next, as shown in FIG. 10, a TEOS (Tetraethylortho) insulating film is formed on the silicon oxide film and the gate 40 formed in FIG.
(silicate) film 53 having a thickness of, for example, 0.01 to
The silicon nitride film 54 is formed to a thickness of about 0.20 μm.
Is formed, for example, in a thickness of about 0.01 to 0.20 μm. Then, on the silicon nitride film 54, a BPSG (phosphor boron silicate glass) film 46 having a thickness of, e.g.
A thickness of about 5 to 3.0 μm is formed, and then SOG (Spin
The surface is flattened by the (On Glass) film. Here, since the silicon nitride film 54 is formed under the BPSG film 46, even if moisture permeates the BPSG film 46 and enters the device, the silicon nitride film 54 can prevent the moisture. Becomes

Thereafter, contact holes 48 and 51 are formed by etching. Then, a photoresist having an opening at a portion where the P ++ type diffusion region 47 is formed is formed as a selection mask by a known photolithography technique. Then, a P-type impurity, for example, boric boron (BF) is ion-implanted at an ion energy of 30 to 75 keV and an introduction amount of 1.0 × 10 ^{15 to} 1.0 × 10 ¹⁷ / cm ² . After that, the photoresist is removed. At this time, the N ++ type source region 45 is simultaneously diffused.

Next, as shown in FIG. 11, an N ++ type drain lead region 4 is formed by a known photolithography technique.
A photoresist having an opening at a portion where 9 is to be formed is formed as a selection mask. Then, an N-type impurity, for example, arsenic (As) is ion-energy 20 to 50 ke.
V ions are implanted at a dose of 1.0 × 10 ^{15 to} 1.0 × 10 ¹⁷ / cm ² . At this time, the N ++ type drain region 4
In the step of ion-implanting arsenic (As) into element 9, a feature of this embodiment resides in that a contact hole 48 is used in addition to a photoresist as a selective mask. After that, the photoresist is removed. At this time, the P ++ type diffusion region 47 is simultaneously diffused.

Thereafter, on the N ++ type drain region 49, the N ++ type source region 45, and the P ++ type diffusion region 47, an Al external electrode 48 is formed through contact holes 48 and 51 for electrical connection to the outside. , 49 are formed, and the power MOS transistor 31 in the Bi-CMOS process shown in FIG. 1 is completed.

According to the method of manufacturing the semiconductor integrated circuit device of the present embodiment, N + formed on the surface of the N− type drain region 41 of the power MOS transistor 31 is formed.
The method is characterized by the method of forming the + type drain lead region 49.
That is, the N ++ type drain lead region 49 is formed by ion implantation through the contact hole 48. Therefore, in general, the contact hole 48 of the present embodiment is compared with the case where a selection mask is formed and ion implantation is performed.
Is used, the N ++ type drain lead-out region 49 can be accurately formed at a desired position. As a result, in order to solve the above-described problem, the N ++ type drain lead region 49 can be formed at a necessary distance from the gate 40 and there is no need to anticipate a mask shift.
An increase in the size of the power MOS transistor can be prevented.

In the above embodiment, the case of the N-channel power MOS transistor has been described. However, the same effect can be obtained in the case of the P-channel power MOS transistor. In the present embodiment, the power MO in the Bi-CMOS process is used.
Although the description has been given of the S transistor, the present invention is not limited to the Bi-CMOS process, and the same effect can be obtained if the structure includes a MOS transistor. Various changes can be made without departing from the spirit of the present invention.

[0058]

According to the present invention, in a MOS semiconductor device, an N ++ type drain extraction region is formed in a minimum necessary space on the surface of an N− type drain extraction region, and the N ++ type drain extraction region is formed. Is surrounded by the N− type drain region. Further, it has a structure in which the N-type drain region is formed deep under the gate of the MOS transistor. Thereby, when the source voltage or the drain voltage rises when the MOS transistor is turned off, the N− type epitaxial layer under the gate is inverted, and a P− type channel layer is formed under the gate. In this case, the N− type drain region can prevent direct contact between the inverted P− type channel layer and the N ++ type drain lead region. Further, the P-type inversion forming region can be reduced. As a result, when the N ++ type drain lead region comes into contact with the P− type channel layer,
The leakage current generated at that portion is greatly suppressed, and the M
The effect that power consumption when the OS transistor is OFF can be significantly reduced can be obtained.

Further, in the MOS semiconductor device according to the present invention, the N ++ type drain extraction region is formed at a minimum required space on the surface of the N− type drain extraction region. It has a structure in which the periphery is surrounded by the N-type drain region. Accordingly, when the source voltage or the drain voltage rises when the MOS transistor is turned off and the electric field between the drain region and the gate increases, the electric field between the drain region and the gate is lower than and surrounding the gate than the N ++ type drain extraction region. Since the N- type drain region having a low impurity concentration is formed deep, a depletion layer formation region can be secured. As a result, an electric field generated by an increase in the source voltage or the drain voltage can be countered by forming a depletion layer. In addition, the influence of the high electric field on the silicon oxide film formed under the gate can be greatly reduced, and the effect of greatly reducing the characteristic fluctuation of the silicon oxide film can be obtained.

According to the present invention, in the method for manufacturing a MOS semiconductor device, the N
In the step of forming the N ++ type drain lead region formed on the surface of the − type drain region, the N ++ type drain lead region uses a silicon oxide film on a device as a selection mask, and is formed through a contact hole. It is characterized by being formed by ion implantation. Thus, in comparison with the case where a selection mask is formed and ion implantation is generally performed, in the case of the present embodiment, the N ++ type drain lead-out region can be accurately formed at a desired position by using a contact hole. it can. As a result, in order to solve the above-mentioned problem, the N ++ type drain lead-out region can be formed separately from the gate, and there is no need to anticipate a mask shift, so that an increase in MOS transistor size can be prevented.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a MOS semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view illustrating a method for manufacturing a MOS semiconductor device according to the present invention.

FIG. 3 is a sectional view illustrating a method for manufacturing a MOS semiconductor device according to the present invention.

FIG. 4 is a cross-sectional view illustrating a method for manufacturing a MOS semiconductor device according to the present invention.

FIG. 5 is a sectional view illustrating a method for manufacturing a MOS semiconductor device according to the present invention.

FIG. 6 is a sectional view illustrating a method for manufacturing a MOS semiconductor device according to the present invention.

FIG. 7 is a cross-sectional view illustrating a method for manufacturing a MOS semiconductor device according to the present invention.

FIG. 8 is a cross-sectional view illustrating a method for manufacturing a MOS semiconductor device according to the present invention.

FIG. 9 is a cross-sectional view illustrating the method for manufacturing a MOS semiconductor device according to the present invention.

FIG. 10 is a sectional view illustrating a method for manufacturing a MOS semiconductor device according to the present invention.

FIG. 11 is a sectional view illustrating a method for manufacturing a MOS semiconductor device according to the present invention.

FIG. 12 is a cross-sectional view illustrating a conventional MOS semiconductor device.

FIG. 13 is a cross-sectional view illustrating a method for manufacturing a conventional MOS semiconductor device.

FIG. 14 is a sectional view illustrating a method for manufacturing a conventional MOS semiconductor device.

FIG. 15 is a sectional view illustrating a method for manufacturing a conventional MOS semiconductor device.

FIG. 16 is a cross-sectional view illustrating a method for manufacturing a conventional MOS semiconductor device.

FIG. 17 is a cross-sectional view illustrating a method for manufacturing a conventional MOS semiconductor device.

FIG. 18 is a sectional view illustrating a method for manufacturing a conventional MOS semiconductor device.

FIG. 19 is a sectional view illustrating a method for manufacturing a conventional MOS semiconductor device.

FIG. 20 is a sectional view illustrating a method for manufacturing a conventional MOS semiconductor device.

Continued on front page F-term (reference) BD05 BE07 BF01 BF04 BG08 BH13 BH17 BH30 BH43 BH49 BJ01 BJ05 BK13 BK20 CA03 CB01 CB03 CC03 CD02 DA06

Claims (9)

[Claims] A semiconductor substrate of one conductivity type; an epitaxial layer of opposite conductivity type laminated on the surface of the substrate; and a separation region of one conductivity type penetrating the epitaxial layer to form an island region; A LOCOS oxide film formed on the isolation region for isolating the island region between elements; and a MO of a reverse conductivity type channel formed in the island region.
An S transistor; an insulating film formed on the LOCOS oxide film and the MOS transistor; and an external electrode formed through a contact hole of the insulating film; a reverse conductivity type drain of the MOS transistor. The area is
A second diffusion region having a width substantially equal to the width of the first diffusion region having a higher impurity concentration and the width of the contact hole having a higher impurity concentration.
A MOS semiconductor device characterized by being formed so as to overlap with a diffusion region. 2. The MOS semiconductor device according to claim 1, wherein said second diffusion region is connected to said external electrode. 3. The MOS semiconductor device according to claim 1, wherein said first diffusion region is formed deep in a depth direction of said epitaxial layer. 4. The MOS semiconductor device according to claim 1, wherein said second diffusion region is formed shallow in a depth direction of said epitaxial layer. 5. A step of preparing a semiconductor substrate of one conductivity type, a step of laminating an epitaxial layer of the opposite conductivity type on the substrate, and forming an island region by the isolation region of one conductivity type penetrating the epitaxial layer. Forming a LOCOS oxide film on the isolation region; and forming a reverse conductivity type first MOS transistor of a reverse conductivity type channel in the island region.
Forming an insulating film on the epitaxial and LOCOS oxide films; forming a contact hole in the insulating film; and forming a reverse conductive type drain region of the MOS transistor in the contact region. Implanting impurities through holes and forming a second diffusion region of the opposite conductivity type so as to overlap with the first diffusion region. 6. The method according to claim 5, wherein the second diffusion region is connected to the external electrode. 7. The method according to claim 5, wherein the second diffusion region has a higher impurity concentration than the first diffusion region. 8. The method according to claim 5, wherein the first diffusion region is formed deep in a depth direction of the epitaxial layer. 9. The semiconductor device according to claim 5, wherein the second diffusion region has a width substantially equal to that of the contact hole and is formed shallow in a depth direction of the epitaxial layer.
The method for manufacturing a MOS semiconductor device according to any one of the above.