JP3454734B2 - Manufacturing method of semiconductor integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a junction field effect transistor (hereinafter referred to as J-FET) in a BIP-IC. The present invention relates to a formed semiconductor integrated circuit device. 2. Description of the Related Art J-FETs have a higher input impedance than BIP type devices and a higher electrostatic breakdown resistance than MOS type FET devices. I have. In addition, it has characteristics such as low low frequency noise and good high frequency characteristics for small signal amplification. In addition to the discrete type, a J-FET integrated on a BIP-IC has been developed. [0003] an example that, for example, Japanese 58-197885 Patent Publication, shown in FIG. First, a P-type semiconductor substrate 1
, An N-type epitaxial layer 2 is laminated, and an N + -type buried layer 3 is formed therebetween. This buried layer 3
P + type isolation region 4 surrounds epitaxial layer 2
An island region 5 is formed by penetrating the semiconductor substrate 1 from the surface. On the surface of the island region 5, an N + type top gate region 6 is formed. Under the top gate region 6, a P type channel region 7 is formed. A P-type source region 8 and a P-type drain region 9 are formed at both ends of the channel region, and a high-concentration gate contact region 10 is formed outside. Further, a source electrode, a drain electrode and a gate electrode are interposed via an insulating film to constitute a P-channel type J-FET. Since a PN junction is formed in the gate region, the PN junction is reverse-biased, and the drain current is controlled by the size of the depletion layer. [0007] However, the P-channel J-FET has a problem that the SN ratio is poor due to the mobility of carriers (holes). Therefore, it is desired to integrate an N-channel type J-FET having a good SN ratio in an integrated circuit. SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problem, and firstly, an N-channel type is formed in a well region of one conductivity type formed in an island region and serving as a bottom gate region. J-
The problem is solved by forming an FET. The formation of the well region allows the N-channel type J
-An FET can be formed and can be built in a BIP-IC. Furthermore, by providing a buried layer of one conductivity type between the well region and the buried layer of the opposite conductivity type provided below the well region, a depletion layer generated by a reverse bias is provided. The formation portion can be lowered from between the well region and the island region to between the buried layer of the opposite conductivity type and the buried layer of one conductivity type, thereby preventing punch-through of the depletion layer from occurring. I have. Further, a simplified manufacturing process is established by forming a gate lead-out region of a J-FET by diffusion of a base of an NPN transistor and forming a source / drain region by diffusion of an emitter. Further, by forming the channel region and the top gate region through the same mask, the process can be further simplified. Embodiments of the present invention will be described below. First step: Referring to FIG. 1A, a P-type semiconductor substrate 20 is prepared. An oxide film is formed by thermally oxidizing the surface, and an opening is formed in the oxide film by a photoetching technique. Semiconductor substrate 2 exposed at the opening
Antimony (Sb) is diffused on the surface 0 to form N + type buried layers 21 and 22. Subsequently, the oxide film is formed again, an opening is formed in the oxide film again by photoetching, and boron (B) is ion-implanted into the surface of the substrate 20 to form a P + type buried layer 23 and an isolation region 24. I do. Second step: Refer to FIG. 1B. After removing the oxide film mask for ion implantation, an N-type epitaxial layer 25 is formed by a vapor phase growth method. The film thickness is 5 to 12 μm, and the specific resistance ρ = 5 to 2
0 Ω · cm. After forming the epitaxial layer, a Si oxide film is formed on the surface of the epitaxial layer 25, and an opening is formed in the Si oxide film by a photo-etching technique. Boron (B, BF2) is ion-implanted through the opening to form a P-type well region 26. And 1 for the whole
By applying a heat treatment at 100 ° C. for about 1 to 3 hours, the lower isolation region 24 is diffused above the epitaxial layer 25. Third step: Refer to FIG. 2A. Subsequently, a resist mask for ion implantation is formed on the Si oxide film grown on the surface of the epitaxial layer 25 by this heat treatment, and corresponds to the upper isolation region 27. P-type impurities, in this case, boron are ion-implanted through the openings of the portions. Then, after removing the resist mask, 1100 ° C., 1 to 3 hours until the upper and lower isolation regions 24 and 27 are combined and the P-type buried layer 23 and the P-type well region 26 are combined. Diffuse heat diffusion.
By the isolation regions 24 and 27, the epitaxial layer 25 is junction-isolated into a first region where a junction FET (J-FET) is to be formed and a second region where an NPN transistor is to be formed. Fourth step: After removing the SiO 2 film grown on the surface of the epitaxial layer 25 by the heat treatment shown in FIG.
2 Reattach the film. A mask for ion implantation is provided on the SiO2 film with a photoresist film, a portion corresponding to the base region 28 and the gate contact region 29 of the NPN transistor is opened, and boron as a base impurity is ion-implanted therein. After removing the resist mask, 1100
Base diffusion is performed by a heat treatment at a temperature of 1 to 2 hours. Base region 28 and gate contact region 29 are diffusion regions shallower than P-type well region 26, and gate contact region 29 is P-type well region 26 and N-type epitaxial layer 25.
Are arranged so as to cover the upper part of the PN junction with the PN junction.
That is, the gate contact region 29 annularly surrounds the periphery of the well region 26. Then, the ion implantation mask is attached again, and the emitter region 30 to be formed is
Portions corresponding to the source region 31, the drain region 32 and the contact region 35 are opened, and arsenic or phosphorus as an N-type impurity is ion-implanted therein. Fifth step: Refer to FIG. 3A.
A mask layer 41 having an opening 40 is formed on a portion of the Si oxide film corresponding to. The end of the opening 40 is located above the gate contact region 29 and exposes the surface of the well region 26 and the surface near the inner peripheral end of the annularly formed gate contact region 29. Then, arsenic or phosphorus, which is an N-type impurity that forms the channel region 33 through the opening of the mask layer 41, is doped with 1 × 10 ¹² to 10 ¹³ atoms
Ions are implanted at s / cm ³ . [0020] Step 6: Figure 3 (B) refer to the mask layer 41 intact, the top through the opening 40
B or B which is a P-type impurity forming the gate region 34
F ₂ is ion-implanted at 1 × 10 ¹³ to 10 ¹⁴ atoms / cm ³
Enter . Thereafter, the mask for ion implantation is removed, and the emitter is diffused at 1000 ° C. for 30 to 1 hour to form an emitter region 30, a source region 31, and a drain region 32.
As well as N-type impurities and P-type impurities
Is thermally diffused to form a channel region 33 and a top gate region 34.
Are simultaneously formed. Note that after the emitter diffusion, the impurity
The channel region 33 and the top gate are
The heating region 34 may be formed at the same time. Seventh step: see FIG. 4A Finally, a contact hole is opened in the SiO2 film on the surface of the epitaxial layer, and a drain electrode, a source electrode, a gate electrode, a VCC applying electrode, an emitter electrode, a base electrode and a collector are formed. Form electrodes. The semiconductor integrated circuit manufactured by these steps is divided into the first and second regions separated by the separation regions 24 and 27.
NPN transistors and J-FET elements are formed in the regions of FIG. The J-FET element is an element configured by using the well region 26 as a bottom gate. The gate contact region 29 reaches the well region 26 to apply a gate potential to the bottom gate and the top gate. The source / drain regions 31 and 32 are It is formed to a depth penetrating the channel region 33. FIG. 4B is a plan view of the J-FET device. The gate contact region 29 has an annular shape and overlaps the top gate region 34, the channel region 33, and the peripheral portion of the well region 26, and overlaps the well region 26,
It is designed to have a higher impurity concentration than the channel region 33 and the top gate region 34. Thereby, the PN of each area is
Exposing the junction to the surface of the epitaxial layer 25 is avoided. A source region 31 and a drain region 32 are formed in a band shape in a portion surrounded by the annular gate contact region 29. Then, the gate contact region 2
The depletion layer formed at the PN junction between the well region 26 and the channel region 33 and the depletion layer formed at the PN junction between the top gate region 34 and the channel region 33 are controlled in accordance with the voltage applied via Thus, the channel current flowing between the source region 31 and the drain region 32 is controlled. Also, the epitaxial layer 25 around the well region 26
The N + type contact region 35, a voltage higher than the voltage applied to the gate electrode (for example, the power supply voltage Vc
c), the gate contact region 29 is short-circuited and the same potential as the gate is applied, the ground potential (GND) is applied, or a floating state where no potential is applied. The circuit is designed so that the gate potential is given a potential lower than the source potential. When a large amplitude signal having an amplitude of about 1 V or more is applied as a gate signal, a VCC potential is applied to prevent the operation of the parasitic PNP transistor including the well region 26, the epitaxial layer 25, and the isolation regions 24 and 27. Is good. Conversely, the amplitude of the gate signal is, for example, ± 0.0.
When a weak amplitude signal of about 01 to 0.5 V is applied, if a reverse bias having a large potential difference is applied between the epitaxial layer 25 and the well region 26, the weak signal may not be recognized due to the dark current of the PN junction. There is. In this case, it is preferable that the epitaxial layer 25 be in a floating state in which no potential is applied. The first feature of the present invention resides in the well region 26. By forming the P-type well region 26, an N-type channel region 33 can be formed in this region, and the BIP-
An N-channel J-FET can be formed in an IC. Therefore, an N-channel type J-FET having a high SN ratio, which has conventionally been commercialized only as a discrete type, can be integrated into one chip, the ease of assembling a set and the like using the same is improved, and the cost merit increases. The second feature is that the P + type buried layer 23
It is in. For example, the contact region 35 reverse biases the epitaxial layer 25 to VCC, and applies a potential lower than VCC to the bottom / top gate to apply a reverse bias. The depletion layer due to the reverse bias forms the epitaxial layer 25 and the well region. Spread between 26. Temporarily
If the buried layer 23 of the + layer is omitted, since the remaining film thickness of the well region 26 is small, the depletion layer reaches the channel region 33 and is likely to punch through. In the present invention, P +
The provision of the buried layer 23 causes a depletion layer to be generated at the PN junction between the P + buried layer 23 and the N + type buried layer 21, which is farther from the channel region 33 and makes it difficult for punch-through to occur. The withstand voltage characteristics between the region 33 and the bottom gate (well region) 26 can be improved. In addition, by forming the gate contact region 29 simultaneously with the formation of the base region 28 of the NPN transistor, it is possible to measure the sharing of the manufacturing process. The gate contact region 29 is overlapped with the end of the PN junction formed by the well region 26, the channel region 33, and the top gate region 34, so that the surface of the epitaxial layer 25 (the interface with the Si oxide film) is formed. Without exposing these PN junctions to the S
It is possible to prevent generation of a leak current due to contact with the i-oxide film. Separating the low impurity concentration channel region 33 from the oxide film interface by the top gate region 34 also has the effect of reducing leakage (low noise). Further, by simultaneously forming the source / drain regions 31 and 32 simultaneously with the formation of the emitter region 30, the manufacturing process can be further simplified. Further, by forming the channel region 33 and the top gate region 34 with the common mask layer 41,
Further simplification of the manufacturing process can be achieved. According to the present invention, an N-channel J-FET having an excellent SN ratio is formed by forming an N-channel J-FET in a well region of one conductivity type serving as a bottom gate.
It has the advantage that ET can be built into a BIP-IC. Further, by providing a buried layer of one conductivity type below the well region, a portion where a depletion layer is generated due to a reverse bias can be kept far away from the channel region 33. And the withstand voltage characteristics between the channel and the bottom gate can be improved. Further, by forming the gate contact region 29 and the source / drain regions 31 and 32 by forming each region of the NPN transistor, there is an advantage that the manufacturing process can be simplified. Further, by forming the channel region 33 and the top gate region 34 using the common mask layer 41, there is an advantage that the manufacturing process can be further simplified.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view for explaining the present invention. FIG. 2 is a cross-sectional view for explaining the present invention. FIG. 3 is a cross-sectional view for explaining the present invention. FIG. 4 is a sectional view (A) and a plan view (B) for explaining the present invention. FIG. 5 is a cross-sectional view illustrating a conventional semiconductor integrated circuit device.

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-54-150092 (JP, A) JP-A-54-158888 (JP, A) JP-A-10-163334 (JP, A) JP-A 53-158334 149773 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/337 H01L 29/808 H01L 29/778 H01L 27/095 H01L 27/06

Claims (1)

(57) Claims 1. A step of forming a reverse conductivity type epitaxial layer on a semiconductor substrate of one conductivity type, and forming a well of one conductivity type in a first region of the epitaxial layer. Forming a region, forming a base region of one conductivity type in a second region of the epitaxial layer, and simultaneously forming the gate contact region on the surface of the well region; Forming an emitter region of the opposite conductivity type and simultaneously forming source / drain regions on the surface of the well region; and an opening on the surface of the well region such that an end thereof is located above the gate contact region. Forming a mask layer having the following steps: after forming the gate contact region, ion-implanting impurities of the opposite conductivity type using the mask layer as a mask; After tact region forming a step of ion-implanting impurity of one conductivity type using the mask layer as a mask, the opposite conductivity type impurity and an impurity of one conductivity type of the thermal diffusion, the end to each of the gate contact region Heavy
Forming a channel region and a top gate region to be folded at the same time.