JP2949743B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a self-aligned bipolar transistor and an LDD.
(Lightly deped drain) The present invention relates to a method for manufacturing a semiconductor device suitable for manufacturing a MOS transistor or the like.

[Prior Art] FIG. 3 is a sectional view showing a method of manufacturing a conventional high-speed bipolar transistor.

First, an n ⁺ -type buried collector layer 52 is formed in a predetermined region of a p-type silicon substrate 51, and an n-type epitaxial layer 53 is formed on the substrate 51 and the buried collector layer 52.

Next, an element isolation insulating film 54 and an n ⁺ -type collector lead-out region 55 are selectively formed in a region reaching the substrate 51 and the buried collector layer 52 from the surface of the epitaxial layer 53. Each element region is electrically insulated from each other by the element isolation insulating film 54. In addition, due to this element isolation insulating film 54,
Base and emitter formation area and collector extraction area
55 is separated.

Next, a collector extraction electrode 56b made of n ⁺ -type polycrystalline silicon is selectively formed on the collector extraction region 55, and a base extraction electrode 56a made of p ⁺ -type polycrystalline silicon is selectively formed on the epitaxial layer 53. Form. Then, after an insulating film 57 is formed on the entire surface of the substrate 51, the insulating film 57 and the base extraction electrode 56a in the region where the emitter is to be formed are sequentially removed by using photolithography technology, and an opening reaching the epitaxial layer 53 is formed. Form 63.

Next, heat treatment is performed to introduce a p-type impurity at a high concentration from the base extraction electrode 56a to the epitaxial layer 53, thereby forming the p ⁺ -type graft base region 58. Thereafter, a low concentration p-type base region 59 is formed by introducing a p-type impurity into the epitaxial layer 53 from the opening 63 by ion implantation.

Next, a sidewall insulator 60 is formed on the sidewall of the opening 63. Then, the emitter electrode 61 is formed by burying n ⁺ -type polycrystalline silicon in the opening 63 and extending the polycrystalline silicon on the insulating film 57. Thereafter, an n-type impurity is diffused from the emitter electrode 61 into the base region 59 to form a high-concentration n ⁺ -type emitter region 62. Then, the insulating film 57 on the base lead electrode 56a and the collector lead electrode 56b is selectively opened, and a contact hole 64 is provided.

In the bipolar transistor thus formed, the emitter region 62 is reduced by the thickness of the sidewall insulating film 60 from the opening width of the opening 63 formed by the photolithography technique, and the emitter region 62 The distance from the graft base region 58 can be determined by the thickness of the sidewall insulating film 60. In this case, a bipolar transistor having excellent high-frequency characteristics is manufactured by forming an appropriate thickness of the sidewall insulating film 60 and setting an appropriate interval between the emitter region 62 and the graft base region 58. can do.

When a bipolar transistor and a MOS transistor are simultaneously formed on the same semiconductor substrate as in a Bi-COMS device, a source / drain region is formed in the same manner as the graft base region 58, and a base region is formed.
Instead of not forming the 59 and the emitter region 62, a gate oxide film is formed on the epitaxial layer 53, and a gate electrode is formed by the same method as that for forming the emitter electrode 61.
This enables the same process as bipolar transistor
A MOS transistor can be formed.

[Problems to be Solved by the Invention] However, the conventional method for manufacturing a semiconductor device has the following disadvantages.

That is, the side wall insulating film 60 is formed to electrically insulate the base extraction electrode 56a and the emitter electrode 61, and the transistor characteristics change depending on the thickness of the side wall insulating film 60. That is, it is necessary to reduce the width of the emitter region 62 in order to improve the high frequency characteristics of the transistor. However, if the thickness of the sidewall insulating film 60 is increased to reduce the width of the emitter region, the distance between the graft base region 58 and the emitter region 62 becomes longer, and the low-concentration p-type base region 59 interposed therebetween. Therefore, the base resistance increases. If the impurity concentration of the base region 59 is increased in order to avoid an increase in the base resistance, the _hFE characteristics of the transistor and the high-frequency characteristics are disadvantageously deteriorated. In addition, if the thickness of the sidewall insulating film 60 is reduced to reduce the base resistance, a high concentration of p ⁺
The type graft base region 58 and the n ⁺ -type emitter region 62 are in direct contact with each other, so that the reverse breakdown voltage between the base and the emitter is deteriorated and a current leak of input characteristics occurs.

In addition, a bipolar transistor and a
When a MOS transistor is formed simultaneously, there is also a problem that it is difficult to match the manufacturing methods of the bipolar transistor and the MOS transistor. That is, in the bipolar transistor, the thickness of the sidewall insulating film needs to be formed so as not to make contact between the graft base region 58 and the emitter region 62 in order to avoid a current leak of the input characteristic. However, when a MOS transistor is formed such that the source / drain electrode and the gate electrode are separated from each other by the sidewall insulating film, similarly to the bipolar transistor, the distance from the end of the source / drain region to the end of the gate electrode is reduced. Because of the separation, the performance of the MOS transistor deteriorates.

The present invention has been made in view of such a problem, and it is possible to stably manufacture a bipolar transistor that can reduce a base resistance without increasing an impurity concentration of a base region and that has a small power supply leakage of input characteristics. It is another object of the present invention to provide a method of manufacturing a conductor device that can perform the MOS transistor even when the MOS transistor is formed on the same semiconductor substrate without deteriorating the performance of the MOS transistor.

[Means for Solving the Problems] In a method for manufacturing a semiconductor device according to the present invention, a step of selectively forming a second conductivity type polycrystalline silicon film on a first conductivity type semiconductor region; First on the entire surface of the semiconductor region
Forming an insulating film, selectively forming a first opening reaching the first conductive type semiconductor region from the surface of the first insulating film, and forming the first opening from the polycrystalline silicon film. Forming a first diffusion region by diffusing a second conductivity type impurity into the first conductivity type semiconductor region; and forming a second insulating film only on a side wall of the first opening. Embedding a third insulating film in the first opening, and removing the second insulating film to form a second opening to expose the first conductivity type semiconductor region. Forming a second diffusion region having an impurity concentration lower than that of the first diffusion region by introducing a second conductivity type impurity from the second opening into the first conductivity type semiconductor region; Embedding a fourth insulating film in the second opening, and removing the third insulating film; Forming a third opening from the first
Exposing the conductive semiconductor region.

[Operation] In the present invention, first, a second conductivity type polycrystalline silicon film and a first insulating film are formed on a first conductivity type semiconductor region, and a polycrystalline silicon film is formed from the surface of the first insulating film. A first opening reaching the first conductivity type semiconductor region through the first opening is formed. Then, a second diffusion type impurity is introduced from the polycrystalline silicon film into the first conductivity type semiconductor region to form a first diffusion region. As a result, a first diffusion region is formed in the first conductive type semiconductor region in a region sandwiching the first opening. Next, after forming a second insulating film only on the side wall of the first opening, a third insulating film is buried in the first opening. Then, by removing the second insulating film, a second opening is formed in which the first conductivity type semiconductor region is exposed. From the second opening, the second opening is formed in the first conductivity type semiconductor region. A second conductivity type impurity is introduced. Thereby, a second diffusion region is formed in a region of the first conductivity type semiconductor region adjacent to the first diffusion region. Then
After embedding a fourth insulating film in the second opening, the third insulating film is removed to form a third opening. Thus, the first diffusion region in the region adjacent to the second diffusion region
The conductive semiconductor region is exposed.

In the above-described method for manufacturing a semiconductor device, the first diffusion region is a high-concentration impurity region, and the second diffusion region is a medium-concentration impurity region having a lower impurity concentration than the first diffusion region. Thus, in the case of a bipolar transistor, the first diffusion region has the same conductivity type as the first diffusion region between the first diffusion region acting as a graft base region and the emitter region formed below the third opening. The concentration impurity diffusion region (second diffusion region) is interposed. For this reason,
Even if the width of the emitter region is reduced, the emitter region and the graft base region are connected via the second diffusion region, thereby suppressing an increase in base resistance. Further, since it is not necessary to increase the impurity concentration of the base region, _hFE and high-frequency characteristics do not decrease. Further, since the graft base region and the emitter region are not directly connected, a decrease in the reverse breakdown voltage between the base and the emitter is suppressed.

Also, when a MOS transistor is formed at the same time as the bipolar transistor, the first diffusion region acting as a source / drain region and the end of the gate electrode formed in the third opening region are formed between the first diffusion region and the first opening region. Since the medium-concentration impurity diffusion region (second diffusion region) of the same conductivity type as the diffusion region is interposed, the second diffusion region acts as a part of the source / drain region, and the source / drain region and the gate electrode Deterioration of the performance of the MOS transistor due to the separation from the end is prevented.

Example Next, an example of the present invention will be described with reference to the accompanying drawings.

1 (a) to 1 (g) are sectional views showing a first embodiment in which the present invention is applied to the manufacture of a bipolar transistor in the order of steps.

First, as shown in FIG. 1A, an n ⁺ -type buried collector layer 2 is formed in a predetermined region of a p-type silicon substrate 1. Thereafter, an n-type epitaxial layer 3 is formed on the p-type silicon substrate 1 and the buried collector layer 2. Then, an element isolation insulating film 4 is selectively formed in a region reaching the silicon substrate 1 or the buried collector layer 2 from the surface of the epitaxial layer 3 and reaches the buried collector layer 2 from the surface of the epitaxial layer 3. An n ⁺ -type collector lead-out region 5 is formed in a predetermined region. Next, a base extraction electrode 6a made of p ⁺ -type polycrystalline silicon is selectively formed with a thickness of 2000 to 4000 ° on the epitaxial layer 3 in a region where a base and an emitter are to be formed, and n ⁺ Lead electrode 6b made of polycrystalline silicon
It is selectively formed with a thickness of 2000 to 4000 mm. Thereafter, a silicon oxide film 7 and a polycrystalline silicon film 8 are formed on the entire surface of the substrate 1.
Are sequentially formed with a thickness of 2000 to 4000 mm and 1000 to 2000 mm, respectively.

Next, as shown in FIG. 1 (b), the first opening 9 is formed by sequentially removing the polycrystalline silicon film 8, the silicon oxide film 7, and the base extraction electrode 6a in the region where the emitter is to be formed. I do. Thereafter, heat treatment is performed to diffuse a p-type impurity from the base extraction electrode 6a into the epitaxial layer 3 to form a high-concentration p ⁺ -type graft base region 10 having a layer resistance of about 50 to 200 Ω / □. Then, after forming a first silicon nitride film 11 on the entire surface of the substrate 1 to a thickness of about 2000 to 4000 °, the first silicon nitride film 11 is etched and packed by reactive ion etching, and the first silicon nitride film 11 is formed only on the side wall of the first opening 9. One silicon film 11 is left.

Next, as shown in FIG. 1 (c), a coating silicon oxide film 12 is applied to the entire surface of the substrate 1 by a spin coating method, and the first opening 9 is filled with the coating silicon oxide film 12.

Next, as shown in FIG. 1 (d), the coated silicon oxide film 12 is etched back by reactive ion etching so that the coated silicon oxide film 12 remains only in the opening 9 and the other regions are removed. The applied silicon oxide film 12 is removed. Thereafter, by removing the first silicon nitride film 11 by etching, a second opening 9a is provided around the applied silicon oxide film 12, and the epitaxial layer 3 is exposed.
In this case, for example, only the first silicon nitride film 11 can be selectively removed by performing etching under an etching condition in which the selectivity between the silicon nitride film and the applied silicon oxide film is large. After that, boron (B), which is a p-type impurity, is ion-implanted into the epitaxial layer 3 from the opening 9a, and then heat treatment is performed so that the layer resistance is 500 to 1 kΩ.
A middle concentration p-type base connection region 14 of about / □ is formed.

Next, as shown in FIG. 1E, a second silicon nitride film 15 is formed on the entire surface of the substrate 1, and the second opening 9a is filled with the second silicon nitride film 15. In this case, the second
The thickness of the silicon nitride film 15 is made to be half or more of the first silicon nitride film 11 formed in the step shown in FIG.

Next, as shown in FIG. 1 (f), the second silicon nitride film 15 is etched back by the reactive ion etching method, and the second silicon nitride film 15 is formed only in the second opening 9a.
Is left, and the second silicon nitride film 15 in the other region is removed. Thereafter, the coated silicon oxide film 12 is removed by wet etching to form a third opening 9b, and the epitaxial layer 3 is exposed. In this case, the etching is performed under the etching conditions that can obtain a large selectivity between the silicon nitride film and the coated silicon oxide film, thereby leaving the second silicon nitride film 15 and leaving the coated silicon oxide film.
Remove 12 Thereafter, boron is ion-implanted into the exposed region of the epitaxial layer 3 to have a layer resistance of 2 to 4 kΩ /
A p ^- type base region 16 having a low concentration of about □ is formed.

Next, as shown in FIG.
An n ⁺ -type polycrystalline silicon film 17 is formed to a thickness of 1000 to 3000 °. Then, a heat treatment is applied to this polycrystalline silicon film 17.
Diffuses n-type impurities into the base region 16 from the
An n ⁺ type emitter region 18 is formed. Thereafter, the second polycrystalline silicon film 17 and the polycrystalline silicon film 8 other than the emitter region are simultaneously removed, and then the silicon oxide film 7 on the base lead electrode 6a and the collector lead electrode 6b is selectively opened. A contact hole 19 is formed.

The bipolar transistor manufactured in this manner includes a p ⁺ -type graft base region 10 and an emitter region via a p-type base connection region 14 having a lower layer resistance than the base region 16.
As a result, the base resistance is reduced and stabilized. Normally, the layer resistance of the base region is 2 to 4 kΩ, and the layer resistance of the p-type base connection region 14 is 500 to 1 kΩ / □ as described above. , The resistance between the emitter regions is reduced to about 1/4 of the conventional resistance.

In the present embodiment, the polycrystalline silicon film 8 is formed on the silicon oxide film 7 and the polycrystalline silicon film 8 is used as an etching mask when the coated silicon oxide film 12 is removed. Polycrystalline silicon film 8 if the etching selectivity between silicon oxide film 12 and silicon oxide film 12 is appropriate.
Need not be formed.

FIGS. 2A to 2D are cross-sectional views showing a second embodiment in which the present invention is applied to a Bi-CMOS manufacturing method in the order of steps.

First, as shown in FIG. 2 (a), a p-type silicon substrate
The n ⁺ -type buried layers 22 and n
A well region 24 is formed. Also, the n-channel MO of the substrate 21
A p ⁺ type buried layer 23 and a p well region 25 are formed in the region where the S transistor is to be formed. Then, an element isolation insulating film 26 is formed at the boundary between these element regions and at the boundary between the region where the base region of the bipolar transistor is to be formed and the region where the collector extraction region is to be formed, and separates each region. afterwards,
A p ⁺ -type polycrystalline silicon film 27 is formed in a predetermined shape on the n-well region 24 in the p-channel MOS transistor region and on the n-well 24 in the base transistor formation region of the bipolar transistor. Further, an n ⁺ -type polycrystalline silicon film 28 is selectively formed on the p-well region 25 in the n-channel MOS transistor region and on the n-well 24 in the collector extraction region of the bipolar transistor. Then, a silicon oxide film is formed on the entire surface of the substrate 21.
29 and a polycrystalline silicon film 30 are formed.

Next, as shown in FIG. 2B, in the same manner as the steps shown in FIGS. 1B to 1D in the first embodiment,
An n-well region 24 or a p-well region 25 from the surface of the polycrystalline silicon film 30 in a predetermined region via the silicon oxide film 29 and the p ⁺ -type polycrystalline silicon film 27 or the n ⁺ -type polycrystalline silicon film 28
Is formed, and the n-well region 24 and the p-well region 25 are exposed. Next, to form the high-concentration p ⁺ -type region 31 by diffusing p-type impurities from the p ⁺ -type polycrystalline silicon film 27 in the n-well region 24, the n ⁺ -type polycrystalline silicon between 28 to p-well region 25 An n-type impurity is diffused to form a high-concentration n ⁺ -type region 32. Thereafter, an insulating film (not shown) is formed only on the side wall of the first opening, and the coated silicon oxide film 33 is buried in the first opening, and then the side wall of the first opening is formed. By removing the insulating film formed in the portion, a second opening 43 is formed, and the n-well region 24 and the p-well region 25 on the side of the coated silicon oxide film 33 are exposed.
Then, a p-type impurity is introduced into the exposed portion of the n-well region 24 to form a medium concentration p-type region 35, and an n-type impurity is introduced into the exposed portion of the p-well region 25 to form a medium concentration n-type A region 36 is formed.

Next, as shown in FIG. 2C, the second opening 43 is formed with the silicon nitride film 37 in the same manner as in the steps shown in FIGS. 1E and 1F in the first embodiment. After the filling, the third silicon oxide film 33 is removed to form a third opening 44, and the n-well region 24 in the region sandwiched by the silicon nitride film 37 is formed.
And the p-well region 25 is exposed. Then, a p-type impurity is introduced into the exposed region of the n-well region 24 in the bipolar transistor region to form a low-concentration p ⁻ -type base region 39.
In the MOS transistor region, the n-well region 2
A gate oxide film 38 is formed on the p-well region 25 with a thickness of about 100 to 200 °.

Next, as shown in FIG. 2D, an n-type polycrystalline silicon film 40 is formed on the base region 39 and the gate oxide film 38, and an n-type impurity is doped from the polycrystalline silicon film 40 into the base region 39. By introduction, an n ⁺ -type emitter region 41 is formed. In the first embodiment, similarly to the step shown in FIG. 1 (g), after the polycrystalline silicon film 30 is selectively removed, a predetermined region of the silicon oxide film 29 is opened to form a contact hole 42. To form Thus, the Bi-CMOS is completed.

In this embodiment, as described above, the bipolar transistor and the MOS transistor can be simultaneously and easily formed on the same substrate. This Bi-CMOS is composed of a bipolar transistor having excellent high-frequency characteristics as described in the first embodiment and a MOS transistor having an LDD structure.

When not forming a bipolar transistor,
A high-performance CMOS composed of MOS transistors having an LLD structure can be formed.

[Effects of the Invention] As described above, according to the present invention, the first and second diffusion regions of the second conductivity type are formed adjacent to each other in the semiconductor region of the first conductivity type. In this case, even if the thickness of the sidewall insulating film is increased and the width of the emitter region is reduced, the high-concentration graft base region and the low-concentration intrinsic base region, which are the first diffusion regions, are connected to the second diffusion region. And the resistance between the graft base region and the emitter region can be reduced.
Therefore, a bipolar transistor having a low base resistance, excellent high-frequency characteristics, and a small leakage current can be stably manufactured.

In the case of manufacturing a MOS transistor according to the present invention, the gate width can be made shorter than the opening formed by the lithography technique, and the LDD structure can be easily formed. A transistor can be manufactured.

Furthermore, in the present invention, the bipolar transistor and the MOS transistor having the above-described excellent characteristics can be manufactured in the same process, and the Bi-CMOS device can be easily manufactured.

[Brief description of the drawings]

1A to 1G are sectional views showing a first embodiment in which the present invention is applied to the manufacture of a bipolar transistor in the order of steps, and FIGS. 2A to 2D show the present invention in a Bi-CMOS. And FIG. 3 is a sectional view showing a conventional method for manufacturing a high-speed bipolar transistor. 1,21,51; silicon substrate, 2,52; buried collector layer, 3,53; epitaxial layer, 4,26,54; element isolation insulating film, 5,55; collector lead region, 6a, 56a; base lead Electrode, 6b, 56b; Collector extraction electrode, 7, 29; Silicon oxide film, 8, 17, 27, 28,
30,40; polycrystalline silicon film, 9,9a, 9b, 43,44,63; aperture, 1
0,58; graft base region, 11, 15, 37; silicon nitride film,
12,33; Coated silicon oxide film, 14; Base connection area, 16,3
9,59; base region, 18,41,62; emitter region, 19,42,64;
Contact hole, 22, 23; buried layer, 24, 25; well region, 31; p
⁺ -Type region, 32; n ⁺ -type region, 35; p-type region, 36; n-type region, 38;
Gate oxide film, 57; insulating film, 60; sidewall insulating film, 61; emitter electrode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ identification code FI H01L 27/092 29/73 29/78 (58) Investigated field (Int.Cl. ⁶ , DB name) H01L 21/33-21 / 331 H01L 29/68-29/737 H01L 21/336 H01L 29/76 H01L 29/772 H01L 29/78 H01L 27/06 H01L 27/08

Claims (1)

(57) [Claims] A step of selectively forming a second conductive type polycrystalline silicon film on the first conductive type semiconductor region; and a step of forming a first insulating film over the entire surface of the first conductive type semiconductor region. ,
Selectively forming a first opening reaching the first conductivity type semiconductor region from the surface of the first insulating film; and forming a second opening from the polycrystalline silicon film into the first conductivity type semiconductor region. Forming a first diffusion region by diffusing a conductive impurity, forming a second insulating film only on a side wall of the first opening, and forming a second insulating film on the first opening. 3) a step of embedding an insulating film, a step of forming a second opening by removing the second insulating film and exposing the first conductivity type semiconductor region, and a step of removing the second opening from the second opening. Introducing a second conductivity type impurity into the first conductivity type semiconductor region to form a second diffusion region having a lower impurity concentration than the first diffusion region; and forming a fourth diffusion region in the second opening portion. Forming a third opening by removing the third insulating film; and forming a third opening by removing the third insulating film. The method of manufacturing a semiconductor device, characterized in that it comprises a step of exposing the first conductive type semiconductor region.