JPS59208851A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve the density of integration by forming an insulating film on a side surface section isolating elements through the implantation of impurity ions and obtaining an isolation in an extremely narrow region. CONSTITUTION:A semiconductor substrate 1 is prepared, and an insulating film 13 consisting of SiO2 or Si3N4 obtained by combining O2 or N2 and Si is formed in predetermined depth by implanting impurity ions such as O2 or N2 to the whole surface on one main surface of the substrate and controlling the energy of the implantation. An impurity implantation control mask 2 is formed on the surface of a semiconductor substrate 1b. The impurity implantation control mask has an inclined section in its side surface, and impurity ions are implanted through the mask 2 to form insulating films 3a, 3b for isolating elements surrounding the bottoms and side surfaces of one semiconductor regions. Si gates 6, n<+> type sources-drains 10 and p<+> type sources-drains 8 are each shaped to the surfaces of each region in a self-alignment manner through selective diffusion.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to element isolation technology using an insulating film in a semiconductor integrated circuit device.

[Background technology]

10. In semiconductor integrated circuit devices called LSIs, it is necessary to electrically isolate multiple semiconductor elements formed on the surface of a semiconductor substrate, and isolation methods using pn junctions and insulating films are used as isolation means (isolation). A separation method is used.

However, in the case of isolation using a pn junction, since a mantissa region with a conductivity type different from that of the substrate is formed on a part of the surface of the semiconductor substrate, the area of the separation region increases due to lateral diffusion.
There are drawbacks such as the generation of parasitic transistor effects due to pn junction capacitance, and isolation using an insulating film makes it difficult to form an insulating film on the sides of the region where the element is formed. It has also been proposed to form an insulating film by semiconductor oxidation on the inner surface of the etched recess, but this method cannot avoid disadvantages such as a large number of steps and an increase in the area of the isolation region.

Particularly in the recent LSIs that require ultra-high integration, the separation technology available in the United States is no longer able to adequately meet the demands.

[Object of the Invention] An object of the present invention is to provide an element isolation technique using an insulating film that suppresses impurity ion implantation and is suitable for ultra-highly integrated LSI.

Outline of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

That is, it has a first semiconductor region whose bottom and side surfaces are surrounded by an insulating film on the entire surface of a semiconductor substrate, and a second semiconductor region which is in contact with the first semiconductor region through an insulating film on the side surfaces thereof, A semiconductor device in which semiconductor elements are formed electrically isolated from each other in these semiconductor regions, and an insulating film surrounding the bottom and side surfaces of the semiconductor regions is selected from the surface of the semiconductor substrate into the semiconductor substrate by ion implantation technology. The semiconductor nitride is made of a semiconductor nitride or a semiconductor nitride with impurities introduced into the semiconductor nitride, thereby making it possible to provide a semiconductor device with improved integration density.

〔Example〕

FIGS. 1 to 8 are cross-sectional views of a manufacturing process of an embodiment of a semiconductor device having one complementary MOSFET using the insulation isolation method according to the present invention. Each step will be explained in detail below.

(1) As shown in FIG. 1, a semiconductor substrate 1, for example, an n-type S
i. A crystal wafer is prepared, and an impurity implantation control mask 2 made of a 5-inch film formed by selective etching using photoresist (photoresist) or photoresist is formed on the surface of the crystal wafer. The side surfaces of this impurity implantation control mask 2 have an inclination angle θ<0<θ<90° with respect to a vertical plane on the substrate surface.

(2) Implanting impurity ions such as O7 or N2 into the Si substrate 1 through the impurity implantation control mask 2,
81 An insulating film 3 for element isolation is formed in the substrate 1 as shown in FIG. This insulating film is introduced into the substrate by ion implantation, and Si, which is a combination of N2 and 81, is introduced into the substrate by ion implantation.
n, Si, or N4, and is formed to surround the bottom and side surfaces of one semiconductor region.

FIG. 3 is an enlarged cross-sectional view showing the principle of forming a Si film inside Si by, for example, 02 ion implantation. In other words, mask 2 is formed on the surface of the Si substrate.
The O7 ion implanted from a place where there is no
) is introduced into the Si substrate, and Sl and O3 combine to form 5
An in2 film (thickness t, = 0.1 to 02 μm) 3a is formed. - 10,000, O driven into the side slope part 2a of the mask 2,
Ions are indicated by arrows 0. As shown in D, the implant energy is attenuated by the mask, and the area where the mask is thin (
0) reaches the deep part, and 02 reaches the shallow part in the thick part of the mask (D), respectively.A 5in2 film 3b (thickness t2'') follows the slope at the part corresponding to the slope of the mask side surface.
0.1 to 0.2 μm). Above 5
The thickness of the side surface portion 3b of the in2 film becomes thinner as the inclination angle of the mask side surface (angle θ with the vertical plane) is smaller, and becomes thicker as θ is larger (<90''') until θ reaches 90°. Then, the thickness of the side surface portion approaches the thickness of the bottom surface portion 3a.

(3) After this, with the ion implantation control mask 2 attached, an impurity that creates a conductivity type opposite to that of the n-type substrate,
For example, B (boron) impurities are ion-implanted to form a p-wall region in the semiconductor region surrounded by insulators 3a and 3b as shown in FIG.

(4) Next, the impurity implantation control mask 2 is removed and a thermally cured gate oxide film 5 is formed on the entire surface [2, Si is deposited thereon and then patterned with photoresist to form a poly-S1 gate oxide film as shown in FIG. - Form a toro.

(5) Cover the p-type semiconductor region 4 with a mask 7 made of photoresist or the like, and ion implant and diffuse B (boron) impurities for forming a p-type source/drain to the n-type substrate surface not covered with the mask 7. As shown in FIG. 6, p+ type source/drain regions 8 are formed. In this case, the source/drain diffusion regions are self-aligned (self-aligned) by the poly-Si gate 6.

(6) Remove the mask, cover the substrate surface other than the p-type region 4 with a new mask 9 as shown in FIG. 7, and implant ions such as As (arsenic) to form an n-type source/drain. An n''' type source/drain region 10 is formed on the surface of the p type region 4. In this case, the source/drain is self-aligned at its diffusion site by the poly 3i gate 6.

(7) As shown in Fig. 8, the entire surface is covered with an insulating film 11 such as PSG (phosphorus silicate glass), and after contact photoetching, AJ (aluminum) is evaporated and patterned to contact each area. AItKoku Q
Form 3S, G, D... As a result, the insulating film 3
An IO including an n-channel MO8FET and a p-channel MO8FET isolated from each other by a and 3b is completed.

FIGS. 9 to 11 are partial cross-sectional views of a manufacturing process of an embodiment of a semiconductor device having complementary MOSFETs using the insulation isolation method according to the present invention.

(1) As shown in FIG. 9, a semiconductor substrate 1 is prepared, and a 0.000.degree. Alternatively, by implanting impurity ions such as N7 and controlling the implantation energy, an insulating film 13 made of Sin, Si, or N4 in which 02 or N and 81 are combined is formed at a constant depth. Note that the semiconductor substrate 1 is entirely made of one and the same conductive layer (p-type or n-type).
8! It may be a Si crystal substrate, or it may be a p-type S! An n-type Si lb may be epitaxially grown on the substrate 1a, and in that case, the insulating film 13 made of Sin, Si, or N4 is formed within the n-type SiJ alloy lb or between the p-type Si substrate 1a and n. It is provided at the interface with the type Si layer 1b.

(2) An impurity implantation control mask 2 is formed on the surface of the semiconductor substrate (1b). This impurity implantation control mask has a sloped cross section on its side surface as shown in FIG. 10, and impurity ions are implanted through this mask 2. Membrane 3a.

3b is formed. The principle of production of this element isolation insulating film 3b is the same as that explained in the above embodiment (FIG. 3). In this example, an insulating film 3a formed on the bottom surface
By using the same ion implantation energy as in the process shown in FIG. 9, the insulating film 13 coincides with or overlaps with the insulating film 13. Subsequently, using the impurity implantation control mask 2, for example, B (boron) ions are implanted and diffused to form a p-type well 4 in a region surrounded by the insulating films 3a and 3b.

(3) After this, Si gates 6 are provided on the surface of each region by performing selective diffusion similar to the process shown in the above embodiment (FIGS. 4 to 7), and the p-type (well) region 4 is n+ type source/drain lO to n type region 1 bVc
P+ type source/drain 8 are formed in a self-aligned manner. Thereafter, although not shown, an insulating film such as PSG is formed on the surface, and electrodes and wiring are formed through the steps of contact photoetching, AA' vapor deposition, and patterning, to complete MO8IO with complete element isolation by the insulating film.

〔effect〕

The present invention described in accordance with the above embodiments has the following effects.

(1) Since the insulating film on the side surface that separates the elements is formed by implanting impurity ions, isolation can be obtained in an extremely narrow region.

(21 When the diffusion depth of MOSFET and bipolar transistor is shallow (for example, 0.1 to 0.5 μm),
2. Formation of the insulating film by N2 ion implantation is advantageous.

(3) By utilizing the sloped cross section of the side surface of the impurity ion implantation control mask and changing the slope angle, the thickness of the insulating film on the side surface for element isolation can be arbitrarily selected.

(4) Because it is possible to perform insulation separation in a narrow area,
It is possible to use places that were conventionally used as inactive areas such as fields as element areas.

The improvement in integration density has made it possible to reduce the dimensions of the element region including the isolation portion by the isolation insulating film to 15 to 2 μm.

(5) Mutual parasitic effects between elements, which was a problem with ICs with conventional MO8FETs, due to complete isolation by insulating films (
latch amplifier effect) can be completely prevented.

Hereinafter, the invention made by the present invention has been specifically explained based on Examples. However, the present invention is not limited to the above-mentioned Examples, and may be modified in various ways without departing from the gist thereof. Needless to say.

[Application field]

The present invention is effective when applied to bipolar MO8IO or ultra-highly integrated M and 08LSIs of 1 Molt or more, in addition to 10 including the MOSFETs described in the embodiments.

[Brief explanation of the drawing]

1 to 8 are cross-sectional views of main steps in a manufacturing process showing an embodiment of a semiconductor device using the insulation isolation method according to the present invention. 9 to 11 show other embodiments of a semiconductor device using the insulation isolation method according to the present invention, and are cross-sectional views of a part of the manufacturing process. 1.Semiconductor substrate-2. ... Impurity implantation control mask, 3 (3a-3b)... Insulating film for element isolation, 4...
p-type (well) region, 5... gate insulating film, 6...
Bo1 Si gate, 7...mask, 8...p
+ type north, drain, 9...mask, 10...n
Medium size sauce, 1・Rain, 11...? FIH(P
SG), 12-Aelit, 13... semiconductor substrate, 14... insulating film. Agent Patent Attorney Akio Takahashi 'Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 7 Figure 9 Figure 10 Figure 11

Claims (1)

[Claims] 1. A first semiconductor region whose bottom and side surfaces are surrounded by an insulating film on the entire surface of a semiconductor substrate, and a second semiconductor which is in contact with the first semiconductor region through an insulating film on its side surfaces. has a region,
A semiconductor device in which semiconductor elements are formed electrically isolated from each other in these semiconductor regions, wherein the insulating film is a semiconductor oxide bonded to impurities selectively introduced into the semiconductor substrate from the surface of the semiconductor substrate. Or a semiconductor device characterized by being made of semiconductor nitride. 2. When implanting impurity ions using the impurity ion implantation control film partially formed on the surface of the silicon semiconductor substrate as a mask to form an insulating film for element isolation made of semiconductor oxide or semiconductor nitride in the substrate, the above impurity 1. A method of manufacturing a semiconductor device, which comprises using an inclined cross section of a side surface of an ion implantation control mask to form an insulating film for element isolation having an insulator side surface that follows the inclined cross section.