JP2000164727A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress reduction in breakdown voltage of the junction between transistors and increase in junction leakage or off-leakage of the transistors, and to achieve the enhancement of the breakdown voltage of hot carriers with out increasing the number of makes. SOLUTION: Gate electrodes 7 are formed on a semiconductor substrate 1 via a first gate oxide film 5b and a second gate electrode 6. Then, a P-MOS region of a low-breakdown voltage transistor formation region and an N-MOS region of a high-breakdown voltage transistor formation region are covered with a resist mask 8 and boron ions are implanted rotatingly. Then, phosphorus ions are ion-implanted using the same mask 8. For this condition, the phosphorus ions are implanted in the substrate in an N-MOS region of the low-breakdown voltage transistor formation region, but the phosphorus ions are stopped in the thick gate oxide film 5b in a P-MOS region of the high-breakdown voltage transistor formation region and do not reach the substrate 1. Then, the N-MOS region of the low-breakdown voltage transistor formation region and the P-MOS region of the high-breakdown voltage transistor formation region are respectively covered with resist masks 11, and the phosphorus ions are implanted rotatingly.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a plurality of MOS transistors on the same semiconductor substrate.

[0002]

2. Description of the Related Art In recent years, with the high integration of LSI, a system-on-chip having various functions mounted on one chip has appeared. In such an LSI, a number of different types of circuit blocks are mounted, and the required characteristics of each are different. Therefore, in the case where a single type of transistor cannot be used, transistors are separately formed for each application. For example, in a portable device or the like, a peripheral circuit for low power consumption as well as high speed of an internal circuit is required. Further, even in connection with another chip having a high power supply voltage, a transistor having a high withstand voltage is required for the I / O block.

A technique for forming a plurality of transistors on the same chip is disclosed in Japanese Patent Application Laid-Open No. 9-266255.
A number of proposals have been made, describing a technique for forming a combination of a low breakdown voltage transistor and a high breakdown voltage transistor.

However, these techniques have a considerable number of additional steps in addition to the step of forming a single transistor, are specially adapted, and have the cost of a standard process required for a general system-on-chip. Compatibility is reduced. Therefore, there is a demand for a manufacturing method in which an increase in the number of steps is suppressed to a minimum. For example, there is JP-A-9-186224. These are two types of gate oxide films having different thicknesses prepared so as to correspond to different driving voltages. This is a minimal increase in the number of processes, which is quite desirable as a system-on-chip technology.

[0005] Here, JP-A-9-186244 will be described as a conventional technique with reference to FIG.

[0006] First, as shown in FIG.
N-type well regions 22 and 23 are formed in a P-type silicon substrate 21 by using a MOS process. Next, after selectively forming an oxide film 24 for element isolation, a gate oxide film 25 is formed to a thickness of about 12 nm on the silicon substrate 21 on the isolated element region. .

Next, the MOS constituting the cell and the peripheral circuit
When the gate insulating film 25 of the FET is selectively etched and removed to expose the silicon substrate 21, the result is as shown in FIG. 6B.

Thereafter, thermal oxidation is performed again to form a film having a thickness of about 12 on the exposed silicon substrate 21 of the cells and the peripheral circuits.
A gate oxide film 26 of nm in thickness is formed. At this time, the gate oxide film 25 of the input / output circuit grows on the gate oxide film 27 having a thickness of about 20 nm, as shown in FIG.

After that, the process is the same as in a normal CMOS process. After a polysilicon gate 28 is formed, ion implantation of impurities for forming N-type and P-type impurity regions is selectively performed using the polysilicon gate 28 as a mask. The source region 29a of the N-channel MOSFET,
A drain region 30a, a source region 29b and a drain region 30b of the P-channel MOSFET are formed (FIG. 6D).

[0010]

However, in the above-mentioned conventional method, the gate oxide film thickness of the high bias application transistor is merely increased, so that the withstand voltage of the gate oxide film can be prevented from deteriorating, but the hot carrier effect can be prevented. Is not enough. Furthermore, transistor off-leakage, junction leakage, and deterioration of junction breakdown voltage due to high bias application are inevitable, and application to low power consumption bias is difficult.

It is an object of the present invention to suppress a decrease in junction breakdown voltage, an increase in junction leak or an off-leak of a transistor, and to achieve an improvement in hot carrier breakdown voltage without increasing a mask.

[0012]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a first conductive type MOS transistor for a low withstand voltage; and a second conductive type MOS transistor for a high withstand voltage on the same semiconductor substrate. In the method of manufacturing a semiconductor device for forming a MOS transistor, the gate oxide film in the formation region of the high breakdown voltage second conductivity type MOS transistor is formed by forming the gate oxide film in the formation region of the low breakdown voltage first conductivity type MOS transistor. Forming a gate oxide film thicker than the thickness of the gate oxide film, and forming a gate electrode in the formation region of the high breakdown voltage second conductivity type MOS transistor and the formation region of the low breakdown voltage first conductivity type MOS transistor. And forming a halo layer in the formation region of the first-conductivity-type MOS transistor for low breakdown voltage and forming a halo layer in the formation region of the second-conductivity-type MOS transistor for high breakdown voltage. Ion-implanting a second conductivity type impurity into the semiconductor substrate to form a source / drain diffusion layer; and forming source / drain diffusion regions only in a formation region of the low breakdown voltage first conductivity type MOS transistor. In the formation region of the low breakdown voltage first conductivity type MOS transistor, the gate reaches the semiconductor substrate, and in the formation region of the high breakdown voltage second conductivity type MOS transistor, the gate is formed. Ion-implanting impurities of the first conductivity type so as to stop in the oxide film.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the present invention, wherein a low breakdown voltage first conductivity type MOS transistor and a high breakdown voltage second conductivity type MOS transistor are formed on the same semiconductor substrate.
In the method of manufacturing a semiconductor device for forming an S transistor, the gate oxide film in the formation region of the high breakdown voltage second conductivity type MOS transistor is formed in the formation region of the low breakdown voltage first conductivity type MOS transistor. Forming the gate oxide film thicker than the thickness of the gate oxide film; and forming a gate electrode in the formation region of the high-breakdown voltage second conductivity type MOS transistor and the formation region of the low breakdown voltage first conductivity type MOS transistor. Process and the MO of the first conductivity type for the low withstand voltage described above.
In order to form a halo layer of an S transistor and to form a low-concentration source / drain diffusion layer in a formation region of the high-withstand-voltage second conductivity type MOS transistor, a second conductivity type impurity is formed in the semiconductor substrate. And forming the low-concentration source / drain diffusion region only in the formation region of the low-withstand-voltage first-conductivity-type MOS transistor. MO
An impurity of the first conductivity type is implanted so as to reach the semiconductor substrate in the formation region of the S transistor and to stop in the gate oxide film in a formation region of the second conductivity type MOS transistor for high breakdown voltage. Forming a sidewall on the side wall of the gate electrode; forming a first photoresist in a formation region of the second-conductivity-type MOS transistor for high breakdown voltage; In order to form a high-concentration source / drain region in a formation region of a one-conductivity-type MOS transistor, a first-conductivity-type impurity is implanted using the gate electrode, the sidewall, and the first photoresist as a mask. And after removing the first photoresist, a second photoresist is formed in the formation region of the first conductive type MOS transistor for low breakdown voltage. Forming the gate electrode, the sidewalls, and the second photoresist in order to form a high-concentration source / drain region in the formation region of the high-withstand-voltage second conductivity type MOS transistor. And implanting a second conductivity type impurity using the mask as a mask.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the present invention, comprising a CMOS transistor comprising a first conductive type MOS transistor and a second conductive type MOS transistor for a low breakdown voltage on the same semiconductor substrate. And a first conductive type MOS transistor and a second conductive type M
In a method of manufacturing a semiconductor device for forming a CMOS transistor including an OS transistor, a gate oxide film in a formation region of the high breakdown voltage CMOS transistor is formed to have a thickness larger than a thickness of the gate oxide film in the formation region of the low breakdown voltage CMOS transistor. Forming a gate electrode in the high-breakdown-voltage CMOS transistor formation region and the low-breakdown-voltage CMOS transistor formation region; and forming the low-breakdown-voltage first conductivity type MOS transistor. In order to form a halo layer in a formation region and to form a source / drain diffusion layer in a formation region of the second MOS transistor for high breakdown voltage, a second conductivity type impurity is ion-implanted into the semiconductor substrate. And a source / drain only in the formation region of the low breakdown voltage first conductivity type MOS transistor. In order to form the in-diffusion region, the formation region of the low-breakdown-voltage first-conductivity-type MOS transistor reaches the semiconductor substrate, and the formation region of the high-breakdown-voltage second-conductivity-type MOS transistor. Then, a step of ion-implanting impurities of the first conductivity type so as to stop in the gate oxide film, a step of forming a halo layer in a formation region of the second conductivity type MOS transistor for low breakdown voltage, and a step of forming a high breakdown voltage Implanting one conductivity type impurity into the semiconductor substrate to form a source / drain diffusion layer in the formation region of the first conductivity type MOS transistor; Since the source / drain diffusion region is formed only in the MOS transistor formation region, the semiconductor substrate is formed in the low breakdown voltage second conductivity type MOS transistor formation region. As to reach,
And ion-implanting a second conductivity type impurity in the formation region of the high breakdown voltage first conductivity type MOS transistor so as to stop in the gate oxide film. .

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a CMOS transistor comprising a first conductive type MOS transistor and a second conductive type MOS transistor for low breakdown voltage on the same semiconductor substrate. And a first conductive type MOS transistor and a second conductive type M
In a method of manufacturing a semiconductor device for forming a CMOS transistor including an OS transistor, a gate oxide film in a formation region of the high breakdown voltage CMOS transistor is formed to have a thickness larger than a thickness of the gate oxide film in the formation region of the low breakdown voltage CMOS transistor. Forming a gate electrode in the high-breakdown-voltage CMOS transistor formation region and the low-breakdown-voltage CMOS transistor formation region; and forming the low-breakdown-voltage first conductivity type MOS transistor. In order to form a halo layer in a formation region and to form a source / drain diffusion layer in a formation region of the second MOS transistor for high breakdown voltage, a second conductivity type impurity is ion-implanted into the semiconductor substrate. And a source / drain only in the formation region of the low breakdown voltage first conductivity type MOS transistor. In order to form the in-diffusion region, the formation region of the low-breakdown-voltage first conductivity-type MOS transistor reaches the semiconductor substrate, and the formation region of the high-breakdown-voltage second conductivity-type MOS transistor. A step of ion-implanting an impurity of a first conductivity type so as to stop in the gate oxide film; a step of forming a sidewall on the side wall of the gate electrode; and a step of forming a second conductivity type MOS transistor for high breakdown voltage. Forming a first photoresist in the formation region and the low-breakdown-voltage second-conductivity-type MOS transistor formation region; and forming the low-breakdown-voltage first-conductivity-type MOS transistor formation region and the high-breakdown-voltage MOS transistor. In order to form a high-concentration source / drain region in a formation region of the first conductivity type MOS transistor, the gate electrode, the sidewall, and the gate are formed. And Torejisuto as a mask, implanting an impurity of the first conductivity type, after removing the first photoresist, the first for the low-voltage
The second region is formed in the formation region of the conductivity type MOS transistor and the formation region of the first conductivity type MOS transistor for high breakdown voltage.
Forming a photoresist, and forming high-concentration source / drain regions in the formation region of the second-conductivity-type MOS transistor for low breakdown voltage and the formation region of the second-conductivity-type MOS transistor for high breakdown voltage. And implanting a second conductivity type impurity using the gate electrode, the sidewalls, and the second photoresist as a mask.

Further, in the method of manufacturing a semiconductor device according to the present invention, only the gate oxide film in the gate electrode formation region of the low breakdown voltage MOS transistor is etched to form the high breakdown voltage MOS transistor. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the gate oxide film in the region is formed to be thicker than the gate oxide film in the region where the low breakdown voltage MOS transistor is formed. Is the way.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments.

FIGS. 1 to 4 are views showing the steps of manufacturing a semiconductor device according to one embodiment of the present invention, and FIG. 5 is a view showing the steps of manufacturing a semiconductor device according to another embodiment of the present invention.

First, an N-type well 2 is formed on a P-type silicon substrate 1 as shown in FIG. Here, the region A is a low breakdown voltage transistor formation region (a transistor having fineness and high speed), the region B is a high breakdown voltage transistor formation region (a transistor having a high breakdown voltage and low leakage characteristics), and reference numeral 3 denotes an element isolation. 1 shows an insulating film for use.

The method for forming the N well is not particularly limited, and the P well may be formed if necessary.
These are determined by the application device and the desired properties.

Next, as shown in FIG. 1B, a first gate oxide film 5a is formed at a temperature of 800 to 900 ° C. to a thickness of 10 to 15 nm, a high withstand voltage region is covered with a resist mask 4, and HF treatment is performed. Thereby, the surface of the silicon substrate 1 in the low breakdown voltage transistor formation region is exposed.

Next, as shown in FIG. 1C, the second gate oxide film 6 in the low breakdown voltage transistor formation region is
The film is formed at 900 ° C. at 5 to 10 nm. At this time, the thickness of the first gate oxide film 5b in the high breakdown voltage transistor formation region also increases at the same time. In this embodiment, the thickness of the gate oxide film 6 in the low breakdown voltage transistor formation region is 7 nm, and the thickness of the gate oxide film 5b in the high breakdown voltage transistor formation region is 20 nm.
And

Next, as shown in FIG. 2A, a gate electrode 7 is formed. In the present invention, after depositing 200 to 300 nm of phosphorus-doped polysilicon by a CVD method,
Patterning was performed by a known technique, but the material and method are not limited.

The gate length is 0.2 for a low breakdown voltage transistor.
~ 0.4 μm, 0.5 ~ 0.8 for high breakdown voltage transistor
μm.

Next, the PM of the low breakdown voltage transistor formation region is
The OS and the NMOS region of the high breakdown voltage transistor formation region are covered with a resist mask 8 and boron is applied at 40 to 60 keV, 5
The injection is performed 8 times with a tilt of 50 to 60 ° under the condition of 〜１０10 × 10 ¹¹ cm ⁻² . 9a and 9b are regions into which boron is implanted.

Next, as shown in FIG. 2B, using the same resist mask 8, phosphorus is applied at 10 to 30 keV,
Ions are implanted under the condition of 5 × 10 ¹³ cm ⁻² . Under this condition, phosphorus ions are implanted into the substrate in the low-breakdown-voltage NMOS region, but stop in the thick gate oxide film 5b and do not reach the silicon substrate 1 in the high-breakdown-voltage PMOS region. Reference numerals 10a and 10b are regions into which phosphorus has been implanted.

Next, as shown in FIG. 2C, the low-breakdown-voltage NMOS region and the high-breakdown-voltage PMOS region are covered with a resist mask 11, and phosphorus is applied at 120 to 170 keV and at 1 to 2 × 1.
Under the condition of 0 ¹² cm ^-2 , an inclination of 30 to 50 °
Spin injection. Reference numerals 12a and 12b are regions into which phosphorus has been implanted.

Next, as shown in FIG. 3A, using the same resist mask 11, boron is applied at 5 to 8 keV and 1 to 8 keV.
Ions are implanted under the condition of 5 × 10 ¹³ cm ⁻² . Under this condition, boron ions are implanted into the substrate in the low-breakdown-voltage PMOS region, but stop in the thick gate oxide film 5b and do not reach the silicon substrate 1 in the high-breakdown-voltage NMOS region.
Reference numerals 14a and 14b are regions into which phosphorus has been implanted.
In addition, boron implantation is performed using boron difluoride (B
F ₂ ) may be used. In that case, the implantation energy is suitably 20 to 30 keV.

Next, as shown in FIG. 3B, a CVD oxide film is deposited to a thickness of 80 to 120 nm and etched back to form a sidewall 15. Here HT
Although an O film was used, an NSG film may be used. Under this condition, the width of the sidewall 15 can be obtained at about 0.6 to 1.2 μm.

Next, as shown in FIG. 3C, the low-breakdown-voltage PMOS region and the high-breakdown-voltage PMOS region are covered with a resist mask 16, arsenic is 20 to 40 keV, and 2 to 5 × 10 ¹⁵
Ion implantation is performed under the condition of cm ⁻² . Symbols 17a, 17b
Is a region into which arsenic is implanted, and functions as a source / drain of an NMOS transistor.

Next, as shown in FIG.
The S region and the high withstand voltage NMOS region are covered with a resist mask 18, and boron difluoride (BF ₂ ) is
Ion implantation is performed under the condition of about 5 × 10 ¹⁵ cm ⁻² . Sign 1
9a and 19b are regions into which boron difluoride is implanted,
It works as the source / drain of the PMOS transistor.

Next, heat treatment for activation, for example, 800 to
By performing a heat treatment at 900 ° C. for 30 to 60 minutes, the source / drain regions are activated. Symbol 17a
Represents a high concentration n-type layer, 30 represents a low concentration p-type layer, and 31 represents a high concentration p-type layer.
The type layer 32 is a low-concentration p-type layer. Each of the low-concentration layers functions as a halo layer of a transistor in a low-breakdown-voltage CMOS section and as an LDD section of a transistor in a high-breakdown-voltage CMOS section.

Thereafter, in the actual manufacturing process, the process proceeds to the formation of the insulating film and the formation of the wiring, but is omitted because it is not a main part of the present invention.

Next, a second embodiment will be described.

The second embodiment is characterized in that, when the gate oxide film is formed separately in the first embodiment, only the gate region of the low breakdown voltage transistor forming region is thinned. That is, FIG. 1B of the first embodiment corresponds to FIG. 5, and the region C in FIG. 5 is a gate electrode formation region of the low breakdown voltage transistor.

In the case of the second embodiment, since the field region in the low breakdown voltage region is not etched, there is no reduction in film thickness and no reduction in field breakdown voltage. The other manufacturing steps are the same as in the first embodiment, and a description thereof will be omitted.

[0037]

As described in detail above, by using the present invention, whether or not to introduce impurities into the substrate by utilizing the difference in gate oxide film thickness is used. Only by using a mask, a plurality of transistors having different characteristics are formed on the same chip.

Further, according to the present invention, not only a plurality of power supply voltages can be used, but also a transistor capable of maximizing circuit performance even at the same voltage can be selectively formed.

Further, by using the invention described in claim 5, it is possible to prevent the insulating film for element isolation from being reduced.

[Brief description of the drawings]

FIG. 1 is a partial cross-sectional view of a manufacturing step of a semiconductor device according to an embodiment of the present invention;

FIG. 2 is a partial cross-sectional view of a manufacturing step of the semiconductor device according to the embodiment of the present invention;

FIG. 3 is a partial cross-sectional view of a manufacturing step of the semiconductor device according to the embodiment of the present invention;

FIG. 4 is a partial cross-sectional view of a manufacturing step of the semiconductor device according to the embodiment of the present invention;

FIG. 5 is a partial cross-sectional view of a manufacturing step of a semiconductor device according to another embodiment of the present invention;

FIG. 6 is a view showing a manufacturing process of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 P-type silicon substrate 1 2 N-type well 3 Element isolation insulating film 4, 8, 11, 13, 16 Resist mask 5a First gate oxide film 6 Second gate oxide film 65b First after thermal oxidation Gate oxide film 7 Gate electrode 9a, 9b Boron implanted region 10a, 10b Phosphorus implanted region 12a, 12b Phosphorus implanted region 14a, 14b Phosphorus implanted region 15 Side wall 17a, 17b Arsenic implanted Implanted regions 19a, 19b Boron 2 fluoride implanted regions 30 Low-concentration P-type layer 31 High-concentration p-type layer 32 Low-concentration p-type layer A Low-breakdown-voltage transistor formation region B High-breakdown-voltage transistor formation region C Low-breakdown-voltage transistor Gate electrode formation area

Claims (5)

[Claims] An MOS transistor of a first conductivity type for a low breakdown voltage and a MO transistor of a second conductivity type for a high breakdown voltage are formed on the same semiconductor substrate.
In the method for manufacturing a semiconductor device forming an S transistor, the gate oxide film in the formation region of the high breakdown voltage second conductivity type MOS transistor is formed by removing the low breakdown voltage first conductivity type M transistor.
Forming a gate oxide film thicker than the thickness of the gate oxide film in the formation region of the OS transistor; and forming the second conductivity type MOS transistor for high breakdown voltage and the formation region of the first conductivity type MOS transistor for low breakdown voltage. Forming a gate electrode; forming a halo layer in a formation region of the low breakdown voltage first conductivity type MOS transistor;
A step of ion-implanting a second conductivity type impurity into the semiconductor substrate to form a source / drain diffusion layer in a formation region of the conductivity type MOS transistor; In order to form the source / drain diffusion region only in the formation region, the formation region of the low breakdown voltage first conductivity type MOS transistor reaches the semiconductor substrate and the high breakdown voltage second conductivity type. Implanting an impurity of the first conductivity type so as to stop in the gate oxide film in the region where the MOS transistor is formed. 2. A low-voltage first-conductivity-type MOS transistor and a high-voltage second-conductivity-type MOS transistor on the same semiconductor substrate.
In a method of manufacturing a semiconductor device for forming an OS transistor, a gate oxide film in a formation region of the high breakdown voltage second conductivity type MOS transistor is formed by removing the gate oxide film of the low breakdown voltage first conductivity type M transistor.
A step of forming a gate oxide film thicker than a thickness of a gate oxide film in a formation region of an OS transistor; a formation region of a second conductivity type MOS transistor for high breakdown voltage; and a formation region of a first conductivity type MOS transistor for low breakdown voltage. Forming a halo layer of the low-breakdown-voltage first-conductivity-type MOS transistor, and forming the high-breakdown-voltage second-conductivity-type M transistor.
Ion-implanting a second conductivity type impurity into the semiconductor substrate to form a low-concentration source / drain diffusion layer in a formation region of the OS transistor; In order to form the low-concentration source / drain diffusion region only in the formation region, the low-breakdown-voltage first-conductivity-type MOS transistor formation region reaches the semiconductor substrate and the high-breakdown-voltage source / drain diffusion region. Implanting an impurity of the first conductivity type in the formation region of the second conductivity type MOS transistor so as to stop in the gate oxide film; forming a sidewall on the side wall of the gate electrode; Forming a first photoresist in a region where a second-conductivity-type MOS transistor for use is formed; Implanting a first conductivity type impurity using the gate electrode, the sidewall, and the first photoresist as a mask to form a high concentration source / drain region in the formation region; Forming a second photoresist in the formation region of the low breakdown voltage first conductivity type MOS transistor after removing the photoresist, and forming the second breakdown region of the high breakdown voltage second conductivity type MOS transistor. Implanting a second conductivity type impurity using the gate electrode, the sidewalls, and the second photoresist as a mask to form a high-concentration source / drain region. To manufacture a semiconductor device. 3. A CMOS transistor comprising a first conductive type MOS transistor and a second conductive type MOS transistor for a low withstand voltage and a first conductive type MOS transistor for a high withstand voltage on the same semiconductor substrate. M of two conductivity type
In a method of manufacturing a semiconductor device for forming a CMOS transistor including an OS transistor, the gate oxide film in the formation region of the high-breakdown-voltage CMOS transistor is made thicker than the gate oxide film in the formation region of the low-breakdown-voltage CMOS transistor. Forming a gate electrode in the formation region of the high-breakdown-voltage CMOS transistor and the formation region of the low-breakdown-voltage CMOS transistor; The second step for forming the halo layer in the formation region and the second step for the high withstand voltage is performed.
A step of ion-implanting a second conductivity type impurity into the semiconductor substrate to form a source / drain diffusion layer in a formation region of the conductivity type MOS transistor; In order to form the source / drain diffusion region only in the formation region, the formation region of the low breakdown voltage first conductivity type MOS transistor reaches the semiconductor substrate and the high breakdown voltage second conductivity type. A step of ion-implanting impurities of the first conductivity type so as to stop in the gate oxide film in the formation region of the MOS transistor, and forming a halo layer in the formation region of the low breakdown voltage second conductivity type MOS transistor. And the first for the high withstand voltage
A step of ion-implanting one conductivity type impurity into the semiconductor substrate to form a source / drain diffusion layer in a formation region of the conductivity type MOS transistor; and forming the second conductivity type MOS transistor for low breakdown voltage. In order to form the source / drain diffusion region only in the region, the formation region of the low breakdown voltage second conductivity type MOS transistor reaches the semiconductor substrate and the high breakdown voltage first conductivity type MOS transistor. Implanting an impurity of the second conductivity type so that the impurity remains in the gate oxide film in the region where the MOS transistor is formed. 4. A CMOS transistor comprising a first conductive type MOS transistor and a second conductive type MOS transistor for a low withstand voltage and a first conductive type MOS transistor for a high withstand voltage on the same semiconductor substrate. M of two conductivity type
In a method of manufacturing a semiconductor device for forming a CMOS transistor including an OS transistor, the gate oxide film in the formation region of the high-breakdown-voltage CMOS transistor is made thicker than the gate oxide film in the formation region of the low-breakdown-voltage CMOS transistor. Forming a gate electrode in the formation region of the high-breakdown-voltage CMOS transistor and the formation region of the low-breakdown-voltage CMOS transistor; The second step for forming the halo layer in the formation region and the second step for the high withstand voltage is performed.
A step of ion-implanting a second conductivity type impurity into the semiconductor substrate to form a source / drain diffusion layer in a formation region of the conductivity type MOS transistor; In order to form the source / drain diffusion region only in the formation region, the formation region of the low breakdown voltage first conductivity type MOS transistor reaches the semiconductor substrate and the high breakdown voltage second conductivity type. A step of ion-implanting an impurity of the first conductivity type so as to stop in the gate oxide film in a region where the MOS transistor is formed; a step of forming a sidewall on the side wall of the gate electrode; Forming a first photoresist in a formation region of a conductivity type MOS transistor and a formation region of the second conductivity type MOS transistor for low breakdown voltage; The gate electrode is formed to form high-concentration source / drain regions in the formation region of the low-breakdown-voltage first conductivity type MOS transistor and the formation region of the high-breakdown-voltage first conductivity type MOS transistor. Implanting impurities of a first conductivity type using the side walls and the photoresist as a mask; and forming a region for forming the low breakdown voltage first conductivity type MOS transistor after removing the first photoresist. Forming a second photoresist in the formation region of the high breakdown voltage first conductivity type MOS transistor; and forming the low breakdown voltage second conductivity type MOS transistor formation region and the high breakdown voltage second conductivity type. In order to form a high-concentration source / drain region in the formation region of the MOS transistor of the type, the gate electrode, the sidewall, and the second photo A resist as a mask, characterized by a step of implanting an impurity of the second conductivity type, a method of manufacturing a semiconductor device. 5. The method according to claim 5, wherein only the gate oxide film in the gate electrode formation region of the low breakdown voltage MOS transistor is etched, so that the gate oxide film in the formation region of the high breakdown voltage MOS transistor is formed. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the thickness of the gate oxide film in the region is larger than that of the region.