JP3778810B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which a threshold voltage is well controlled and a manufacturing method thereof.
[0002]
[Prior art and problems to be solved by the invention]
Conventionally, an LSI excellent in low power consumption has been realized by a CMOS transistor in which an NMOS transistor and a PMOS transistor are mixedly mounted on the same semiconductor substrate.
[0003]
However, due to the recent miniaturization and higher integration of CMOS transistors, there is a problem of a short channel effect in which the threshold voltage decreases as the gate length of the transistors constituting the CMOS transistor becomes shorter. In particular, in the NMOS transistor, as shown by white circles in FIG. 10, the threshold voltage is temporarily increased as the channel length is shortened by introducing boron, which is a p-type impurity, into the channel region by the channel doping method. The problem is that the reverse short channel effect occurs.
[0004]
Usually, when forming an NMOS transistor, boron ions are introduced as a p-type impurity in advance in order to adjust the threshold voltage in the channel region, and then a gate electrode or the like is formed to form an LDD region or source / drain. 1 × 10 for area formation¹⁴~ 1x10¹⁵cm^-2About n-type impurities are ion-implanted into the semiconductor substrate, and then heat treatment is performed to activate the impurities.
[0005]
However, the crystal structure of the semiconductor substrate is destroyed by the ion implantation for forming the LDD region and the source / drain region, and a large number of point defects are generated. The boron ions present in the crystal pair with point defects, and so-called "accelerated diffusion" occurs, and the boron concentration becomes extremely high at both ends of the channel region (boron ion pile-up).
[0006]
Therefore, in the NMOS transistor, the boron concentration in the channel region tends to increase as the channel length becomes shorter, and the threshold voltage increases more rapidly than the designed value (CS Rafferty et al. “Explanation of Reverse Short Channel Effect by Defect Gradients”). , IEDM93, p311-314).
[0007]
When the reverse short channel effect in such an NMOS transistor becomes significant, the threshold voltage largely fluctuates due to a slight gate length variation, and the controllability of the threshold voltage deteriorates.
[0008]
Therefore, a method for manufacturing a CMOS transistor in which the reverse short channel effect is suppressed has been proposed in, for example, Japanese Patent Application Laid-Open Nos. 8-18047 and 8-78682.
[0009]
According to these methods, as shown in FIG. 14, in the NMOS and PMOS transistor formation regions 27 and 28, after performing impurity ion implantation and activation annealing for forming the source / drain regions 31 and 32, In the NMOS transistor formation region 27, boron ions are introduced into the channel region by the implantation energy penetrating the gate electrode 33 (see 29 in FIG. 14). As a result, point defects generated at the time of ion implantation for forming the source / drain regions 31 and 32 can be reduced, and accelerated diffusion is prevented.
[0010]
However, when boron ions are implanted into the channel region in both the NMOS and PMOS transistor formation regions 27 and 28, the PMOS transistor is attributed to the boron ions implanted into the PMOS transistor formation region 28. Not only lowers the punch-through breakdown voltage, but also forms a new junction under the source / drain region 32, resulting in a problem that the substrate potential cannot be maintained properly.
[0011]
In order to avoid such a problem, as shown in FIG. 15, after covering the PMOS transistor formation region 28 with a resist mask 30, boron ions are implanted only into the channel region of the NMOS transistor formation region 27 (FIG. 15). 15 (see 29, 15)), there arises a problem that the number of photolithography steps for covering the PMOS transistor formation region 28 increases.
[0012]
The present invention has been made in view of the above problems, and in the CMOS transistor, without adding a photolithography step, further prevents the accelerated diffusion of boron ions and suppresses the reverse short channel effect of the NMOS transistor, At the same time, an object of the present invention is to provide a semiconductor device which can control the threshold value of the PMOS transistor to a desired value and prevent the punch-through breakdown voltage from deteriorating and maintain the PMOS transistor characteristics appropriately, and a method for manufacturing the same.
[0014]
[Means for Solving the Problems]
  According to the present invention, (a) forming a p-well and an n-well, a gate insulating film and a gate electrode in NMOS and PMOS transistor formation regions on a silicon semiconductor substrate,
(B) In the NMOS and PMOS transistor formation regions, n-type impurities andAnd BF₂ ⁺Ion source and heat treatment to form source / drain regions,
(C) Boron ions or BF penetrating through the gate electrode all over the silicon semiconductor substrate₂ ⁺TheThe implantation peak depth is in the range from the lower half of the gate electrode to the upper half of the depth of the source / drain region, and immediately below the boundary between the source / drain region and the well.Ion implantation and heat treatment are performed to form a band-shaped boron ion or BF having a constant width in the depth direction in the channel region immediately below the gate electrode.₂ ⁺Forming a high-concentration region in this order so as to overlap the channel region in part or all of the width in the depth direction,
  Immediately before or immediately after the formation of the n-well in step (a), using the n-well formation mask, boron ions or BF implanted in the step (c) into the channel region immediately below the gate electrode of the PMOS transistor.₂ ⁺A method for manufacturing a semiconductor device is provided, wherein an n-type impurity in an amount exceeding the concentration is introduced.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
The semiconductor device of the present invention is a CMOS transistor configured by forming an NMOS transistor and a PMOS transistor on a p-well and an n-well formed on the surface of a semiconductor substrate.
[0016]
As the semiconductor substrate used in the semiconductor device of the present invention, various substrates such as elemental semiconductor substrates such as silicon and germanium, substrates made of compound semiconductors such as GaAs and InGaAs, SOI substrates, and multilayer SOI substrates can be used. . Of these, a silicon substrate is preferable. The semiconductor substrate has a semiconductor element or circuit such as a transistor or a capacitor on its surface; a wiring layer; an element isolation region such as a LOCOS film, a trench element isolation film, or an STI (Shallow Trench Isolation) film; an insulating film or the like. It may be formed.
[0017]
It is sufficient that at least one p well and n well are formed on the surface of the semiconductor substrate. The impurity concentration of these wells is not particularly limited.¹⁷-10¹⁸cm^-3Degree.
[0018]
An NMOS transistor and a PMOS transistor are formed on the p well and the n well, respectively. These transistors have a gate insulating film, a gate electrode, a channel region, and a source / drain region. The gate insulating film, the gate electrode, and the source / drain region here can be any material, film thickness, shape, and size as long as they can constitute an NMOS transistor or a PMOS transistor as used in a normal CMOS transistor. The impurity concentration is not particularly limited. For example, the gate insulating film is suitably formed of a silicon oxide film, and the film thickness is about 1 to 10 nm. The gate electrode is suitably formed of polysilicon, and the film thickness is about 70 to 500 nm. The source / drain region has an impurity concentration of, for example, 10¹⁸-10²⁰cm^-3Degree. Note that sidewall spacers may be formed on the sidewalls of the gate electrodes by insulating films. Further, the source / drain region may include an LDD region on the channel region side.
[0019]
In both the NMOS and PMOS transistors, the channel region contains a region containing p-type impurities at a higher concentration than the p-type impurity in the p-well, that is, the p-type high-concentration impurity region has a certain width in the depth direction. It arrange | positions in the strip | belt shape which has. Here, the channel region includes not only a region that is normally inverted when the transistor is turned on, but also a region in a range in which the threshold voltage can generally be controlled by channel implantation. For example, the channel region has a width of about 30 nm from the surface of the semiconductor substrate under the gate insulating film.
[0020]
The p-type high-concentration impurity region differs depending on the characteristics, size, etc. of the CMOS to be obtained, but is preferably arranged in the channel region with a width of at least about 20 nm. However, if the entire width in the depth direction of the p-type high-concentration impurity region is greater than this, the entire region in the depth direction may overlap the channel region. The portion may extend into the gate insulating film or the gate electrode. The total width in the depth direction of the p-type high concentration impurity region is suitably about 50 to 100 nm. The p-type impurity concentration contained in the p-type high-concentration impurity region can be appropriately adjusted depending on the operating voltage, threshold value, etc. of the NMOS transistor to be obtained.¹⁷-10¹⁸cm^-3Degree. Here, the p-type high concentration impurity region means a width including ions of about 50% of the total implantation amount centering on one implantation peak of the p-type impurity. For example, according to the Gaussian distribution function, 50% of all ions are present within a range from the peak one to 0.675 times ΔRp on one side. Since ΔRp varies depending on the impurity implantation energy and the like, for example, in boron, ΔRp = 40 nm and the width are 54 nm at 40 keV, and ΔRp = 60 nm and the width are 81 nm at 70 keV.
[0021]
In the channel region of the PMOS transistor, even if the p-type high concentration impurity region is arranged similarly to the channel region of the NMOS transistor, the n-type impurity is contained in an amount exceeding the p-type impurity concentration. As a result, n-type conductivity is shown. Here, the n-type impurity has a concentration after being offset by the p-type impurity in the p-type high-concentration impurity region.¹⁷-10¹⁸cm^-3Degree.
[0022]
Further, the p-type high concentration impurity region may be arranged not only in the channel region of the NMOS and PMOS transistors but also in a region including the boundary between the source / drain region and the well. Further, when the LDD region is formed, the LDD region may be arranged in a part of the LDD region or in a region including the boundary between the LDD region and the well.
[0023]
In the method for manufacturing a semiconductor device of the present invention, first, in step (a), a p-well and an n-well, a gate insulating film, and a gate electrode are formed in NMOS and PMOS transistor formation regions on a semiconductor substrate, respectively. For the p-well and n-well, a resist mask having an opening on each region is formed by a known method, for example, photolithography and etching, and p-type or n-type impurities are ion-implanted using the resist mask. Can be formed. Further, the gate insulating film and the gate electrode can be formed by forming and patterning by a method known in the art.
[0024]
In particular, in the PMOS transistor formation region, a resist mask used for forming the n well is used on the surface of the semiconductor substrate after or before ion implantation of an n-type impurity for forming the n well. It is preferable to introduce an n-type impurity in an amount exceeding the p-type impurity concentration introduced into the p-type high concentration impurity region. The ion implantation in this case can be appropriately adjusted depending on, for example, the characteristics of the CMOS to be obtained, the operating voltage, the size, the impurity concentration of the p-type high-concentration impurity region, etc. 10¹³cm^-2About a dose, about 120 keV acceleration energy.
[0025]
In the case of forming the LDD region, after forming the gate electrode and before the step (b), the LDD region is formed by ion implantation of p-type or n-type impurities using the gate electrode as a mask. After that, an insulating film is preferably formed on the entire surface of the semiconductor substrate including the gate electrode, and etched back to form sidewall spacers on the side walls of the gate electrode. The ion implantation for forming the LDD region is, for example, acceleration energy of about 5 to 20 keV for arsenic ions, 1 × 10¹⁴-10¹⁵cm^-2Degree dose or BF₂ ⁺Acceleration energy of about 5 to 20 keV, 1 × 10¹⁴-10¹⁵cm^-2It can be performed at a moderate dose.
[0026]
Next, in step (b), n-type or p-type impurities are ion-implanted into the NMOS and PMOS transistor formation regions using the gate electrode (or gate electrode and sidewall spacer) as a mask, and heat treatment is performed to form source / drain regions. Form each one. The ion implantation conditions here are not particularly limited. For example, arsenic ions are accelerated at an energy of about 30 to 50 keV and 5 × 10 5.¹⁴~ 5x10¹⁵cm^-2Degree dose or BF₂ ⁺Acceleration energy of about 10 to 50 keV, 5 × 10¹⁴~ 5x10¹⁵cm^-2About a dose. The heat treatment can be performed by various methods such as lamp annealing, furnace annealing, and RTA method. For example, a temperature range of about 1000 to 1100 ° C. and about 5 to 20 seconds may be mentioned by lamp annealing.
[0027]
In the step (c), a p-type impurity is ion-implanted through the gate electrode over the entire surface of the semiconductor substrate, heat treatment is performed, and a band-shaped p-type high concentration with a constant width in the depth direction is formed in the channel region immediately below the gate electrode. The impurity regions are formed so that part or all of them are arranged. The ion implantation here can be adjusted as appropriate depending on the film thickness of the gate electrode, the depth of the source / drain region, the ion species, and the like. Can be set to be within the upper half of the depth of the / drain region, preferably set to be near the boundary between the gate insulating film and the surface of the channel region, It is preferably set so that it is close to the boundary with the well, and more preferably set so that it is immediately below the boundary between the source / drain region and the well. Specifically, boron ions or BF₂ ⁺Acceleration energy of about 50 to 90 keV, 1 × 10¹²-10¹³cm^-2It is possible to implant ions with a moderate dose. From another viewpoint, the implantation peak depth of ion implantation can be set to about 100 to 300 nm in consideration of the film thickness of the gate insulating film and the gate electrode, the impurity concentration of the source / drain regions, and the like. . Moreover, heat processing can be performed by the method similar to the above. By performing such ion implantation and heat treatment, a part or all of the p-type high concentration impurity region can be finally arranged in the channel region.
[0028]
In the method for manufacturing a semiconductor device of the present invention, after the above-described series of steps, the semiconductor further includes the formation of an interlayer insulating film, the formation of contact holes, the formation of a wiring layer, and the cleaning of the surface of the semiconductor substrate or the surface of the obtained semiconductor substrate. The semiconductor device of the present invention can be completed by arbitrarily combining the steps in the process.
[0029]
Hereinafter, a semiconductor device and a manufacturing method thereof according to the present invention will be described in detail with reference to the drawings.
[0030]
As shown in FIG. 1, the CMOS transistor 37 which is a semiconductor device in this embodiment includes an NMOS transistor 2 and a PMOS transistor 3 formed on a silicon substrate 4 having an element isolation insulating film 1.
[0031]
In the NMOS transistor 2, a gate electrode 10 is formed on a p-well 5 formed on the surface of a silicon substrate 4 via a gate insulating film 9, and a side wall spacer 13 is formed on the side wall of the gate electrode 10. . An LDD region 11 is formed adjacent to the channel region 7 and immediately below the sidewall spacer 13, and a source / drain region 14 is formed adjacent to the LDD region 11. The channel region 7 has a certain width (for example, about 80 nm) in the depth direction, and 10¹⁷-10¹⁸cm^-3A band-shaped p-type high concentration impurity region 16 containing a certain amount of boron ions is formed.
[0032]
As shown in FIG. 2, the p-type high concentration impurity region 16 may be disposed in the gate insulating film 9 or the gate electrode 10 as long as a part thereof is disposed in the channel region 7. Good.
[0033]
The threshold voltage of the NMOS transistor 2 can be controlled by adjusting the impurity concentration of the p-type high concentration impurity region 16.
[0034]
In the PMOS transistor 3, a gate insulating film 9, a gate electrode 10, and a sidewall spacer 13 are formed on an n well 6 formed on the surface of the silicon substrate 4, adjacent to the channel region 8. Thus, the LDD region 12 and the source / drain region 15 are formed. Further, a p-type high concentration impurity region 16 is formed in the channel region 8 as in the NMOS transistor 2.
[0035]
In the channel region 8 of the PMOS transistor 3, arsenic ions are 10¹⁷-10¹⁸cm^-3Since it is introduced at a certain concentration, the conductivity type of the p-type high concentration impurity 16 is offset. In the source / drain region 15 of the PMOS transistor 3, the p-type high concentration impurity region 16 is located immediately below the source / drain region 15. Since no new junction is formed under the substrate 15, the substrate potential can be kept appropriate.
[0036]
Such a semiconductor device can be formed by the following method.
[0037]
First, as shown in FIG. 3A, the element isolation insulating film 1 is formed on the p-type silicon substrate 4 and separated into the NMOS transistor formation region 17 and the PMOS transistor formation region 18. Next, a silicon oxide film 19 is formed as an implantation protection film on the entire surface of the silicon substrate 4.
[0038]
Thereafter, as shown in FIG. 3B, a resist mask 20 covering the PMOS transistor formation region 18 is formed, and boron ions are implanted as p-type impurities into the NMOS transistor formation region 17 to form the p well 5. .
[0039]
Similarly, as shown in FIG. 4C, phosphorus ions are implanted as n-type impurities into the PMOS transistor formation region 18 to form the n-well 6.
[0040]
Then, arsenic ions are¹³cm^-2The channel region 8 is formed by implantation at a moderate dose.
[0041]
Subsequently, after the silicon oxide film 19 is wet etched, as shown in FIG. 4D, the gate insulating film 9 having a thickness of about 3.4 nm and the polysilicon film 22 having a thickness of about 150 nm are formed on the entire surface of the silicon substrate 4. Form.
[0042]
Next, as shown in FIG. 5E, the gate electrode 10 is formed by patterning the gate insulating film 9 and the polysilicon film 22.
[0043]
After that, as shown in FIG. 5F, a resist mask 23 covering the PMOS transistor formation region 18 is formed, and arsenic ions as n-type impurities are converted into an NMOS transistor formation region 17 with an acceleration energy of 10 keV, 5 × 10 5.¹⁴cm^-2Then, the LDD region 11 is formed on the surface of the silicon substrate 4.
[0044]
Subsequently, as shown in FIG. 6G, a resist mask 24 covering the NMOS transistor formation region 17 is formed, and BF as a p-type impurity is formed in the PMOS transistor formation region 18.₂ ⁺10 keV acceleration energy, 1.2 × 10¹⁴cm^-2Then, the LDD region 12 is formed on the surface of the silicon substrate 4.
[0045]
Next, a silicon nitride film is formed on the entire surface of the silicon substrate 4 and etched back to form side wall spacers 13 on the side walls of the gate electrode 10 as shown in FIG.
[0046]
Thereafter, as shown in FIG. 7 (i), a resist mask 25 covering the PMOS transistor formation region 18 is formed, and arsenic ions as n-type impurities are formed in the NMOS transistor formation region 17 with an acceleration energy of 50 keV and 3 × 10 3.¹⁵cm^-2The source / drain regions 14 are formed on the surface of the silicon substrate 4.
[0047]
Similarly, as shown in FIG. 7J, a resist mask 26 covering the NMOS transistor formation region 17 is formed, and BF as a p-type impurity is formed in the PMOS transistor formation region 18.₂ ⁺With an acceleration energy of 30 keV, 2 × 10¹⁵cm^-2Then, source / drain regions 15 are formed on the surface of the silicon substrate 4. At this stage, the source / drain regions 14 and 15 are still electrically inactive, and there are a number of point defects in the vicinity thereof.
[0048]
Next, activation annealing is performed by, for example, lamp heating at 1050 ° C. for 10 seconds. As a result, the source / drain regions 14 and 15 are activated and the point defects disappear.
[0049]
Subsequently, as shown in FIG. 8 (k), boron ions are converted into acceleration energy of 70 keV, 10¹²-10¹³cm^-2The p-type high-concentration impurity region 16 is formed by implanting ions into the entire surface of the silicon substrate 4 through the gate electrode with a moderate dose. At this time, the peak depth of the ion implantation in the region where the gate electrode 10 is formed is set to be within a range of half the depth of the source / drain regions 14 and 15 from below the gate electrode 10, and is p-type. All or part of the high concentration impurity region 16 in the depth direction is set in the channel regions 7 and 8. Note that the peak depth of ion implantation in the source / drain regions 14 and 15 is set to be immediately below the source / drain regions 14 and 15. That is, the peak depth of ion implantation is adjusted according to the thickness of the gate electrode and the depth of the source / drain region.
[0050]
Thereafter, similarly to the above, activation annealing is performed again to activate the p-type high concentration impurity region 16. At this time, since point defects have already disappeared by the first heat treatment, accelerated diffusion of boron ions does not occur.
[0051]
As shown in FIG. 9, in the NMOS transistor in the CMOS transistor created by the semiconductor device manufacturing method as described above, the boron ion distribution in the depth direction in the region where the gate electrode 10 is formed is the conventional method. As can be seen, there is no rapid increase in the boron concentration on the substrate surface, indicating that no accelerated diffusion has occurred.
[0052]
FIG. 10 shows the threshold voltage fluctuation amount (degree of reverse channel effect) of such an NMOS transistor. In such an NMOS transistor, no accelerated diffusion occurs, so that even when the channel length is short as in the conventional method, the threshold is not increased, and the reverse short channel effect is sufficiently suppressed. I understand.
[0053]
Further, FIG. 11 shows the gate dependence of the punch-through breakdown voltage in the PMOS transistor in the CMOS transistor produced by the semiconductor device manufacturing method as described above. Here, the punch-through breakdown voltage is defined as a drain voltage when a gate voltage is 0 V (Vgs = Vbs = Vs = 0 V) and a drain current Id of 1 μA flows. In this embodiment, 1.8 V is used as the power supply voltage.
[0054]
According to FIG. 11, such a PMOS transistor does not show any deterioration in breakdown voltage even when compared with the conventional method.
[0055]
FIG. 12 shows the substrate bias voltage dependence of the threshold voltage of such a PMOS transistor. The substrate bias voltage dependency here is defined by the amount of change in the triode threshold voltage when the substrate voltage is varied. Vgs = 0.05V, Vs = 0V, Vbs are varied, and Vg at GMMax. The threshold voltage was read by extrapolation of the tangent line of the -Id curve.
[0056]
According to FIG. 12, such a PMOS transistor has no difference even when compared with the conventional method.
[0057]
FIG. 13 shows the junction diode characteristics of the NMOS and PMOS transistors in the CMOS transistor produced by the semiconductor device manufacturing method as described above. The junction diode characteristics here are IV characteristics when a reverse bias is applied in the PN junction, and the upper limit of the current amount (leakage current amount) at the operating voltage (1.8 V) and the upper limit to the intrinsic breakdown voltage. Is provided. The substrate potential Vbs was fixed at 0 V, and a reverse bias of 0 to 10 V was applied to the source / drain regions to obtain an IV curve.
[0058]
According to FIG. 13, an appropriate breakdown voltage is obtained in any transistor. Even if boron ions for controlling the threshold value of the NMOS transistor are implanted entirely through the gate electrode without masking the PMOS transistor region as in the conventional method, it is appropriate for the PMOS transistor by adjusting the implantation peak depth. Special characteristics can be obtained.
[0059]
【The invention's effect】
According to the present invention, a band-shaped p-type high concentration impurity region having a constant width in the depth direction is disposed in the channel regions of the NMOS and PMOS transistors, and the p-type is disposed in the channel region of the PMOS transistor. Since there is an n-type impurity in an amount exceeding the p-type impurity concentration in the high-concentration impurity region, the threshold shift due to the reverse short channel effect of the NMOS transistor can be prevented while minimizing the photolithography process, and In the PMOS transistor, a good punch-through breakdown voltage can be maintained.
[0060]
In the case where p-type high-concentration impurity regions are arranged in the region including the boundary between the source / drain region of the NMOS transistor and the p-well and the region including the boundary between the source / drain region of the PMOS transistor and the n-well, respectively. In particular, the well potential can be appropriately controlled without forming a new junction below the source / drain region in the PMOS transistor.
[0061]
Further, according to the present invention, after ion implantation for forming the source / drain regions, heat treatment for activation is performed, and then the p-type impurities are ionized through the gate electrode over the entire surface of the semiconductor substrate. Since the heat treatment is performed by implantation, the shift of the threshold due to the reverse short channel effect due to the enhanced diffusion in the NMOS transistor can be effectively prevented by a simple method without adding a photolithography process. Therefore, the manufacturing cost can be reduced and the deterioration of the characteristics of the CMOS transistor can be prevented, thereby improving the yield.
[0062]
In particular, the implantation peak depth in the ion implantation in the step (c) is in the range from the lower half of the gate electrode to the upper half of the depth of the source / drain region, and immediately below the boundary between the source / drain region and the well. Therefore, it is possible to avoid the formation of a new PN junction in the PMOS transistor, to easily control the well potential, and to avoid the deterioration of the punch-through breakdown voltage. be able to.
[0063]
Also, when an n-type impurity in an amount exceeding the p-type impurity concentration introduced into the p-type high-concentration impurity region is introduced into the surface of the semiconductor substrate immediately before or immediately after the n-well formation in the step (a), The p-type impurity having a concentration can be surely offset, and the threshold voltage of the PMOS transistor can be easily controlled.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view of a main part of a semiconductor device of the present invention.
FIG. 2 is a schematic cross-sectional view of a main part of another semiconductor device of the present invention.
FIG. 3 is a schematic cross-sectional process diagram of the main part for explaining the method of manufacturing a semiconductor device of the invention.
FIG. 4 is a schematic cross-sectional process diagram of the main part for explaining the method of manufacturing a semiconductor device according to the invention.
FIG. 5 is a schematic cross-sectional process diagram of the main part for explaining the method of manufacturing a semiconductor device according to the invention.
FIG. 6 is a schematic cross-sectional process diagram of the main part for explaining the method of manufacturing a semiconductor device according to the invention.
FIG. 7 is a schematic cross-sectional process diagram of the main part for explaining the method of manufacturing a semiconductor device according to the invention.
FIG. 8 is a schematic cross-sectional process diagram of the main part for explaining the method of manufacturing a semiconductor device according to the invention.
FIG. 9 is a diagram simulating the boron ion depth distribution in the gate electrode portion of the NMOS transistor in the semiconductor device of the present invention.
FIG. 10 is a characteristic diagram showing variation in threshold voltage of an NMOS transistor in a semiconductor device of the present invention.
FIG. 11 is a characteristic diagram showing the gate length dependence of the punch-through breakdown voltage of the PMOS transistor in the semiconductor device of the present invention.
FIG. 12 is a characteristic diagram showing the substrate bias voltage dependence of the threshold voltage of the PMOS transistor in the semiconductor device of the present invention.
FIG. 13 is a diagram showing junction diode characteristics of NMOS and PMOS transistors in the semiconductor device of the present invention.
FIG. 14 is a schematic cross-sectional view of a CMOS transistor for explaining a conventional method of manufacturing a CMOS transistor.
FIG. 15 is a schematic cross-sectional view of a main part showing a configuration of a conventional CMOS transistor.
[Explanation of symbols]
1 Element isolation insulating film
2 NMOS transistor
3 PMOS transistor
4 Silicon substrate
5 p-well
6 n-well
7, 8 channel region
9 Gate insulation film
10 Gate electrode
11, 12 LDD region
13 Sidewall spacer
14, 15 Source / drain regions
16 p-type high concentration impurity region
17 NMOS transistor formation region
18 PMOS transistor formation region
19 Silicon oxide film
20, 21, 23, 24, 25, 26 Resist mask
22 Polysilicon film
37 CMOS transistor

Claims (1)

(A) forming a p-well and an n-well, a gate insulating film and a gate electrode in the NMOS and PMOS transistor formation regions on the silicon semiconductor substrate,
(B) step of the the NMOS and PMOS transistor formation region, an n-type impurity及beauty B F ₂ ⁺ respectively the gate electrode as a mask by ion implantation, to form respectively the source / drain regions by heat treatment,
(C) Boron ions or BF ₂ ⁺ are penetrated through the gate electrode over the entire surface of the silicon semiconductor substrate , and the implantation peak depth is within the range from the lower half of the gate electrode to the upper half of the depth of the source / drain region. At the same time, ion implantation is performed immediately below the boundary between the source / drain region and the well, and heat treatment is performed, so that a band-like boron ion or BF ₂ ⁺ with a constant width in the depth direction is formed in the channel region immediately below the gate electrode. Forming a concentration region in this order so as to overlap the channel region in part or all of the width in the depth direction;
Immediately before or after the formation of the n-well in step (a), using the n-well formation mask, boron ions or BF ₂ implanted in the step (c) into the channel region immediately below the gate electrode of the PMOS transistor. ^A method for manufacturing a semiconductor device, comprising introducing an n-type impurity in an amount exceeding the concentration of ⁺ .

Images