KR100474543B1 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
- Publication number
- KR100474543B1 KR100474543B1 KR10-1998-0025983A KR19980025983A KR100474543B1 KR 100474543 B1 KR100474543 B1 KR 100474543B1 KR 19980025983 A KR19980025983 A KR 19980025983A KR 100474543 B1 KR100474543 B1 KR 100474543B1
- Authority
- KR
- South Korea
- Prior art keywords
- well
- semiconductor substrate
- forming
- oxide film
- film
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 하나의 기판에 다양한 Vt값을 갖는 소자를 구비하는 장치에서 소자분리 공정후에 N채널 Vt 이온주입을 실시하고, 반도체기판의 N웰 및 P웰상에 희생산화막을 형성하고, 나머지 다른 Vt를 필요로하는 부분상에 SPG막을 형성한 후에 NMOS 및 PMOS를 형성하여 서로 다른 Vt를 갖는 MOS를 간단한 공정으로 형성하였으므로, 공정이 간단해지고, 이온주입에 따른 기판 손상이 방지되어 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, an N-channel Vt ion implantation is performed after a device separation process in an apparatus having a device having various Vt values on one substrate, and on the N well and P well of the semiconductor substrate. After forming the sacrificial oxide film, forming the SPG film on the part requiring the other Vt, and forming the NMOS and the PMOS, the MOS having different Vt was formed in a simple process. Damage can be prevented to improve process yield and device operation reliability.
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 특히 별도의 마스크 공정이나 웰 공정 없이 선택적 다결정실리콘 성장(selective poly-Si growing; 이하 SPG라 칭함) 방법으로 서로 다른 문턱전압을 갖는 트랜지스터를 형성하여 공정을 단순하여 수율이 향상되며, 소자의 동작 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and in particular, to form transistors having different threshold voltages by using selective poly-Si growing (SPG) without a separate mask process or well process. The present invention relates to a method for manufacturing a semiconductor device which can improve the yield by simplifying the operation and improve the operation reliability of the device.
일반적으로 반도체소자가 고집적화되어 감에 따라 하나의 기판에 서로 다른 Vt를 갖는 소자를 형성하여야할 필요성이 대두되고, 이를 위하여 한가지 도전형의 반도체기판에 P 및 N웰 영역을 형성하고, 서로 다른 도전형의 웰영역내에도 별도의 웰영역들을 형성하는 3중 웰 구조를 갖도록하거나, 마스크 공정으로 Vt를 조절하게 된다. In general, as semiconductor devices are highly integrated, there is a need to form devices having different Vt on one substrate. For this purpose, P and N well regions are formed on one conductive semiconductor substrate, and different conductivity In the well region of the mold, it is possible to have a triple well structure that forms separate well regions or to control Vt by a mask process.
예를들어 P 및 N모스 트랜지스터를 함께가지는 씨모스(complementry MOS) 트랜지스터는 소비전력이 매우 적고, 동작속도가 매우 빠른 이점이 있다. For example, a complementary MOS transistor having both P and N MOS transistors has advantages of low power consumption and very high operating speed.
종래 3중 웰 구조를 갖는 반도체소자의 제조 방법에 관하여 살펴보면 다음과 같다. Looking at the manufacturing method of a semiconductor device having a conventional triple well structure as follows.
먼저, 실리콘 웨이퍼 반도체기판상에 소자분리를 위한 패드산화막과 질화막 패턴을 형성하고, 상기 질화막패턴에 의해 노출되어있는 반도체기판의 하부에 N웰 형성을 위한 불순물을 이온주입한 후, 열산화 공정을 실시하여 상기 질화막 패턴에 의해 노출되어있는 반도체기판에 소자분리 산화막을 형성함과 동시에 상기 불순물을 확산시켜 N웰을 형성한다. First, a pad oxide film and a nitride film pattern for device isolation are formed on a silicon wafer semiconductor substrate, and ion implantation of impurities for N well formation is performed in the lower portion of the semiconductor substrate exposed by the nitride film pattern, followed by a thermal oxidation process. In this case, the device isolation oxide film is formed on the semiconductor substrate exposed by the nitride film pattern, and the impurities are diffused to form N wells.
그다음 상기 반도체기판의 N웰이나 그 외부에 P웰 및 R웰 형성을 위한 고에너지 이온주입하고 확산시켜 P웰과 R웰을 동시에 형성한다. Then, the P well and the R well are simultaneously formed by implanting and diffusing high-energy ions for forming the P well and the R well into the N well or the outside of the semiconductor substrate.
상기에서 N웰 형성시 R웰을 위한 N웰도 함께 형성하는데, 셀영역이나 주변회로영역 모두 열확산이 아닌 N웰 마스크나 추가된 셀-웰 마스크를 이용하여 고에너지 이온주입으로 N웰을 형성하는데, N웰의 도핑 프로파일을 완만하게 하기 위하여 여러 에너지 단계의 이온주입을 실시하며, 이온주입에 따른 결함을 보상하고자 열처리 공정을 거치게 된다. In forming the N well, the N well for the R well is also formed. In the cell region or the peripheral circuit region, the N well is formed by high energy ion implantation using an N well mask or an added cell-well mask, not thermal diffusion. In order to smooth the doping profile of the N well, ion implantation is performed at various energy levels, and a heat treatment process is performed to compensate for defects caused by ion implantation.
또한 마스크 공정에 의한 Vt 조절은 상기와 같이 형성된 웰의 소정 부분에 Vt 조절용 이온을 주입하여 트랜지스터의 Vt를 조절하게 된다.In addition, in the Vt control by the mask process, the Vt control ions are implanted into a predetermined portion of the well formed as described above to adjust the Vt of the transistor.
상기와 같은 종래 기술에 따른 반도체소자의 Vt 조절방법은 3중웰을 형성하거나 필요한 영여에 마스크를 이용한 Vt 조절용 이온주입등의 방법으로 트랜지스터의 Vt를 조절하는데, 이러한 방법은 공정이 복잡하고, 수차례의 공정에 의해 기판 표면에 손상되는 등의 불량 발생 원인으로 공정수율 및 소자동작의 신뢰성이 떨어지는 문제점이 있다. Vt control method of the semiconductor device according to the prior art as described above to adjust the Vt of the transistor by a method such as forming a triple well or ion implantation for Vt control using a mask in the required area, such a process is complicated, several times There is a problem that the process yield and the reliability of the device operation is inferior due to the occurrence of defects such as damage to the substrate surface by the process.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본 발명의 목적은 SPG 방법으로 서로 Vt가 다른 트랜지스터를 형성하여 공정이 간단하고 기판 손상을 방지하여 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법을 제공함에 있다. The present invention is to solve the above problems, an object of the present invention is to form a transistor having a different Vt by the SPG method to simplify the process and to prevent substrate damage to improve the process yield and device operation reliability The present invention provides a method for manufacturing a semiconductor device.
상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체소자 제조방법의 특징은, Features of the semiconductor device manufacturing method according to the present invention for achieving the above object,
반도체기판상에 소자분리 산화막을 형성하는 공정과,Forming a device isolation oxide film on the semiconductor substrate;
상기 반도체기판의 일측 및 타측에 N웰 및 P웰을 형성하는 공정과,Forming an N well and a P well on one side and the other side of the semiconductor substrate;
상기 반도체기판의 NMOS를 형성할 영역에 N채널 이온주입을 실시하는 공정과, Performing an N-channel ion implantation into a region where an NMOS is to be formed on the semiconductor substrate;
상기 반도체기판의 전표면에 희생산화막을 형성하는 공정과,Forming a sacrificial oxide film on the entire surface of the semiconductor substrate;
상기 반도체기판에서 다른 Vt를 가지는 소자가 형성될 부분상의 희생산화막을 제거하는 공정과, Removing the sacrificial oxide film on the portion where the device having another Vt is to be formed in the semiconductor substrate;
상기 희생산화막이 제거되어 노출되어있는 반도체기판상에 SPG막을 형성하는 공정과,Forming an SPG film on the exposed semiconductor substrate by removing the sacrificial oxide film;
상기 남아 있는 희생산화막을 제거하는 공정과, Removing the remaining sacrificial oxide film;
상기 SPG막과 반도체기판상에 게이트산화막을 형성하는 공정과, Forming a gate oxide film on the SPG film and the semiconductor substrate;
상기 게이트 산화막상에 게이트전극을 형성하는 공정과, Forming a gate electrode on the gate oxide film;
상기 게이트전극 양측의 반도체기판과 SPG막에 N- 저농도 불순물영역을 형성하는 공정과,Forming an N − low concentration impurity region in the semiconductor substrate and the SPG film on both sides of the gate electrode;
상기 SPG막-N웰 및 P웰상의 N- 저농도 불순물영역에 각각 N+와 P+의 고농도 불순물영역을 형성하여 SPG막상에 낮은 Vt를 갖는 NMOS와 노말 Vt를 갖는 NMOS 및 PMOS를 형성하는 공정을 구비함에 있다.Forming a high concentration impurity region of N + and P + in the N - low concentration impurity regions on the SPG film-N well and the P well to form NMOS having low Vt and NMOS and PMOS having normal Vt on the SPG film; It's in the box.
이하, 본 발명에 따른 반도체소자의 제조방법에 관하여 첨부도면을 참조하여 상세히 설명한다. Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1f는 본 발명에 따른 반도체소자의 삼중웰 제조공정도이다. 1A to 1F are triple well manufacturing process diagrams of a semiconductor device according to the present invention.
먼저, 제1도전형, 예를들어 P형 실리콘 웨이퍼 반도체기판(10)상에 통상의 소자분리 방법으로 소자분리 산화막(12)을 형성하고, 상기 반도체기판(10)상에 희생산화막(14)을 형성한다. First, a device isolation oxide film 12 is formed on a first conductive type, for example, a P-type silicon wafer semiconductor substrate 10 by a conventional device isolation method, and a sacrificial oxide film 14 is formed on the semiconductor substrate 10. To form.
그다음 상기 반도체기판(10)의 일측에 N웰(16)과 P웰(18)을 형성하고, 상기 반도체기판(10)에서 NMOS 영역으로 예정되어있는 부분을 노출시키는 제1감광막패턴(20)을 형성한 후, 상기 노출된 반도체기판(10)에 N채널 이온주입(도시되지 않음)을 실시한다. 상기 N채널 이온주입은 희생산화막(14) 형성전에 실시할 수도 있다. (도 1a 참조). Next, an N well 16 and a P well 18 are formed on one side of the semiconductor substrate 10, and the first photoresist layer pattern 20 exposing a portion scheduled for the NMOS region of the semiconductor substrate 10 is formed. After formation, N-channel ion implantation (not shown) is performed on the exposed semiconductor substrate 10. The N-channel ion implantation may be performed before forming the sacrificial oxide film 14. (See FIG. 1A).
그후, 상기 제1감광막패턴(20)을 제거하고, 반도체기판(10)에서 다른 Vt를 갖는 소자 영역으로 예정되어있는 부분을 노출시키는 제2감광막패턴(22)을 희생산화막(14)상에 형성한 후, 상기 제2감광막패턴(22)에 의해 노출되어있는 희생산화막(14)을 제거하고, (도 1b 참조), 상기 제2감광막패턴(22)을 제거한후, 상기 노출되어있는 반도체기판(10)상에 SPG막(24)을 형성한다. (도 1c 참조). Thereafter, the first photoresist layer pattern 20 is removed, and a second photoresist layer pattern 22 is formed on the sacrificial oxide layer 14 to expose a portion of the semiconductor substrate 10 to a device region having a different Vt. After that, the sacrificial oxide film 14 exposed by the second photoresist layer pattern 22 is removed (see FIG. 1B), the second photoresist layer pattern 22 is removed, and the exposed semiconductor substrate ( 10, an SPG film 24 is formed. (See FIG. 1C).
그다음, 상기 남아 있는 희생산화막(14)을 전부 제거하고, 상기 반도체기판(10)과 SPG막(24)상에 게이트 산화막(26)을 형성하고, 상기 게이트 산화막(26)상에 게이트전극(28)을 형성한다. (도 1d 참조). Then, the remaining sacrificial oxide film 14 is removed completely, and a gate oxide film 26 is formed on the semiconductor substrate 10 and the SPG film 24, and the gate electrode 28 is formed on the gate oxide film 26. ). (See FIG. 1D).
그후, 상기 게이트전극(28) 양측의 반도체기판(10)과 SPG막(24)에 N- 저농도 불순물영역(30)을 형성하고, (도 1e 참조), 각각의 게이트전극(28) 측벽에 산화막 재질의 절연 스페이서(32)를 형성한 후, 상기 스페이서(32)양측에 고농도 불순물영역을 형성하되, 상기 SPG막(24)과 N웰 반도체기판(10)상에는 N+ 고농도 불순물영역(34)을 형성하고, P웰 반도체기판(10)상에는 P+ 고농도 불순물영역(36)을 형성한다. 여기서 상기 SPG막(24)상에 형성된 NMOS는 낮은 Vt를가지며, N웰 및 P웰에 형성된 NMOS 및 PMOS는 각각 노말한 Vt를 갖는 MOS가 된다. (도 1f 참조).Thereafter, an N − low concentration impurity region 30 is formed in the semiconductor substrate 10 and the SPG film 24 on both sides of the gate electrode 28 (see FIG. 1E), and an oxide film is formed on the sidewalls of the respective gate electrodes 28. After the insulating spacer 32 is formed of a material, a high concentration impurity region is formed on both sides of the spacer 32, and an N + high concentration impurity region 34 is formed on the SPG film 24 and the N well semiconductor substrate 10. P + high concentration impurity regions 36 are formed on the P well semiconductor substrate 10. Here, the NMOS formed on the SPG film 24 has a low Vt, and the NMOS and PMOS formed on the N well and the P well are MOSs having normal Vt, respectively. (See FIG. 1F).
상기에서는 낮은 Vt의 MOS를 SPG상에 형성하였으나, SPG막상에 PMOS를 형성하면 또 다른 Vt를 갖도록 할수도 있다.In the above, a low Vt MOS is formed on the SPG, but forming a PMOS on the SPG film may have another Vt.
상기한 바와같이 본 발명에 따른 반도체소자의 제조방법은, 소자분리 공정후에 N채널 Vt 이온주입을 실시하고, 반도체기판의 N웰 및 P웰상에 희생산화막을 형성하고, 나머지 다른 Vt를 필요로하는 부분상에 SPG막을 형성한 후에 NMOS 및 PMOS를 형성하여 서로 다른 Vt를 갖는 MOS를 간단한 공정으로 형성하였으므로, 공정이 간단해지고, 이온주입에 따른 기판 손상이 방지되어 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있는 이점이 있다. As described above, in the method of manufacturing a semiconductor device according to the present invention, N-channel Vt ion implantation is performed after the device isolation process, a sacrificial oxide film is formed on the N well and the P well of the semiconductor substrate, and the other Vt is required. After forming the SPG film on the part, NMOS and PMOS were formed to form MOS having different Vt in a simple process, which simplifies the process and prevents substrate damage due to ion implantation, thereby improving process yield and device operation reliability. There is an advantage to this.
도 1a 내지 도 1f는 본 발명에 따른 반도체소자의 제조공정도. 1A to 1F are manufacturing process diagrams of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
10 : 반도체 기판 12 : 소자분리 산화막10 semiconductor substrate 12 device isolation oxide film
14 : 희생산화막 16 : N웰14: sacrificial oxide film 16: N well
18 : P웰 20,22 : 감광막패턴18: P well 20, 22: photosensitive film pattern
24 : SPG막 26 : 게이트 산화막24: SPG film 26: gate oxide film
28 : 게이트전극 30 : N- 저농도 불순물영역28: gate electrode 30: N - low concentration impurity region
32 : 절연 스페이서 34 : N+ 고농도 불순물영역32: insulation spacer 34: N + high concentration impurity region
36 : P+ 고농도 불순물영역36: P + high concentration impurity region
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-1998-0025983A KR100474543B1 (en) | 1998-06-30 | 1998-06-30 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-1998-0025983A KR100474543B1 (en) | 1998-06-30 | 1998-06-30 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20000004539A KR20000004539A (en) | 2000-01-25 |
| KR100474543B1 true KR100474543B1 (en) | 2005-05-27 |
Family
ID=19542364
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-1998-0025983A KR100474543B1 (en) | 1998-06-30 | 1998-06-30 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100474543B1 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR900005343A (en) * | 1988-09-14 | 1990-04-14 | 아오이 죠이치 | Pattern data generator |
| JPH05110004A (en) * | 1991-10-21 | 1993-04-30 | Nec Corp | Manufacture of semiconductor device |
| KR970052106A (en) * | 1995-12-27 | 1997-07-29 | 김주용 | Manufacturing method of semiconductor device |
-
1998
- 1998-06-30 KR KR10-1998-0025983A patent/KR100474543B1/en not_active IP Right Cessation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR900005343A (en) * | 1988-09-14 | 1990-04-14 | 아오이 죠이치 | Pattern data generator |
| JPH05110004A (en) * | 1991-10-21 | 1993-04-30 | Nec Corp | Manufacture of semiconductor device |
| KR970052106A (en) * | 1995-12-27 | 1997-07-29 | 김주용 | Manufacturing method of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20000004539A (en) | 2000-01-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH05315561A (en) | Manufacture of semiconductor device | |
| EP0465045B1 (en) | Method of field effect transistor fabrication for integrated circuits | |
| US6054357A (en) | Semiconductor device and method for fabricating the same | |
| JPH1084045A (en) | Semiconductor integrated circuit device and its manufacturing method | |
| KR100232197B1 (en) | Method of manufacturing semiconductor device | |
| KR100840659B1 (en) | Method for Manufacturing DEMOS Device | |
| KR100474543B1 (en) | Manufacturing method of semiconductor device | |
| KR100465606B1 (en) | Triple well manufacturing method of semiconductor device | |
| JP3778810B2 (en) | Manufacturing method of semiconductor device | |
| JP2000164727A (en) | Manufacture of semiconductor device | |
| KR0146528B1 (en) | Method for manufacturing semiconductor device | |
| KR100310173B1 (en) | Method for manufacturing ldd type cmos transistor | |
| KR100406591B1 (en) | Manufacturing method of semiconductor device | |
| KR100207547B1 (en) | Method of fabricating cmos | |
| KR0165381B1 (en) | High voltage mosfet manufacturing method | |
| KR100265351B1 (en) | Cmos transistor and method for fabricating the same | |
| KR19990057380A (en) | Manufacturing method of MOS field effect transistor | |
| KR100263464B1 (en) | Semiconductor element isolation method | |
| KR100537272B1 (en) | Method for fabricating of semiconductor device | |
| JPH05121432A (en) | Semiconductor integrated circuit element | |
| KR100252902B1 (en) | method for fabricvating complementary metal oxide semiconductor device | |
| KR100327438B1 (en) | method for manufacturing of low voltage transistor | |
| KR100439102B1 (en) | Method for manufacturing a semiconductor device | |
| KR100399069B1 (en) | Method for fabricating of logic device | |
| JPH06216379A (en) | Semiconductor device and its manufacture |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20110126 Year of fee payment: 7 |
|
| LAPS | Lapse due to unpaid annual fee |