JPH03151669A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the breakdown strength across a junction by implanting impurity ions into a region where a source.drain region is to be formed, dividing the process into a plurality of stages. CONSTITUTION:There are formed an element isolation layer 2, a gate 3, and the like on a p-type Si substrate 1, and <31>P<-> is implanted into a surface layer of the substrate 1 to form a source.drain region (n<->)4. Then, after a side wall insulating film 5 is formed around the sides of the gate 3, <31>P<+> is implanted into the source.drain region 4 in concentration of about 10<18>atoms/cm<3> to form a diffusion region (n<+>)4a. Further, the substrate 1 surface is covered with an insulating film 6 to form a contact hole, and thereafter <75>As<+> is implanted into the contact part in concentration of about 10<20>atoms/cm<2> to form a contact region (n<+>)4b. The ion implantation is performed in three stages as described above, whereby concentration of a region of the source.drain region 4 along a junction between the region 4 and the substrate 1 can be restricted to lower one and hence breakdown strength of the junction can be prevented from being lowered.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming source/drain regions in the manufacturing process of, for example, a MOS transistor.

<Prior Art> As a conventional method for forming source/drain regions of a MOS transistor, for example, after forming a gate, an element isolation layer, etc. on a p-type Si substrate, a method is used to form a source/drain region in the region where the source/drain is to be formed. Methods such as diffusing impurities such as P or implanting impurity ions have been adopted.

<Problem to be solved by the invention> Now, in the MO3I transistor, the source
Although it is desirable to improve the breakdown voltage at the junction between the drain region and the surrounding region, it has been difficult to improve the junction breakdown voltage using the above-described conventional formation method. In other words, in order to increase the junction breakdown voltage, it is sufficient to lower the impurity concentration at the junction of the source/drain regions, but according to conventional methods, it is impossible to lower the concentration only at the junction. In order to improve the junction breakdown voltage, it is necessary to lower the concentration in the entire source/drain region. However, when the concentration in the entire source/drain region is lowered, the diffusion resistance in each region increases, and the contact resistance with electrodes and electrodes in each region also increases, resulting in a decrease in characteristics.

An object of the present invention is to provide a method that can improve junction breakdown voltage without increasing diffusion resistance when forming source/drain regions of a MOS transistor or the like.

<Means for Solving the Problems> In order to achieve the above object, in the method of the present invention, a semiconductor substrate 1 is prepared as shown in FIGS. 1 to 3 corresponding to the embodiment.
After implanting impurity ions with a conductivity type different from that of the surface layer into the region where the source/drain is to be formed in the surface layer (Fig. 1), the junction with the surface layer of the substrate 1 in the impurity implanted region 4 is implanted. Impurity ions of the same conductivity type are implanted at a higher concentration than the previous implantation (second implantation) except for the region along the
figure.

Figure 3).

By implanting impurity ions into the region where the source/drain is to be formed in multiple stages, it is possible to lower the impurity concentration only in the region along the junction of the source/drain region with the substrate. Become.

<Example> FIGS. 1 to 3 are diagrams for explaining the steps of the manufacturing method of the present invention, and show an example in which the present invention is applied to manufacturing a MO3I-transistor.

First, as shown in FIG. 1, p-type Si is
A device isolation layer (LOGOS) 2, a gate 3, etc. are formed on a substrate 1. Note that the concentration of the St substrate 1 is 10
It is set to be about 5 atoms/cm.

Now, 31p- is implanted into the surface layer of the substrate 1 and the source
A drain region (n-) 4 is formed. The implantation concentration at this time is about 10"aLoms7cm".

Next, after forming a sidewall insulating film 5 around the sides of the gate 3, i+p+ is implanted into the source/drain region 4 at a concentration of about 10 ``atoms/cm'' to form the source/drain region 4.
A diffusion region (n”) 4a is formed in the drain region 4 (
Figure 2).

Next, the surface of the substrate 1 is covered with an insulating film 6 to form a contact hole, and then "As" is implanted into the contact portion at a concentration of about 10 "atoms/cn+" to form a contact region (n") 4b. (Figure 3).

As described above, by performing ion implantation in three stages, the concentration in the region along the junction with the substrate 1 of the source/drain region 4 can be kept low, and the concentration in other regions,
The concentration of the diffusion region 4a and the contact region 4b can be increased. This makes it possible to suppress a decrease in breakdown voltage of the junction without increasing the diffusion resistance of the source/drain region 4, and furthermore, it becomes possible to improve the junction resistance. Moreover, the contact resistance with the electrode can also be kept low.

In the above embodiment, ion implantation is performed in three stages, but it may be performed in two stages, and the same effect can be obtained in this case as well. Further, ion implantation may be performed in three or more stages as necessary.

The above describes an example in which the present invention is applied to an n-channel MOS transistor, but the present invention also applies to a p-channel MOS transistor.
O3) Of course, it can be applied to transistors, and furthermore, it can be applied to forming source/drain regions of other transistors.

Note that the technical idea of the present invention can also be applied to other semiconductor devices having a pn junction.

<Effects of the Invention> As explained above, according to the method of the present invention, for example, M
OS) When forming the source/drain regions of a transistor, it is possible to lower the concentration only at the junction of the source/drain regions, thereby improving the junction breakdown voltage without increasing the diffusion resistance. Furthermore, the contact resistance between the source and drain regions and the electrodes can be kept low. As a result, M with good characteristics
An OS transistor can be obtained.

[Brief explanation of the drawing]

1 to 3 are diagrams for explaining the steps of the manufacturing method of the present invention. 1...p-type Si substrate 3...gate 4...source/drain region 4a...diffusion region 6-4b...contact region

Claims (1)

[Claims] A method for forming source/drain regions of a transistor in the manufacturing process of a semiconductor device, the method comprises implanting impurity ions having a conductivity type different from that of the surface layer into a predetermined region of a surface layer of a semiconductor substrate, and then implanting impurity ions into the impurity implanted region. A method for manufacturing a semiconductor device, comprising implanting impurity ions of the same conductivity type into a portion of the semiconductor device other than a region along a junction with the substrate surface layer at a higher concentration than the previous implantation concentration.