JPH0346238A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To inhibit the spread of a depletion layer and to obtain stable transistor characteristics by a method wherein with the first source and drain of a P-channel MOS transistor formed, nitrogen or oxygen ions are implanted and high-resistance regions are respectively formed between the first source and drain and the second source and drain of the transistor. CONSTITUTION:First source and drain 4 and 5 are formed and thereafter, N or O ion-implantated layers 6 are formed. Then, when second source and drain 8 and 9 are formed, the structure of a P-channel MOS transistor becomes a structure, in which the high-resistance layers 6 of a strong N or O concentration respectively exist in the vicinities of the shoulders of the P-type impurity second source and drain 8 and 9. With this when a voltage is applied to the first and second sources and drains 4, 5, 8 and 9, a depletion layer 10 is generated, but there are the layers 6 of a strong N or O concentration at the circumferential parts, at which the spread of the layer 10 becomes widest, of the second source and drain 8 and 9, in short, at the parts of the shoulders of the source and drain 8 and 9 and have a high resistance. Thereby, the existence of the layers 6 inhibits the spread of the layer 10 and stable transistor characteristics can be obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is applicable to metals, oxides, and semiconductors (hereinafter referred to as MOS).
The present invention relates to a method for manufacturing a type semiconductor device.

[Summary of the invention]

After forming the gate electrode of the P-channel MOS transistor, a first source/drain having a P-type impurity concentration is formed, and at the same time nitrogen or oxygen ions are implanted using the gate electrode as a mask, and then sidewall spacers of the gate electrode are formed. A region with high resistance is formed between the source and drain by forming a second source/drain having a P-type impurity concentration.

[Conventional technology]

As shown in FIG. 3, the channel length l of the gate electrode 23 is 2.
．． If the length is less than 0 μm, the electric field between the source and drain of the PMOS transistor increases and punch-through is more likely to occur.
The drain was formed twice in a self-aligned manner using the gate t123 as a mask.

That is, after forming the gate electrode 23, first sources and drains 24 and 25 having a P-type impurity concentration are formed, and then sidewall spacers 26 are formed.

Next, using the gate electrode 23 and sidewall spacer 26 as masks, second sources and drains 27 and 28 having a P-type impurity concentration are formed. Here, the concentration of the first source/drain 24.25 is the same as that of the second source/drain 27.25.
It is generally thinner than the concentration of No. 28.

This structure is generally called Lightly Doped Dr.
ain (abbreviated as LDD)) transistor.

[Problem to be solved by the invention]

Even in the case of an LDD transistor, if the heat treatment temperature after forming the source/drain becomes high, the second source/drain with a high P-type impurity concentration will extend laterally, or the gate electrode 23 will become short. When you run around,
As the actual effective channel length becomes shorter, as shown in Figure 3, when a voltage is applied to the source and drain, the depletion layer 2
9 occurs, and as the electric field is increased, the depletion layer expands and the source and drain depletion layers are directly connected, causing a large t current to flow, and the transistor no longer exhibits characteristics as a transistor.0 The present invention has solved this drawback. The purpose of the present invention is to provide a method for manufacturing a semiconductor device.

[Means to solve the problem]

In order to achieve the above object, the present invention adopted the following method. That is, a method for manufacturing a P-channel MOS transistor includes a step of forming a gate electrode, a step of implanting nitrogen or oxygen ions into a P-type silicon substrate, and a step of implanting a P-type impurity layer into the silicon S plate. Making first
A step of forming a second source and a drain, a step of forming a sidewall insulating film of a gate electrode, and a step of forming a P-type impurity layer in the silicon substrate to form a second source and drain. This is a method for manufacturing a semiconductor device.

〔Example〕

An embodiment of the present invention will be described in detail based on FIG. 1st
As shown in Figure fa), after forming a gate insulating film 2 on a semiconductor substrate 1 such as silicon (Si), a gate electrode 3 is formed, and then using this gate electrode 3 as a mask, a P-type Source/drain with an impurity layer of 4.5
form. In the case of silicon, the semiconductor substrate 1 is an N-well formed in N-type silicon or P-type silicon. Further, the gate insulating film 2 is generally a silicon oxide film, but may also be a silicon nitride film, a silicon oxynitride film, or a variety of these films. Furthermore, the gate electrode 3 may be a polycrystalline silicon film, a metal film, a polycide film, or the like.

Next, as shown in Figure 1 (1)), nitrogen (N) or oxygen (
0) is ion-implanted. Since ions are implanted using the gate electrode 3 as a mask, N or 0 ions are not implanted into the channel directly under the gate electrode 3.

In addition, when ions are not implanted into the gate electrode 3, the gate electrode 3
You may leave a photoresist or the like on top.The ion implantation range (Rp) at this time corresponds to the depth of the region where the second source/drain depletion layer will extend from the surface of the semiconductor substrate 1 in the future. For example, if the source/drain diffusion depth is 0.3 μm, the ion implantation range is preferably 0.3 μm ± 0.05 μm. Of course, the effect will be smaller if it is outside this range. However, it is possible to prevent the source and drain depletion layers from coming into contact with each other. Also, N
Alternatively, it is desirable that the range of ion implantation for 0 is below the first source/drain 4, 5. In other words, it is preferable that the range of ion implantation is below the first source/drain 4,5.
The range of impurity ion implantation is 0.
If the diameter is 1 μm, the range of N or 0 ion implantation is 0.1
The depth should be deeper than μm. The impurity concentration of the first source/drain 4.5 is generally lower than the impurity concentration of the second source/drain. It is generally smaller than the extension of the drain depletion layer.

Furthermore, the larger the amount of N or ○ ions implanted, the more effective it is in preventing the extension of the depletion layer. This is not desirable because it causes a decrease in mobility.

Therefore, the amount of N or O ions to be implanted is preferably in the range of IXIQ''/cd to 5XIQ1S-.

Next, as shown in FIG. 1 (C1), a spacer insulating film 7 is formed on the side wall of the gate insulating film 3.
This method is the same as the method for forming a spacer for a DD transistor. This insulation M7 is made of silicon oxide film (SiCh film), silicon nitride film (Si is Na film), silicon oxynitride film (
StoxNy membrane), etc.

Next, as shown in FIG. 1+dl, P-type impurities are introduced into the silicon substrate 1 using the gate electrode 3 and sidewall spacers as masks to form a second source/drain 8.9.

Examples of methods for introducing P-type impurities include ion implantation and diffusion. In the case of ion implantation, boron (B
The second source/drain layer is diffused by further heat treatment performed with ions such as ゛) or boron fluoride (BF2゜), etc., but the second source/drain layer is diffused near the N or O ion implantation layer.・The drain layer does not stretch much.

The P-type transistor created as described above is shown in Figure 1+d.
As shown in FIG. 1, a high-resistance layer 6 with a high concentration of N or O exists near the shoulders of the second source and drains 8 and 9 of P-type impurities.

〔Effect of the invention〕

As shown in FIG. 2, a depletion layer 10 is generated when a voltage is applied to the first and second sources and drains 4, 5, 8.9. However, the concentration of N or ○ is low at the circumferential portion of the second source and drain 8°9, that is, at the shoulder portion, where the depletion 1i10 extends the most. 6 and has high resistance. Due to the presence of N6, the extension of the depletion layer is suppressed, and even if the length l of the gate electrode 3 becomes 2 μm or less (of course, it also includes 1.0 μm or less), the depletion layer on the source side and drain side is There is no contact under the electric field used, and it exhibits stable transistor characteristics.

Furthermore, as explained in the embodiment, since the first sources and drains 4 and 5 are thin and located near the surface, a transistor with a small effective channel length and high speed is formed.
Moreover, the transistor has a large bunch-through breakdown voltage.

Although the above effects are explained for the normally used power supply voltage of 10V or less, it goes without saying that the present invention can also be applied to high-voltage devices to which a voltage higher than IOV is applied.

In this embodiment, it is explained that the N or O ion implantation layer 6 is formed after the first source/drain 4.5 is formed, but the same effect can be obtained even if the process is performed in the opposite direction. . That is, the first source/drain 4.5 may be formed after forming the N or O ion implantation layer 6.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIGS. 1(a) to (di) are cross-sectional views showing the process order of the manufacturing method of the present invention, FIG. 2 is a cross-sectional view showing the effects of the present invention, and FIG. 3 is a conventional transistor. 1.21...Semiconductor substrate 2.22...Gate insulating film 3.23...Gate electrode 4, 5.24.25...First source/drain 6
...N or O ion implantation layer 7.26...Side wall insulating film 8, 9.27.28...Second source/drain 1
0゜29・・Depletion layer・Medium depletion layer or above

Claims (1)

[Claims] In a method of manufacturing a P-channel MOS transistor,
a step of forming a gate electrode; a step of implanting nitrogen or oxygen ions into a P-type silicon substrate; and a step of forming a P-type impurity layer in the silicon substrate to form a first source and a drain; A method for manufacturing a semiconductor device, comprising the steps of forming a sidewall insulating film of a gate electrode, and forming a P-type impurity layer in the silicon substrate to form a second source and drain.