JPH04251939A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent punch-through in a MOSFET by keeping the drain depletion layer from extending toward the source even in the case of a lightly doped substrate. CONSTITUTION:After a gate electrode 4 is formed, an insulating film 5 is deposited on an area away from the gate electrode. The insulating film 5 and gate electrode 4 are used as a mask, and oxygen ions are obliquely implanted to form a buried insulating layer 7 in a channel region.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] This invention relates to semiconductor devices, especially MO
The present invention relates to an S field effect semiconductor device and a method for manufacturing the same.

0002

2. Description of the Related Art FIG. 2 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device of this type. In the figure, 1 is a P-type silicon substrate, 2 is an insulating film formed on the P-type silicon substrate 1,
3 is a LOCOS oxide film (field oxide film) for element isolation provided at a predetermined location on the P-type silicon substrate 1;
, 4 are gate electrodes, and 9 and 10 are N-type source and drain diffusion layer regions formed by implanting N-type impurities, respectively.

Next, the manufacturing method will be explained. First, as shown in FIG. 2A, a gate oxide film 2 and a LOCOS oxide film 3 for element isolation are formed on a P-type silicon substrate 1. After forming a gate electrode 4 on the gate oxide film 2, using this as a mask, ions of an N-type impurity such as arsenic are implanted from the direction shown by the arrow 8. As a result, a source diffusion layer region 9 and a drain diffusion layer region 10 are formed as shown in FIG. 2(b).

Next, the operation will be explained. A positive potential is applied to the drain diffusion layer region 10 with reference to the potential of the source diffusion layer region 9 . If the potential of the gate electrode 4 is equal to the potential of the source diffusion layer region 9, no current will flow between the source and drain, but if the gate electrode 4 is at a positive potential and the channel of the n-type inversion layer is formed between the source and drain. When is formed, current flows between the source and drain. In this way, the electric potential of the gate electrode 4 controls the current flowing between the source and drain.

[0005]

[Problems to be Solved by the Invention] Since the semiconductor device manufactured by the conventional manufacturing method is constructed as described above, when the gate length becomes short, the depletion layer on the drain side reaches the source diffusion layer region, and the gate There is a problem in that a phenomenon called punch-through occurs in which a current that cannot be controlled by the electrode 4 flows between the source and the drain. In addition, to prevent this, it is necessary to increase the substrate concentration to suppress the expansion of the depletion layer, and for that substrate concentration, the gate voltage, that is, the threshold voltage necessary to form a channel, must be set to a constant value. There were problems such as the need to form a thin oxide film with high precision in order to adjust the temperature.

The present invention has been made to solve the above-mentioned problems, and aims to provide a semiconductor device and a method for manufacturing the same that can suppress the expansion of the depletion layer and prevent punch-through even at low substrate concentrations. shall be.

[0007]

SUMMARY OF THE INVENTION In a semiconductor device according to the present invention, an insulating region is provided in a channel region near a source diffusion layer region.

[0008] Furthermore, in the method of manufacturing a semiconductor device according to the present invention, in the normal MOSFET manufacturing process, after forming the gate electrode, oxygen ions are irradiated diagonally with respect to the main surface of the semiconductor substrate using the gate electrode and the insulating film as a mask. The method includes a step of implanting while rotating the wafer, and an insulating region is formed in the channel region near the source diffusion layer region.

[0009]

In the present invention, since the insulating region is provided in the channel region near the source diffusion layer region, it is possible to prevent the drain depletion layer from extending toward the source side, which is a cause of punch-through.

Further, in the step of ion-implanting oxygen in the present invention, the ions are implanted obliquely after forming the gate electrode, so that an insulating region can be formed within the channel region.

[0011]

[Embodiment] FIG. 1 is a process cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. The same reference numerals as in FIG. It is an insulating buried layer (insulating region) embedded in a type semiconductor substrate (channel region).

Next, the manufacturing method will be explained. Figure 1 (a
), first, a P-type silicon substrate 1 is prepared in the same way as in the conventional method.
A gate oxide film 2 and a LOCOS oxide film 3 for element isolation are formed thereon. After that, a gate electrode 4 is formed and CVD
An insulating film 5 such as an oxide film deposited by a method is formed on the gate electrode 4 and separated from the gate electrode 4 by a certain distance. Next, as shown in FIG. 1(b), using the insulating film 5 and the gate electrode 4 as a mask, the silicon substrate 1 is tilted at an angle of 45 degrees as shown by the arrow 6 with respect to the main surface of the silicon substrate 1. While rotating, oxygen ions are implanted at a dose of, for example, 10<17 >cm<-2> and a dose energy of 100 KeV. Next, in an electric furnace at 1350℃, N
2 Heat treatment is performed in an atmosphere for 6 hours to combine oxygen with silicon, forming an insulating buried layer 7 (
oxide film). Next, as shown in FIG. 1(c), the insulating film 5 is removed, and an N-type impurity such as arsenic is implanted from the direction of the arrow 8 using the gate electrode 4 as a mask to form the N+ source diffusion layer region 9 and the N+ drain diffusion. A layer region 10 is formed.

Next, the operation will be explained. A positive potential is applied to the drain diffusion layer region 10 with reference to the potential of the source diffusion layer region 9 . If the potential of the gate electrode 4 is equal to the potential of the source diffusion layer region 9, no current will flow between the source and drain, but if the gate electrode 4 has a positive potential and the channel of the n-type inversion layer is formed between the source and drain. When is formed, current flows. At this time, the expansion of the depletion layer on the drain side stops at the insulating film layer 7 and does not extend toward the source diffusion layer side. Therefore, the punch-through phenomenon in which the source and drain are connected by a depletion layer and current flows regardless of the potential of the gate electrode 4 can be suppressed.

According to this embodiment, after the gate electrode 4 is formed, the insulating film 5 is deposited except in the vicinity of the gate electrode 4, and oxygen ions are obliquely implanted using the insulating film 5 and the gate electrode 4 as a mask. Since the insulating buried layer 7 is provided in the channel region, the extension of the drain depletion layer is suppressed by the insulating buried layer 7, and punch-through can be suppressed even with a low concentration substrate even if the gate length is short. .

Although the above embodiment shows a structure in which the source and drain have a single concentration, in order to prevent the short channel effect, the channel region under the gate, the source, and
LDD (Lightly Doped Drain) in which an intermediate concentration layer of these concentrations is provided between the gate region and the gate region.
Similar effects can be achieved even if the structure is different.

Furthermore, although oxygen ions were implanted into the P-type silicon substrate 1 to form the insulating buried layer, the material for forming the insulating buried layer is not limited to this. Any substance that can be formed may be used.

Further, in the above embodiment, the insulating buried layer 7 is formed near both the source and the drain, but the insulating buried layer 7 may be formed only near the source.

[0018] Furthermore, in the above embodiment, the N-ch MOSFE
Although the example of T is shown, it goes without saying that the same effect can be achieved in the case of P-ch MOSFET.

[0019]

[Effects of the Invention] As described above, according to the present invention, since an insulating region is formed in the channel region by performing ion implantation in an oblique direction while rotating the silicon substrate, the drain depletion layer can be expanded even if the gate length is short. is stopped by this insulating buried layer, and the punch-through phenomenon does not occur. As a result, the substrate concentration does not need to be as high as in the conventional structure, and it is necessary to form a thin oxide film to adjust the threshold voltage to a constant value. This has the effect of eliminating the need for a complicated manufacturing process.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a semiconductor device and a method for manufacturing the same according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a conventional semiconductor device and its manufacturing method.

[Explanation of symbols]

1 P-type substrate 2 Gate oxide film 3 Field oxide film 4 for element isolation
Gate electrode 5 Insulating film 7 Insulating buried layer (insulating region) 9 N+ source region 10 N+ drain region

Claims (2)

[Claims] 1. In a MOS type semiconductor device in which a source/drain diffusion layer region is formed on a substrate, and a gate electrode is formed between the source/drain diffusion layer region with an insulating film interposed therebetween, the source/drain diffusion layer region is 1. A semiconductor device comprising an insulating region within a channel region of the semiconductor device. 2. A method for manufacturing a MOS type semiconductor device comprising forming source/drain diffusion layer regions on a substrate and forming a gate electrode between the source/drain diffusion layer regions with an insulating film interposed therebetween. After forming a gate electrode and source/drain diffusion layer regions above the main surface of the semiconductor substrate, forming an insulating film selectively on the semiconductor substrate except in the vicinity of the gate electrode; 1. A method of manufacturing a semiconductor device, comprising the step of performing ion implantation while rotating the semiconductor substrate from a direction oblique to the main surface to form an insulating region in a channel region near the source diffusion layer region.