JPH06151452A - Manufacture of mos semiconductor device - Google Patents

Abstract

PURPOSE:To obtain the manufacturing method of a MOS semiconductor device having a DI-LDD structure in which the fluctuation of the threshold or deterioration of the current driving ability is suppressed or a pocket structure. CONSTITUTION:The title method involves a process for forming a gate insulating film 3 on a P-type semiconductor substrate 1 and P-type channel impurity area 4 in a channel area, process for forming a gate electrode 5 and N-type low- concentration LDD diffusion layer 6 by using the electrode 5 as a mask, process for forming side walls 7 on both sides of the electrode 5 and P-type punch- through stopper areas 8 by using the walls 7 as masks, and process for forming an N-type high-concentration source-drain areas 9. Since the side walls 7 are utilized for injection at the time of forming the stopper areas 8, the influence of the areas 8 to the impurity area 4 can be prevented and the fluctuation of the threshold or deterioration of the current driving ability can be prevented.

Description

Detailed Description of the Invention [Industrial applications]

The present invention relates to a method of manufacturing a MOS semiconductor device, and more particularly to a method of manufacturing a DI-LDD or a MOS semiconductor device having a pocket structure.

[0002]

2. Description of the Related Art In recent years, a processing size of a gate electrode of a MOS type semiconductor device (generally, it is often formed of polycrystalline silicon doped with a high concentration of impurities) is a so-called submicron of 1.0 μm or less. Has become normal. In the MOS type semiconductor device having such a fine gate length, the distance between the source / drain regions, which is a high-concentration impurity diffusion layer, is also reduced, so that leakage due to the punch-through current between the source / drain when 0V is applied to the gate electrode. There are problems such as an increase in current and a decrease in threshold voltage due to the electric field in the drain affecting the electric field in the channel region.

Various structural measures have been taken against such problems, but in the MOS semiconductor device shown in FIG. 3, impurities of the opposite conductivity type to the source / drain are introduced into the semiconductor substrate by ion implantation. By doing so, an impurity diffusion layer having a higher concentration than that of the semiconductor substrate is formed so as to surround the source / drain and the LDD diffusion layer, the depletion layer is prevented from extending from the drain diffusion layer, and leakage due to punch-through between the source and drain is caused. The current is reduced and the influence of the electric field of the source / drain on the channel region is reduced.

That is, a device region is defined by a field oxide film 2 on a P-type silicon substrate 1, a gate oxide film 3 is formed in the device region, and a gate electrode 5 is further formed thereon.
Sidewall oxide films 7 are formed on both sides of the gate electrode 5. Further, a source / drain is formed on the P-type silicon substrate 1, and the source / drain is an N-type low concentration L-type.
DD diffusion layer 6 and P type punch through stopper region 8
And an N-type high-concentration source / drain diffusion layer 9. Further, a P-type channel impurity region 4 is formed between the source and drain. The structure of such a MOS type semiconductor device is based on a DI-LDD (Donble Implanted-LD
D) or called a pocket structure.

FIGS. 4A to 4C show a conventional DI-LD.
6 shows a method of manufacturing an N-channel MOS type semiconductor device having a D structure in the order of steps. First, as shown in FIG. 4A, a silicon selective oxidation method (L
After the field oxide film 2 is formed by the OCOS method) and then the gate oxide film 3 is formed, impurities for determining the gate threshold voltage of the MOS type semiconductor device, for example, boron are ion-implanted into the entire channel region to form a channel. Impurity region 4 is formed. Further, the gate electrode 5 is formed of polycrystalline silicon that is highly doped with N-type impurities such as phosphorus.

Next, as shown in FIG. 4B, the gate electrode 5
Is used as a mask to ion-implant boron as a P-type impurity having the same conductivity type as that of the P-type silicon substrate 1 to form a punch-through stopper region 8. The energy at the time of ion implantation is selected so that the peak concentration does not overlap with the LDD diffusion layer and is shallower than the source / drain diffusion layer. Further, the dose amount is set to be higher than that of the P-type semiconductor substrate 1. Next, as shown in FIG. 4C, the LDD diffusion layer 6 is formed by vertically ion-implanting phosphorus as an impurity of the same conductivity type as the source / drain into the semiconductor substrate using the gate electrode 5 as a mask. .

After that, as shown in FIG. 3, a silicon oxide film is deposited by the CVD method and etched back to form a side wall 7 of the silicon oxide film only on the side surface of the gate electrode 5. Then, using the gate electrode 5 and the side wall 7 of the silicon oxide film as a mask, N-type impurities such as arsenic are removed by 1
Semiconductor substrate 1 with high dose of × 10 ¹⁵ cm ^-2 to 1 × 10 ¹⁶ cm ^-2
A high concentration source / drain diffusion layer 9 is formed by introducing it into the inside.

[0008]

DISCLOSURE OF THE INVENTION The conventional MOS described above
In the type semiconductor device, since the ion implantation for forming the punch-through stopper region 8 is performed using the gate electrode 5 as a mask, the ion-implanted P-type impurity is implanted in the vicinity immediately below the gate electrode 5. Therefore, a part of the impurities implanted by the heat treatment after implantation diffuses to the P-type channel impurity region 4 to increase the impurity concentration of the channel impurity region 4 and change the threshold voltage of the semiconductor device to increase. . This change in threshold voltage is
It becomes more remarkable as the gate length becomes shorter. Further, since the impurity concentration of the channel impurity region 4 is increased, the mobility of carriers moving in the channel is lowered, and the current driving capability of the MOS semiconductor device is lowered. An object of the present invention is to provide a method of manufacturing a MOS semiconductor device having a DI-LDD structure or a pocket structure without affecting the impurity concentration of the channel region.

[0009]

According to the manufacturing method of the present invention, a step of forming a gate insulating film on a semiconductor substrate of one conductivity type and then introducing an impurity of one conductivity type into a channel region to form a channel impurity region. A step of forming a gate electrode on the gate insulating film, and using the gate electrode as a mask to introduce an impurity of an opposite conductivity type at a low concentration to form an LDD diffusion layer; and a sidewall on both sides of the gate electrode. Forming a punch-through stopper region by using the gate electrode and the side wall as a mask to introduce impurities of one conductivity type, and using the gate electrode and the side wall as a mask to increase the concentration of the opposite conductivity type impurity. And forming source / drain regions.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 shows an N channel M formed by the manufacturing method of the present invention.
It is sectional drawing of an OS type semiconductor device. P-type silicon substrate 1
A field oxide film 2 defines an element region, a gate oxide film 3 is formed in the element region, and a gate electrode 5 is further formed thereon. Sidewall oxide films 7 are formed on both sides of the gate electrode 5. Further, the source / drain is formed on the P-type silicon substrate 1, and the source / drain is
The N-type low-concentration LDD diffusion layer 6, the P-type punch-through stopper region 8 formed at a position retracted from the gate electrode 5 side, and the N-type high-concentration source / drain diffusion layer 9 are formed. Composed. Further, a P-type channel impurity region 4 is formed between the source and drain.

Next, a method of manufacturing the MOS type semiconductor device shown in FIG. 1 is shown in FIGS. First, FIG.
As shown in (a), after the field oxide film 2 is selectively formed on the P-type silicon substrate 1, the gate oxide film 3, the P-type channel impurity region 4, and the gate electrode 5 are formed. This manufacturing method is the same as the conventional method shown in FIG. next,
As shown in FIG. 2B, with the gate electrode 5 as a mask, N-type impurities such as phosphorus are added at 30 to 50 KeV, 1 × 10 ¹³ cm ⁻² to 1 × 10 5.
^It is introduced into the P-type silicon substrate 1 by ion implantation with a dose amount of ¹⁴ cm ⁻² to form an N-type low-concentration LDD diffusion layer 6.

Next, as shown in FIG. 2C, a side wall 7 of a silicon oxide film is formed on the side surface of the gate electrode 5 by depositing a CVD oxide film and etching back, and a P for forming a punch through stopper region 8 is formed. Type impurities are ion-implanted. At this time, the implantation angle may be perpendicular to the semiconductor substrate as in the conventional case, but in order to enhance the effect as a punch-through stopper, the implantation angle should be 20 to 30 degrees with respect to the semiconductor substrate. Good. By implanting ions at an implantation angle with respect to the semiconductor substrate, the P-type impurities are further implanted toward the inside of the gate electrode 5. However, the impurity is not implanted into the channel impurity region 4 by the side wall 7 of the oxide film formed on the side surface of the gate. Next, as shown in FIG. 1, after forming the punch-through stopper region 8, arsenic is ion-implanted with a high dose amount using the gate electrode 5 and the side wall 7 as a mask to form an N-type high-concentration source / drain diffusion layer. 9 is formed.

According to this manufacturing method, a MOS type semiconductor device having a DI-LDD structure or a pocket structure having a punch-through stopper region 8 at a position retracted from the gate electrode 5 side with respect to the LDD diffusion layer 6 is manufactured. be able to. In the MOS semiconductor device having this structure, the impurities injected into the silicon substrate 1 to form the punch-through stopper region 8 are not injected into the channel impurity region 4 immediately below the gate electrode 5. , And does not affect the impurity concentration of the channel impurity region 4. As a result, it is possible to prevent the threshold value of the MOS semiconductor device from fluctuating and prevent the current driving capability from decreasing.

[0014]

As described above, according to the present invention, the impurity ion implantation for forming the punch-through stopper region is performed after the side wall is formed on the side surface of the gate electrode. It is possible to manufacture a MOS type semiconductor device in which the impurity concentration of the channel region is not affected and the threshold voltage and carrier mobility do not fluctuate without being injected into the region.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a MOS type semiconductor device manufactured by a manufacturing method of the present invention.

FIG. 2 is a cross-sectional view showing a method of manufacturing the semiconductor device of FIG. 1 in process order.

FIG. 3 is a cross-sectional view of an example of a conventional MOS semiconductor device having a DI-LDD structure.

4A to 4D are cross-sectional views showing a method of manufacturing the semiconductor device of FIG. 3 in order of steps.

[Explanation of symbols]

 1 P-type silicon substrate 2 Field oxide film 3 Gate oxide film 4 Channel impurity region 5 Gate electrode 6 LDD diffusion layer 7 Side wall 8 Punch through stopper region 9 Source / drain diffusion layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 7377-4M H01L 29/78 301 P

Claims (1)

[Claims] 1. A step of forming a channel impurity region by introducing an impurity of one conductivity type into a channel region after forming a gate insulating film on a semiconductor substrate of one conductivity type, and forming a gate electrode on the gate insulating film. After being formed, the gate electrode is used as a mask to introduce impurities of the opposite conductivity type into a low concentration and
Forming a DD diffusion layer, forming sidewalls on both sides of the gate electrode, introducing impurities of one conductivity type by using the gate electrode and the sidewall as a mask, and forming a punch-through stopper region; And a step of forming a source / drain region by introducing impurities of opposite conductivity type at high concentration using the electrodes and the sidewalls as a mask.
A method for manufacturing an OS type semiconductor device.