KR100265851B1 - Method for fabricating mosfet of semiconductor device - Google Patents
Method for fabricating mosfet of semiconductor deviceInfo
- Publication number
- KR100265851B1 KR100265851B1 KR1019960076267A KR19960076267A KR100265851B1 KR 100265851 B1 KR100265851 B1 KR 100265851B1 KR 1019960076267 A KR1019960076267 A KR 1019960076267A KR 19960076267 A KR19960076267 A KR 19960076267A KR 100265851 B1 KR100265851 B1 KR 100265851B1
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- South Korea
- Prior art keywords
- semiconductor substrate
- gate electrode
- source
- region
- ion implantation
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 title claims abstract description 14
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 26
- 238000005468 ion implantation Methods 0.000 claims abstract description 20
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 230000005669 field effect Effects 0.000 claims abstract description 14
- 239000012535 impurity Substances 0.000 claims abstract description 12
- 150000002500 ions Chemical class 0.000 claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 230000000694 effects Effects 0.000 abstract description 7
- -1 nitrogen ions Chemical class 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 2
- 229920005591 polysilicon Polymers 0.000 abstract description 2
- 125000006850 spacer group Chemical group 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체 장치의 전계효과트랜지스터 제조방법에 관한 것으로, 특히 0.25㎛ 이하의 채널 길이를 갖는 고집적 소자에서의 단채널 효과(Short Channel Effect)를 효과적으로 제거할 수 있는 전계효과트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor manufacturing method of a semiconductor device, and more particularly, to a field effect transistor manufacturing method capable of effectively removing short channel effects in a highly integrated device having a channel length of 0.25 μm or less. .
일반적으로, 반도체 소자가 점차 고집적화되어감에 따라 단채널 효과를 억제함과 동시에 매우 얕으면서 매우 높은 농도의 불순물을 갖는 소오스, 드레인 접합의 형성이 요구되고 있다.In general, as semiconductor devices become increasingly integrated, short source effects are suppressed, and source and drain junctions having very shallow and very high concentrations of impurities are required.
도1은 종래 기술에 따른 반도체 장치의 전계효과트랜지스터 제조 공정 단면도로, 이는 P형 전계효과트랜지스터 제조 공정을 도시한 것이다.1 is a cross-sectional view of a field effect transistor manufacturing process of a semiconductor device according to the prior art, which illustrates a P-type field effect transistor manufacturing process.
먼저, 반도체 기판(1)상에 N-웰(도시하지 않음), 게이트 산화막(2) 및 게이트 전극(3) 패턴을 형성한 후, LDD(Lightly Doped Drain)방식에 의해 저농도 이온 주입(p-) 공정을 실시하여 저농도 이온주입 영역(5)을 형성한다.First, an N-well (not shown), a gate oxide film 2 and a gate electrode 3 pattern are formed on the semiconductor substrate 1, and then low concentration ion implantation (p − ) is performed by a lightly doped drain (LDD) method. ) To form a low concentration ion implantation region (5).
이어서, 전체구조 상부에 산화막을 형성하고, 비등방성 전면식각에 의해 상기 게이트 전극(3) 측벽에 산화막 스페이서(4)를 형성한 후, 고농도 이온 주입(p+)공정을 실시하여 고농도 이온주입 영역(6)을 형성한 다음, 열처리(Anneal)한다.Subsequently, an oxide film is formed on the entire structure, an oxide spacer 4 is formed on the sidewall of the gate electrode 3 by anisotropic front etching, and then a high concentration ion implantation region (p + ) is performed. (6) is formed, and then heat treated (Anneal).
그러나, 이때 상기 저농도 이온주입 영역(p-)(5)과 고농도 이온주입 영역(p+)(6)의 깊이(Depth)는 0.1㎛ 내지 0.3㎛ 정도로 매우 깊으므로 단채널 효과에 매우 취약하며 특히, P형 전계효과트랜지스터의 경우 보론의 불순물의 프로파일(Profile)이 심하고 높은 확산성(Diffusibility)이 문제가 되어 N형 전계효과트랜지스터에 비해 취약하다.However, the depth of the low concentration ion implantation region (p − ) 5 and the high concentration ion implantation region (p + ) 6 is very deep, such as 0.1 μm to 0.3 μm, and thus is particularly vulnerable to short channel effects. In the case of P-type field effect transistors, the boron impurity profile is severe and high diffusibility is a problem, which is weaker than that of N-type field effect transistors.
이를 극복하기 위해서 낮은 에너지(Low Energy)로 이온주입 하는 방법이나 카운터(Counter) 도핑방법 등을 이용하고 있으나, 전체적인 공정이 매우 복잡해지고 저항이 증가하며 접합 캐패시턴스(Junction Capacitance)가 증가하는 등의 문제점이 있었다.In order to overcome this problem, low energy ion implantation method or counter doping method is used, but the overall process becomes very complicated, the resistance increases, and the junction capacitance increases. There was this.
상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 단채널 효과(Short Channel Effect)를 효과적으로 제거함과 동시에 얕으면서도 높은 농도의 불순물을 갖는 소오스, 드레인 접합을 형성할 수 있는 전계효과트랜지스터 제조방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems provides a field effect transistor manufacturing method capable of forming a source, drain junction having a shallow but high concentration of impurities while effectively removing the short channel effect (Short Channel Effect). Its purpose is to.
제1도는 종래기술에 따른 반도체 장치의 전계효과트랜지스터 제조 공정 단면도,1 is a cross-sectional view of a field effect transistor manufacturing process of a semiconductor device according to the prior art,
제2a도 내지 제2c도는 본 발명의 일실시예에 따른 반도체 장치의 전계효과트랜지스터 제조 공정 단면도.2A to 2C are cross-sectional views of a field effect transistor manufacturing process of a semiconductor device according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 반도체 기판 20 : 필드 산화막10 semiconductor substrate 20 field oxide film
30 : 패드 산화막 40 : 게이트 산화막30: pad oxide film 40: gate oxide film
50 : 게이트 전극 60 : 산화막 스페이서50 gate electrode 60 oxide film spacer
70 : n+이온주입 영역 80 : 저농도 이온주입 영역70: n + ion implantation region 80: low concentration ion implantation region
90 : 고농도 이온주입 영역90 high concentration ion implantation region
상기 목적을 달성하기 위하여 본 발명은 반도체 기판상에 패드 산화막을 형성하는 제1단계; 후속 공정에서 채널 영역 및 소오스, 드레인 영역이 형성될 반도체 기판에 질소를 이온주입하는 제2 단계; 상기 패드 산화막을 제고하는 제3 단계; 전체구조 상부에 게이트 절연막 및 게이트 전극을 형성하는 제4 단계; 상기 질소와 반대 도전형의 불순물을 이온주입하여 상기 게이트 전극 양단의 상기 반도체 기판내에 소오스, 드레인 영역을 형성하는 제5 단계; 및 상기 게이트 전극 및 소오스, 드레인 영역에 질소를 이온주입하는 제6 단계를 포함하는 반도체 장치의 전계효과트랜지스터 제조 방법을 제공한다.The present invention to achieve the above object is a first step of forming a pad oxide film on a semiconductor substrate; A second step of ion implanting nitrogen into a semiconductor substrate in which a channel region, a source, and a drain region are to be formed in a subsequent process; A third step of enhancing the pad oxide layer; Forming a gate insulating film and a gate electrode over the entire structure; A fifth step of forming a source and a drain region in the semiconductor substrate across the gate electrode by ion implantation of impurities opposite to the nitrogen; And a sixth step of ion implanting nitrogen into the gate electrode, the source, and the drain region.
이하 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도2a내지 도2c는 본 발명의 일실시예에 따른 반도체 장치의 전계효과트랜지스터 제조 공정 단면도로, P형 전계효과트랜지스터 제조 공정을 도시한 것이다.2A to 2C are cross-sectional views of a field effect transistor manufacturing process of a semiconductor device according to an embodiment of the present invention, which illustrates a P-type field effect transistor manufacturing process.
먼저, 도2a는 N-웰(도시하지 않음)이 기형성된 반도체 기판(10)상에 필드 산화막(20)을 형성하고, 이후의 질소 이온 이온주입 공정시 기판이 스트레스(Stress) 받는 것을 방지하기 위하여 전체구조 상부에 패드 산화막(30)을 형성한 후, 채널 영역 및 소오스, 드레인 영역이 형성될 반도체 기판(10)에 대해 약 5×1014 ions/㎠ v내지 10×1014 ions/㎠ 정도의 도즈(Dose)량으로 질소 이온을 이온주입하여 n+이온주입 영역(70)을 형성한 것을 도시한 것이다.First, FIG. 2A illustrates forming a field oxide film 20 on a semiconductor substrate 10 on which an N-well (not shown) is already formed, and preventing the substrate from being stressed during a subsequent nitrogen ion ion implantation process. In order to form the pad oxide layer 30 over the entire structure, the semiconductor substrate 10 on which the channel region, the source, and the drain region are to be formed is about 5 × 10 14 ions / cm 2 v to 10 × 10 14 ions / cm 2 the dose of the ion implantation of nitrogen ions (dose) amounts shows that the formation of the n + ion implanted region 70.
이어서, 도2b는 상기 패드 산화막(30)을 제거하고, 전체구조 상부에 게이트 산화막(40), 게이트 전극용 폴리실리콘막을 형성한 후, 게이트 전극용 마스크를 사용한 식각 공정에 의해 상기 게이트 전극(50)을 형성한 다음, LDD 구조의 소오스, 드레인 영역 형성을 위해 질소와 반대 도전형의 불순물을 저농도로 이온주입하여 저농도 이온주입 영역(80)을 형성한 것을 도시한 것이다.Subsequently, in FIG. 2B, the pad oxide film 30 is removed, the gate oxide film 40 and the polysilicon film for the gate electrode are formed on the entire structure, and the gate electrode 50 is etched by an etching process using a mask for the gate electrode. ), And then a low concentration ion implantation region 80 is formed by ion implantation of impurities opposite to nitrogen at low concentrations to form a source and drain region of the LDD structure.
마지막으로, 도2c는 전체구조 상부에 산화막을 증착하고, 마스크없이 전면 식각하여 상기 게이트 전극(50) 측벽에 산화막 스페이서(60)를 형성한 후, 질소와 반대 도전형의 불순물을 고농도로 이온주입하여 고농도 이온주입 영역(90)을 형성하여 LDD 구조의 소오스, 드레인 영역(80, 90)을 형성한 다음, 상기 게이트 전극(50) 및 LDD 구조의 소오스, 드레인 영역(80, 90)에 약 5×1014 ions/㎠ 내지 10×1014 ions/㎠ 정도의 도즈(Dose)량으로 질소를 이온주입하고, 열처리(Anneal)한 것을 도시한 것이다.Lastly, in FIG. 2C, an oxide film is deposited on the entire structure, and the entire surface is etched without a mask to form the oxide spacer 60 on the sidewall of the gate electrode 50, and then ion implantation with high concentration of impurities opposite to nitrogen is performed. To form a high concentration ion implantation region 90 to form source and drain regions 80 and 90 of the LDD structure, and then to the source and drain regions 80 and 90 of the gate electrode 50 and the LDD structure. × 10 14 ions / ㎠ to the 10 × 10 14 ions / ion-implantation of nitrogen with a dose (dose) amount of ㎠ degree, showing that the heat treatment (Anneal).
이때, 점선은 상기 게이트 전극(50) 및 LDD 구조의 소오스, 드레인 영역에 질소 이온이 이온주입된 것을 나타낸다.In this case, the dotted line indicates that the ion ion is implanted into the source and drain regions of the gate electrode 50 and the LDD structure.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.
상기와 같이 이루어지는 본 발명은 0.25㎛ 이하의 채널 길이를 갖는 전계효과트랜지스터에 있어서 채널 영역, 게이트 전극 및 소오스, 드레인 영역에 대해 N형 불순물인 질소 이온을 이온주입함으로써, 인터페이스 영역을 최소화할 수 있고, P형 불순물인 보론의 확산도를 크게 떨어뜨려 임계 전압이 변화하는 것을 방지함과 동시에 매우 얕으면서도 높은 농도의 불순물을 갖는 소오스, 드레인 접합을 형성할 수 있어 효과적으로 단채널 효과(Short Channel Effect)를 억제할 수 있다.According to the present invention as described above, in the field effect transistor having a channel length of 0.25 μm or less, by implanting nitrogen ions, which are N-type impurities, into the channel region, the gate electrode, the source, and the drain region, the interface region can be minimized. By reducing the diffusion of boron, which is a P-type impurity, it is possible to prevent the threshold voltage from changing and to form a source / drain junction having a very shallow but high concentration of impurities, effectively reducing the short channel effect. It can be suppressed.
Claims (2)
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| KR1019960076267A KR100265851B1 (en) | 1996-12-30 | 1996-12-30 | Method for fabricating mosfet of semiconductor device |
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| KR1019960076267A KR100265851B1 (en) | 1996-12-30 | 1996-12-30 | Method for fabricating mosfet of semiconductor device |
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| KR19980056997A KR19980056997A (en) | 1998-09-25 |
| KR100265851B1 true KR100265851B1 (en) | 2000-09-15 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR960019613A (en) * | 1994-11-09 | 1996-06-17 | 기다오까 다까시 | Semiconductor device having MOS transistor and manufacturing method thereof |
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR960019613A (en) * | 1994-11-09 | 1996-06-17 | 기다오까 다까시 | Semiconductor device having MOS transistor and manufacturing method thereof |
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| KR19980056997A (en) | 1998-09-25 |
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