KR0156154B1 - Method of fabricating mosfet - Google Patents
Method of fabricating mosfet Download PDFInfo
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- KR0156154B1 KR0156154B1 KR1019950046839A KR19950046839A KR0156154B1 KR 0156154 B1 KR0156154 B1 KR 0156154B1 KR 1019950046839 A KR1019950046839 A KR 1019950046839A KR 19950046839 A KR19950046839 A KR 19950046839A KR 0156154 B1 KR0156154 B1 KR 0156154B1
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- 238000004519 manufacturing process Methods 0.000 title abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 150000002500 ions Chemical class 0.000 claims abstract description 22
- 239000012535 impurity Substances 0.000 claims abstract description 18
- 238000010438 heat treatment Methods 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 8
- 238000005468 ion implantation Methods 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 239000000969 carrier Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000004151 rapid thermal annealing Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- -1 boron ions Chemical class 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- KPSZQYZCNSCYGG-UHFFFAOYSA-N [B].[B] Chemical compound [B].[B] KPSZQYZCNSCYGG-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- Manufacturing & Machinery (AREA)
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- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 모스트랜지스터에 관한 것으로서, 특히 기판과 고농도 소오스/드레인 영역과의 접합 커패시턴스를 감소시켜 고속동작을 가능하게 한 모스트랜지스터의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to MOS transistors, and more particularly, to a method of manufacturing a MOS transistor which enables high-speed operation by reducing junction capacitance between a substrate and a high concentration source / drain region.
이를 위한 본 발명의 모스트랜지스터의 제조방법은 제1도전형의 기판상에 게이트와 게이트 절연막을 순차적으로 형성하는 공정과, 상기 게이트를 마스크로 기판전면에 제2 도전형의 저농도 불순물 이온을 주입하여 제2도전형의 제1 저농도 소오스 드레인 영역을 형성하는 공정과, 상기 게이트 측면에 측벽 절연막을 형성하는 공정과, 상기 측벽 절연막과 게이트를 마스크로 기판전면에 제2도전형 고농도 불순물 이온을 주입하여 제2 도전형 고농도 소오스/드레인 영역을 형성하는 공정과, 상기 기판전면에 저온 열처리를 하여 제2 도전형의 고농도 소오스/드레인 영역 아래에 제2도전형의 제2저농도 소오스/드레인 영역을 형성하는 공정임을 특징으로 한다.A method of manufacturing a MOS transistor according to the present invention includes the steps of sequentially forming a gate and a gate insulating film on a substrate of a first conductivity type, and injecting low concentration impurity ions of a second conductivity type into the entire surface of the substrate using the gate as a mask Forming a first low concentration source drain region of a second conductivity type, forming a sidewall insulating film on the side of the gate, and implanting a second conductive high concentration impurity ion into the front surface of the substrate using the sidewall insulating film and the gate as a mask Forming a second conductive high concentration source / drain region; and forming a second low concentration source / drain region of the second conductive type under the high concentration source / drain region of the second conductive type by performing a low temperature heat treatment on the entire surface of the substrate. Characterized in that the process.
Description
제1도는 종래의 모스트랜지스터의 제조공정도.1 is a manufacturing process diagram of a conventional morph transistor.
제2도는 본 발명의 모스트랜지스터의 제조공정도.2 is a manufacturing process diagram of the morph transistor of the present invention.
제3도는 기판 깊이대 붕소 농도의 관계를 나타낸 도면.3 shows the relationship between the substrate depth and boron concentration.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1. 실리콘기관 2. 게이트 절연막1. Silicon engine 2. Gate insulating film
3. 게이트 4. 제1저농도 소오스/드레인 영역3. Gate 4. First low concentration source / drain region
5. 측벽 절연막 6. 고농도 소오스/드레인 영역5. Sidewall Insulator 6. High Concentration Source / Drain Area
7. 제2 저농도 소오스/드레인 영역7. Second low concentration source / drain region
본 발명은 모스트랜지스터에 관한 것으로서, 특히 기판과 고농도 소오스/드레인 영역과의 접합 커패시턴스를 감소시켜 고속동작을 가능하게 한 모스트랜지스터의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to MOS transistors, and more particularly, to a method of manufacturing a MOS transistor which enables high-speed operation by reducing junction capacitance between a substrate and a high concentration source / drain region.
모스트랜지스터가 고집적화 됨에 따라 게이트 전국의 에지부분 즉, 드레인 영역에 인접한 채널영역에서 고전계가 형성되어 핫 캐리어가 발생되고, 이 핫 캐리어에 의해 모스트랜지스터의 동작특성 저하 및 수명이 단축되었다.As the MOS transistors are highly integrated, high carriers are formed at edge portions of gate gates, that is, channel regions adjacent to the drain regions, and hot carriers are generated. The hot carriers reduce operational characteristics and shorten the lifetime of the MOS transistors.
이러한 핫 캐리어를 제거하기 위하여, 고농도의 드레인 영역에 인접한 부분의 전계를 소거시켜 주기 위한 저농도의 드레인 영역이 고농도의 드레인 영역과 채널영역 사이에 형성된 LDD(Lightly Doped Drain) 구조가 제안되었다.In order to remove such hot carriers, a lightly doped drain (LDD) structure in which a low concentration drain region is formed between a high concentration drain region and a channel region to erase an electric field of a portion adjacent to the high concentration drain region is proposed.
종래의 LDD 구조의 모스트랜지스터의 제조방법을 구체적으로 설명하면 다음과 같다.The manufacturing method of the conventional MOS transistor of the LDD structure will be described in detail as follows.
제1도는 LDD 구조의 모스트랜지스터의 제조방법을 도시한 제조공정도로써, 제1도 (a)와 같이, 실리콘 기판(1)상에 통상적인 공정에 의해 게이트 절연막(2)과 게이트(3)를 순차형성한 후 상기 게이트(3)를 마스크로 기판내부에 P-형 불순물 이온을 주입하고, 열처리 하여 불순물 이온을 활성화(Activation) 시켜 저농도 소오스/드레인 영역(4)을 형성한다.FIG. 1 is a manufacturing process diagram showing a method of manufacturing an LDD structure morph transistor. As shown in FIG. 1 (a), the gate insulating film 2 and the gate 3 are formed on a silicon substrate 1 by a conventional process. After sequential formation, P − type impurity ions are implanted into the substrate using the gate 3 as a mask, followed by heat treatment to activate impurity ions to form a low concentration source / drain region 4.
제1도 (b)와 같이, 기판전면에 걸쳐 CVD 산화막을 증착하고, 상기 CVD 산화막을 에치백(Etch Back)하여 게이트(3) 양측에 측벽 절연막(5)을 형성한다.As illustrated in FIG. 1B, a CVD oxide film is deposited over the entire surface of the substrate, and the sidewall insulating film 5 is formed on both sides of the gate 3 by etching back the CVD oxide film.
제1도 (c)와 같이, 측벽 절연막(5)과 게이트(3)를 마스크로 P+형 불순물을 기판내에 이온주입하고 고온에서 짧은 시간동안 RTA를 실시하여 이온주입된 불순물을 활성화 시켜 고농도 소오스/드레인 영역(6)을 형성한다.As shown in FIG. 1 (c), a P + type impurity is implanted into the substrate using the sidewall insulating film 5 and the gate 3 as a mask, and RTA is performed at a high temperature for a short time to activate the ion implanted impurity / Drain region 6 is formed.
이때 상기 RTA를 통한 열처리는 P+형 불순물 이온의 격자간(Interstitial) 과도확산(Transient Diffusion)을 효과적으로 제거하여 붕소(Boron)의 접합깊이(Junction Depth)을 줄여주고 소자의 스케일 다운(Scale Down) 및 단채널 효과(Short Channel Effect)의 특성을 개선시킨 LDD형 P형 모스트랜지스터를 제조하였다.At this time, the heat treatment through the RTA effectively removes interstitial transient diffusion of P + type impurity ions, thereby reducing the junction depth of boron and scaling down the device. And LDD type P-type transistors having improved characteristics of short channel effects.
이와 같은, 종래의 LDD 구조의 P형 모스트랜지스터의 제조방법에 있어서는, 스케일 다운 및 단채널 효과 특성이 개선되었으나 P+이온주입 직후 고온에서 짧은 시간동안 RTA(Rapid Thermal Annealing)을 실시한 열처리 조건으로 P+이온과 n형 기판간의 접합 커패시턴스(Junction Capacitance)가 증가하여 소자의 동작속도(Speed)가 저하되는 문제점이 발생하였다.In the conventional manufacturing method of the P-type MOS transistor of the LDD structure, although the scale down and short channel effect characteristics are improved, P under the thermal treatment condition of RTA (Rapid Thermal Annealing) for a short time at high temperature immediately after P + ion implantation is performed. The junction capacitance between the ion and the n-type substrate is increased, resulting in a decrease in the operating speed of the device.
본 발명은 상기한 바와 같은 문제를 해결하기 위한 것으로, P+불순물 이온을 기판내에 주입하여 고농도 소오스/드레인 영역을 활성화(Activation) 시키는 열처리 공정에 있어서, 고온 열처리에 앞서 저온 열처리를 함으로써 P형 불순물 이온을 깊고, 넓게(broad)형성하여 동작속도를 향상한 모스트랜지스터의 제조방법을 제공하는데 그 목적이 있다.The present invention is to solve the problems as described above, in the heat treatment step of activating a high concentration source / drain region by implanting P + impurity ions into the substrate, P-type impurities by low temperature heat treatment prior to high temperature heat treatment It is an object of the present invention to provide a method for manufacturing a morph transistor having a deep and broad ion, thereby improving the operation speed.
상기 목적을 달성하기 위한 본 발명은 제1도전형의 기판상에 게이트와 게이트 절연막을 순차적으로 형성하는 공정과, 상기 게이트를 마스크로 기판전면에 제2도전형의 저농도 불순물 이온을 주입하여 제2도 전형의 제1 저농도 소오스 드레인 엉역을 형성하는 공정과, 상기 게이트 측면에 측벽 절연막을 형성하는 공정과, 상기 측벽 절연막과 게이트를 마스크로 기판전면에 제2도전형 고농도 불순물 이온을 주입하여 제2도전형 고농도 소오스/드레인 영역을 형성하는 공정과, 상기 기판전면에 저온 열처리를 하여 제2도전형의 고농도 소오스/드레인 영역 아래에 제2도전형의 제2저농도 소오스/드레인 영역을 형성하는 공정을 포함하는 것을 특징으로 한다.The present invention for achieving the above object is a step of sequentially forming a gate and a gate insulating film on the substrate of the first conductive type, and by implanting the low concentration impurity ions of the second conductive type on the front surface of the substrate using the gate as a mask Forming a first conductive low concentration source drain inversion, forming a sidewall insulating film on the side of the gate, and implanting a second conductive high concentration impurity ion into the front surface of the substrate using the sidewall insulating film and the gate as a mask; Forming a conductive high concentration source / drain region, and forming a second low concentration source / drain region of the second conductivity type under the high concentration source / drain region of the second conductivity type by performing a low temperature heat treatment on the entire surface of the substrate. It is characterized by including.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 상세히 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제2도 (a)에서와 같이, 실리콘 기판(1)상에 통상적인 공정에 의해 게이트 절연막 (2)과 게이트(3)를 순착적으로 형성한 후 상기 게이트(3)를 마스크로 기판내부에 P-형 불순물 이온을 주입하고 열처리 하여 불순물 이온을 활성화(Activation)하여 제1 저농도 소오스/드레인 영역(4)을 형성한다.As shown in FIG. 2 (a), the gate insulating film 2 and the gate 3 are formed on the silicon substrate 1 by a conventional process, and then the gate 3 is used as a mask in the substrate. The P − type impurity ions are implanted and heat treated to activate the impurity ions to form the first low concentration source / drain region 4.
제2도 (b)에서와 같이, 기판전면에 걸쳐 CVD 산화막을 증착하고, 상기 CVD 산화막을 에치백(Etch Back)하여 게이트(3) 양측에 측벽 절연막(5)을 형성한다.As shown in FIG. 2B, a CVD oxide film is deposited over the entire surface of the substrate, and the sidewall insulating film 5 is formed on both sides of the gate 3 by etching back the CVD oxide film.
제2도 (c)에서와 같이, 측벽 절연막(5)과 게이트(3)를 마스크로 P+형 불순물을 기판내에 주입하여 고농도 소오스/드레인 영역(6)을 형성한다..As shown in FIG. 2 (c), P + type impurities are implanted into the substrate using the sidewall insulating film 5 and the gate 3 as a mask to form a high concentration source / drain region 6.
제2도 (d)에서와 같이, 상기 결과물을 어닐링 장비(도시하지 않음)에 장착한 다음 약 700℃의 저온에서 30분간 열처리 공정을 수행한 후 통상의 고온 열처리를 하면 고농도 소오스/드레인 영역(6) 하부에 제2 저농도 소오스/드레인 영역(7)이 형성된다.As shown in FIG. 2 (d), the resultant is mounted on an annealing equipment (not shown), and then subjected to a heat treatment process at a low temperature of about 700 ° C. for 30 minutes, and then subjected to a normal high temperature heat treatment. 6) A second low concentration source / drain region 7 is formed below.
이를 제3도를 참조하여 설명하면 P형 불순물 이온인 붕수(Boron) 이온을 주입한 후 약 700℃의 저온에서 30분간 열처리(Annealing) 공정을 한 다음 통상의 고온 열처리 공정을 수행하면 붕소(Boron) 이온의 격자간(Interstitial) 과도확산(Transient Diffusion)이 발생하여 기판내의 붕소(Boron) 이온 확산 프로파일이 깊고, 넓게(Broad) 형성된다.Referring to FIG. 3, boron ions, which are P-type impurity ions, are implanted, followed by annealing for 30 minutes at a low temperature of about 700 ° C., followed by boron (Boron). ) Interstitial transient diffusion of ions occurs to form a deep and broad boron ion diffusion profile in the substrate.
특히 기판의 일정깊이에서 붕소(Boron)의 농도차가 급격해져 제2도 (d)에서와 같이, 고농도 소오스/드레인(6) 영역 아래에 제2 저농도 소오스/드레인 영역(7)이 형성됨을 보여준다.In particular, the concentration difference between boron (Boron) at a certain depth of the substrate sharply shows that the second low concentration source / drain region (7) is formed below the high concentration source / drain (6) region, as shown in FIG.
이때 붕소(Boron) 이온대신 BF2이온을 주입하여 소오스/드레인 영역을 형성하여도 같은 효과를 볼 수 있다.In this case, the same effect can be obtained even when source / drain regions are formed by injecting BF 2 ions instead of boron ions.
이상에서와 같이, 본 발명에 의하면 LDD 구조의 모스트랜지스터의 결함중 하나이던 접합 커패시턴스(Junction Capacitance)를 감소하기 위해 소오스/드레인 영역과 기판의 접합상태를 P+/N 접합에서 P-/N 접합으로 형성하여 접합 커패시턴스를 최소화하여 모스트랜지스터의 동작속도를 증가하는 효과가 있다.As described above, according to the present invention, the bonding state of the source / drain region and the substrate in order to reduce the junction capacitance (Junction Capacitance) who was one of the defects of the MOS transistor of the LDD structure in the P + / N junction P - / N junction It is formed to reduce the junction capacitance has the effect of increasing the operating speed of the transistor.
Claims (4)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950046839A KR0156154B1 (en) | 1995-12-05 | 1995-12-05 | Method of fabricating mosfet |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019950046839A KR0156154B1 (en) | 1995-12-05 | 1995-12-05 | Method of fabricating mosfet |
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| Publication Number | Publication Date |
|---|---|
| KR970053075A KR970053075A (en) | 1997-07-29 |
| KR0156154B1 true KR0156154B1 (en) | 1998-12-01 |
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| KR1019950046839A KR0156154B1 (en) | 1995-12-05 | 1995-12-05 | Method of fabricating mosfet |
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| KR (1) | KR0156154B1 (en) |
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1995
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