KR100192364B1 - Method of manufacturing mosfet - Google Patents
Method of manufacturing mosfet Download PDFInfo
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- KR100192364B1 KR100192364B1 KR1019960029212A KR19960029212A KR100192364B1 KR 100192364 B1 KR100192364 B1 KR 100192364B1 KR 1019960029212 A KR1019960029212 A KR 1019960029212A KR 19960029212 A KR19960029212 A KR 19960029212A KR 100192364 B1 KR100192364 B1 KR 100192364B1
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- insulating film
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- gate electrode
- mos transistor
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 23
- 239000012535 impurity Substances 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 8
- 150000004767 nitrides Chemical class 0.000 claims description 7
- 230000001590 oxidative effect Effects 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 abstract description 8
- 239000007790 solid phase Substances 0.000 abstract description 8
- 239000004065 semiconductor Substances 0.000 description 6
- 238000004151 rapid thermal annealing Methods 0.000 description 5
- 239000000969 carrier Substances 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 239000005388 borosilicate glass Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 모스 트랜지스터에 관한 것으로, 특히 한번의 SPD(Solid Phase Diffusion)공정으로 LDD 영역 및 고농도 소오스/드레인 영역을 형성할 수 있는 모스 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor, and more particularly, to a MOS transistor manufacturing method capable of forming an LDD region and a high concentration source / drain region in a single solid phase diffusion (SPD) process.
이를 위한 본 발명의 모스 트랜지스터 제조방법은 도1전형의 기판상에 게이트 절연막 및 게이트 전극을 순차적으로 형성하는 단계, 상기 게이트 전극 및 기판 전면에 제1절연막 및 제2절연막을 차례로 형성하는 단계, 상기 제2절연막 및 제1절연막을 식각하여 측벽 절연막으로 형성하는 단계, 상기 측벽 절연막을 제거하는 단계, 상기 제1절연막 및 게이트전극을 포함한 기판 전면에 도 2전형 불순물 함유층을 형성하는 단계, 상기 기판 전면을 열처리하여 LDD영역 및 고농도 소오스/드레인 영역을 동시에 형성하는 단계를 포함함을 특징으로 한다.In the method of manufacturing the MOS transistor of the present invention for this purpose, the step of sequentially forming a gate insulating film and a gate electrode on the substrate of Figure 1, the step of sequentially forming a first insulating film and a second insulating film on the gate electrode and the front surface of the substrate, Etching the second insulating film and the first insulating film to form a sidewall insulating film; removing the sidewall insulating film; forming a typical impurity-containing layer on the entire surface of the substrate including the first insulating film and the gate electrode; Heat treating the same to form an LDD region and a high concentration source / drain region at the same time.
Description
본 발명은 모스 트랜지스터에 관한 것으로, 특히 한번의 고상확산(SPD : Solid Phase Diffusion)공정으로 LDD 영역 및 고농도 소오스/드레인 영역을 형성할 수 있는 모스 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor, and more particularly, to a MOS transistor manufacturing method capable of forming an LDD region and a high concentration source / drain region in a single solid phase diffusion (SPD) process.
모스 트랜지스터(MOS Transistor)가 고집적화 됨에 따라 게이트 전극의 에지부분 즉, 드레인 영역에 인접한 채널영역에서 고전계가 형성되어 핫 캐리어가 발생되고, 이 핫 캐리어에 의해 모스 트랜지스터의 동작특성 저하 및 수명이 단축되었다.As the MOS transistors are highly integrated, high carriers are formed at the edges of the gate electrodes, that is, in the channel regions adjacent to the drain regions, and hot carriers are generated. The hot carriers reduce operational characteristics and shorten the lifetime of the MOS transistors. .
이러한 핫 캐리어를 제거 하기 위하여 고농도의 드레인 영역에 인접한 부분의 전계를 소거시켜 주기 위한 저농도의 드레인 영역이 고농도의 드레인 영역과 채널영역 사이에 형성된 LDD(Lightly Doped Drain) 구조가 제안되었다.In order to remove such hot carriers, a lightly doped drain (LDD) structure in which a low concentration drain region is disposed between a high concentration drain region and a channel region to erase an electric field of a portion adjacent to a high concentration drain region is proposed.
이하, 첨부된 도면을 참조하여 종래 모스 트랜지스터에 대하여 설명하면 다음과 같다.Hereinafter, a conventional MOS transistor will be described with reference to the accompanying drawings.
제1a도 내지 (e)는 종래 모스 트랜지스터의 제조공정 단면도이다.1A to 1E are cross-sectional views of a manufacturing process of a conventional MOS transistor.
먼저, 제1a도에 나타낸 바와 같이 반도체 기판(1)상에 통상의 필드산화 공정을 실시하여 소자격리용 필드 신화막(2)을 형성한다.First, as shown in FIG. 1A, a normal field oxidation process is performed on the semiconductor substrate 1 to form the field isolation film 2 for device isolation.
그 다음 필드산화막(2) 사이의 활성영역에 채널이온을 주입하여 채널층(3)을 형성하고 기판 표면을 열산화하여 게이트 산화막(4)을 형성한다.Then, channel ions are implanted into the active region between the field oxide films 2 to form the channel layer 3, and the substrate surface is thermally oxidized to form the gate oxide film 4.
제1b도에 나타낸 바와 같이 전면에 폴리실리콘을 증착하고 패터닝(포토리소그래피 공정 + 식각공정)하여 게이트전극(5)을 형성한다.As shown in FIG. 1B, polysilicon is deposited on the entire surface and patterned (photolithography process + etching process) to form the gate electrode 5.
제1c도에 나타낸 바와 같이 전면에 BSG(Boro-Silicate Glass)를 증착하고 RIE(Reactive Ion Etch)법으로 전면을 에치백(Etch Back)하여 산화막 측벽(6)을 형성한다.As shown in FIG. 1C, an oxide sidewall 6 is formed by depositing BSG (Boro-Silicate Glass) on the entire surface and etching back the entire surface by a reactive ion etching (RIE) method.
제1d도에 나타낸 바와 같이 고농도 소오스/드레인 영역 형성을 위해 불순물 이온을 주입한다.As shown in FIG. 1d, impurity ions are implanted to form a high concentration source / drain region.
제1e도에 나타낸 바와 같이 RTA(Rapid Thermal Annealing)을 실시하여 고상확산(SRD : Solid Phase Diffusion)법으로 측벽 산화막(6)의 보론(borron)을 확산하여 LDD 영역(7)을 형성한다.As shown in FIG. 1E, rapid thermal annealing (RTA) is performed to diffuse boron of the sidewall oxide layer 6 by solid phase diffusion (SRD) to form the LDD region 7.
이 때, 고농도 불순물 이온도 같이 확산되어 고농도 소오스/드레인 영역(8)을 형성하였다.At this time, the high concentration impurity ions were also diffused to form the high concentration source / drain region 8.
이상에서와 같이 종래의 모스 트랜지스터에 있어서는 제1a도 내지 (e)에서 나타낸 바와 같이 숏채널 효과(Short Channel Effect)를 개선하기 위해 고상확산법을 사용하여 LDD영역을 형성하고 고농도 불순물 이온주입 공정후 열처리하여 고농도 소오스/드레인 영역을 형성하였다.As described above, in the conventional MOS transistor, in order to improve the short channel effect as shown in FIGS. 1A through 1E, an LDD region is formed by using a solid phase diffusion method, followed by heat treatment after a high concentration impurity ion implantation process. To form a high source / drain region.
종래의 모스 트랜지스터 제조방법에 있어서는 고상확산법과 불순물 이온주입 공정을 실시해야 하므로 공정이 복잡하여 수율향상에 문제점이 있었다.In the conventional MOS transistor manufacturing method, the solid phase diffusion method and the impurity ion implantation process have to be performed, and thus, the process is complicated and there is a problem in yield improvement.
본 발명은 종래와 같은 모스 트랜지스터의 문제점을 해결하기 위하여 안출한 것으로, LDD 영역 및 고농도 불순물 영역을 한번의 고상확산공정으로 형성할 수 있는 모스 트랜지스터의 제조방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the problems of the conventional MOS transistor, and an object of the present invention is to provide a method for manufacturing a MOS transistor capable of forming the LDD region and the high concentration impurity region in one solid phase diffusion process.
제1a도 내지 제1e도는 종래 모스 트랜지스터 제조공정 단면도.1A to 1E are cross-sectional views of a conventional MOS transistor manufacturing process.
제2a도 내지 제2f도는 본 발명에 따른 모스 트랜지스터의 제조공정 단면도.2A to 2F are cross-sectional views of a manufacturing process of a MOS transistor according to the present invention.
*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 반도체 기판 11 : 필드 산화막10 semiconductor substrate 11 field oxide film
12 : 채널층 13 : 제1 게이트 절연막12 channel layer 13 first gate insulating film
14 : 게이트전극 15 : 제2 게이트 절연막14 gate electrode 15 second gate insulating film
16 : 측벽 질화막 17 : 불순물 함유층16 sidewall nitride film 17 impurity containing layer
18 : LDD 영역 19 : 소오스/드레인 영역18: LDD region 19: source / drain region
상기와 같은 목적을 달성하기 위하여 본 발명의 모스 트랜지스터 제조방법은 제1도 전형의 기판상에 게이트 절연막 및 게이트 전극을 순차적으로 형성하는 단계, 상기 게이트 전극 및 기판 전면에 제1절연막 및 제2절연막을 차례로 형성하는 단계, 상기 제2절연막 및 제1절연막을 식각하여 측벽 절연막으로 형성하는 단계, 상기 측벽 절연막을 제거하는 단계, 상기 제1절연막 및 게이트전극을 포함한 기판 전면에 도 2전형 불순물 함유층을 형성하는 단계, 상기 기판 전면을 열처리하여 LDD영역 및 고농도 소오스/드레인 영역을 동시에 형성하는 단계를 포함한다.In order to achieve the above object, the MOS transistor manufacturing method of the present invention includes the steps of sequentially forming a gate insulating film and a gate electrode on a first conductive substrate, and a first insulating film and a second insulating film on the entire surface of the gate electrode and the substrate. Forming a sidewall insulating film by etching the second insulating film and the first insulating film in order, removing the sidewall insulating film, and forming a typical impurity-containing layer on the entire surface of the substrate including the first insulating film and the gate electrode. Forming a LDD region and a high concentration source / drain region at the same time by heat-treating the entire surface of the substrate.
이하에서 첨부된 도면을 참조하여 본 발명에 따른 모스 트랜지스터의 제조방법을 설명하면 다음과 같다.Hereinafter, a manufacturing method of a MOS transistor according to the present invention will be described with reference to the accompanying drawings.
제2a도 내지 (f)는 본 발명에 따른 모스 트랜지스터의 제조공정 단면도이다.2A to 2F are cross-sectional views of a manufacturing process of a MOS transistor according to the present invention.
먼저, 제2a도에 나타낸 바와 같이 반도체 기판(10)상에 통상의 필드산화 공정을 실시하여 소자격리용 필드 산화막(11)을 형성한다.First, as shown in FIG. 2A, a normal field oxidation process is performed on the semiconductor substrate 10 to form a device isolation field oxide film 11.
그 다음 필드 산화막(11) 사이의 활성영역에 채널이온을 주입하여 채널층(12)을 형성하고 기판 표면을 열산화하여 제1 게이트 산화막(13)을 형성한다.Next, channel ions are implanted into the active region between the field oxide films 11 to form the channel layer 12, and the substrate surface is thermally oxidized to form the first gate oxide film 13.
제2b도에 나타낸 바와 같이, 전면에 폴리 실리콘을 증착하고 패터닝(포토리소그래피(Photolithograph)공정 + 식각공정)하여 게이트 전극(14)을 형성한다.As shown in FIG. 2B, polysilicon is deposited on the entire surface and patterned (Photolithograph process + etching process) to form the gate electrode 14.
제2c도에 나타낸 바와 같이 기판 전면을 열산화하여 게이트전극(14) 전면 및 기판상에 제2 게이트 산화막(15)을 형성한다.As shown in FIG. 2C, the entire surface of the substrate is thermally oxidized to form a second gate oxide film 15 on the entire surface of the gate electrode 14 and on the substrate.
이 때, 제2 게이트 산화막(15)은 30~87A의 두께로 형성한다.At this time, the second gate oxide film 15 is formed to a thickness of 30 to 87A.
제2d도에 나타낸 바와 같이 제2 게이트 산화막(15)을 포함한 전면에 질화막을 형성하고 RIE법으로 전면을 에치백하여 측벽 질화막(16)으로 형성한다.As shown in FIG. 2D, a nitride film is formed on the entire surface including the second gate oxide film 15, and the entire surface is etched back to form the sidewall nitride film 16 by RIE.
이 때, 에치백 공정은 기판과 게이트 전극(14)노출될 때까지 실시한다.At this time, the etch back process is performed until the substrate and the gate electrode 14 are exposed.
또한 측벽 질화막(16)이 형성된 영역은 후속공정에서 고상확산법으로 형성하는 LDD영역으로 사용할 영역이다.In addition, the region where the sidewall nitride film 16 is formed is a region to be used as an LDD region to be formed by the solid phase diffusion method in a subsequent step.
제2e도에 나타낸 바와 같이 상기 측벽 질화막(16)을 선택적으로 제거하고 제2 게이트 산화막(15) 및 게이트 전극(14)을 포함한 기판 전면에 불순물 함유층(17)을 증착한다.As shown in FIG. 2E, the sidewall nitride film 16 is selectively removed, and the impurity containing layer 17 is deposited on the entire surface of the substrate including the second gate oxide film 15 and the gate electrode 14.
이 때, 불순물 함유층(17)은 기판과 반대도전형으로 형성한다.At this time, the impurity-containing layer 17 is formed in the opposite conductivity type to the substrate.
즉, 반도체 기판(10)이 p형 기판일 경우 n형 불순물 함유층을 형성한다.That is, when the semiconductor substrate 10 is a p-type substrate, an n-type impurity containing layer is formed.
예로써 PSG(Phospho-Silicate Glass)층을 형성할 수 있다.For example, a phos-silicate glass (PSG) layer may be formed.
또한 반도체 기판(10)이 n형 기판일 경우 p형 불순물 함유층을 형성한다.In addition, when the semiconductor substrate 10 is an n-type substrate, a p-type impurity-containing layer is formed.
예로써, PSG(Phospho-Silicate Glass)층을 형성할 수 있다.For example, a Phospho-Silicate Glass (PSG) layer may be formed.
이 때, 불순물 함유층(17)의 불순물 농도는 1019~1023이며 불순물 함유층 (17)은 500~3000A의 두깨를 갖도록 형성한다.At this time, the impurity concentration of the impurity-containing layer 17 is 10 19 to 10 23 and the impurity-containing layer 17 is formed to have a thickness of 500 to 3000A.
제2f도에 나타낸 바와 같이, 기판 전면에 RTA(Rapid Thermal Annealing)를 실시하여 불순물 함유층(17)의 불순물을 활성화(Activation)하여 반도체 기판(10)내로 확산시킨다.As shown in FIG. 2F, Rapid Thermal Annealing (RTA) is applied to the entire surface of the substrate to activate impurities in the impurity-containing layer 17 to diffuse into the semiconductor substrate 10.
즉, 고상확산(SPD : Solid Phase Diffusion)법을 사용하여 동시에 LDD영역(18) 및 고농도 소오스/드레인 영역(19)을 형성하는 것이다.That is, the LDD region 18 and the high concentration source / drain region 19 are formed at the same time by using a solid phase diffusion (SPD) method.
이 때, 측벽 질화막(16)이 형성되었던 게이트전극(14)양측면 하부의 LDD 영역(18)은 제2 게이트 산화막(15)으로 인해 확산(Diffusion)이 지연되어 LDD 영역(18)으로 형성하는 것으로 셀프 얼라인(Self Align)으로 형성됨을 알 수 있다.At this time, the LDD region 18 under both sides of the gate electrode 14 on which the sidewall nitride layer 16 was formed is delayed due to the second gate oxide layer 15 to form the LDD region 18. It can be seen that it is formed by Self Align.
그리고 RTA의 조건은 900℃~1300℃의 온도에서 5~60sec이다.The conditions of the RTA are 5 to 60 sec at a temperature of 900 ° C to 1300 ° C.
본 발명의 모스트랜지스터에 있어서도 LDD영역과 고농도 소오스/드레인 영역을 한번의 공정으로 동시에 형성할 수 있어 제작수율을 향상할 수 있는 효과가 있다.Also in the morph transistor of the present invention, the LDD region and the high concentration source / drain region can be simultaneously formed in one process, thereby improving the production yield.
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