KR960008736B1 - Mosfet and the manufacturing method thereof - Google Patents
Mosfet and the manufacturing method thereof Download PDFInfo
- Publication number
- KR960008736B1 KR960008736B1 KR1019930003733A KR930003733A KR960008736B1 KR 960008736 B1 KR960008736 B1 KR 960008736B1 KR 1019930003733 A KR1019930003733 A KR 1019930003733A KR 930003733 A KR930003733 A KR 930003733A KR 960008736 B1 KR960008736 B1 KR 960008736B1
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- polysilicon
- forming
- ldd region
- gate electrode
- mosfet
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- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000012535 impurity Substances 0.000 claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 21
- 229920005591 polysilicon Polymers 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 125000006850 spacer group Chemical group 0.000 claims abstract description 10
- 238000000137 annealing Methods 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims abstract 2
- 238000005530 etching Methods 0.000 claims abstract 2
- 238000000034 method Methods 0.000 claims description 12
- 238000005468 ion implantation Methods 0.000 abstract description 5
- 230000005684 electric field Effects 0.000 description 10
- 239000000969 carrier Substances 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
Abstract
Description
제1a도 내지 제1c도는 종래 기술에 따른 모스펫트의 제조 단계를 도시한 단면도.1a to 1c is a cross-sectional view showing the manufacturing step of the MOSFET according to the prior art.
제2a도 내지 제2d도는 본 발명에 따른 모스펫트의 제조 단계를 도시한 단면도.2a to 2d are cross-sectional views showing the manufacturing step of the MOSFET according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체 기판 2 : 게이트 산화막1 semiconductor substrate 2 gate oxide film
3 : 게이트 전극 4 : 저농도 불순물3: gate electrode 4: low concentration impurity
5 : LDD 영역 6 : 절연층5: LDD region 6: insulation layer
6' : 절연층 스페이서 7 : 고농도 불순물6 ': insulating layer spacer 7: high concentration impurity
8 : 소오스/드레인 영역 11 : 산화막8 source / drain region 11 oxide film
12 : 폴리실리콘층 12' : 폴리실리콘 스페이서12 polysilicon layer 12 'polysilicon spacer
13 : 얕은 접합13: shallow junction
본 발명은 반도체 소자인 모스 전계 효과 트랜지스터(Metal Oxide Semiconductor Field Effect Transistor; 이하, MOSFET라 칭함) 및 그 제조 방법에 관한 것으로, 핫 캐리어(Hot Carrier)의 발생을 억제시키기 위하여 엘.디.디(Lightly Doped Drain; 이하 LDD라 칭함) 영역에 다른 타입의 불순물로 된 얕은 접합을 형성시키는 MOSFET 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a metal oxide semiconductor field effect transistor (hereinafter referred to as a MOSFET) and a method for manufacturing the same, and to suppress the occurrence of hot carriers. The present invention relates to a MOSFET for forming a shallow junction of different types of impurities in a lightly doped drain (LDD) region and a method of manufacturing the same.
MOSFET에 전류가 흐를 때 발생되는 핫 캐리어를 억제하기 위한 종래 기술의 대표적인 것은 소오스/드레인 영역을 LDD 구조로 형성하는 것이다.A representative of the prior art for suppressing hot carriers generated when current flows through a MOSFET is to form a source / drain region in an LDD structure.
LDD 구조를 형성하는 방법을 제1a도 내지 제1c도를 참조하여 설명하면 다음과 같다.A method of forming the LDD structure will be described with reference to FIGS. 1A to 1C.
제1a도는 반도체 기판(1) 상부에 게이트 산화막(2)과 폴리실리콘층 패턴으로 된 게이트 전극(3)을 형성하고, 상기 게이트 전극(3) 양측의 반도체 기판(1)에 저농도 불순물(4)을 이온 주입하여 LDD 영역(5)을 형성한 상태를 도시한 단면도이다.FIG. 1A shows a gate electrode 3 having a gate oxide film 2 and a polysilicon layer pattern formed on the semiconductor substrate 1, and low concentration impurities 4 on the semiconductor substrate 1 on both sides of the gate electrode 3. Is a cross-sectional view showing a state in which the LDD region 5 is formed by ion implantation.
제1b도는 상기 제1a도의 공정후, 전체적으로 산화막 등의 절연층(6)을 형성한 단면도이다.FIG. 1B is a sectional view in which an insulating layer 6 such as an oxide film is formed as a whole after the process of FIG. 1A.
제1c도는 상기 절연층(6)을 전면 이방성 식각하여 게이트 전극(3)과 게이트 산화막(2)의 측벽에 절연층 스페이서(6')를 형성한 다음, 게이트 전극(3) 양측의 반도체 기판(1)에 고농도 불순물(7)을 이온 주입하여 LDD 영역(5)을 남기면서 소오스/드레인(8)을 형성한 단면도이다.In FIG. 1C, the insulating layer 6 is anisotropically etched to form insulating layer spacers 6 ′ on sidewalls of the gate electrode 3 and the gate oxide layer 2, and then the semiconductor substrates on both sides of the gate electrode 3 are formed. It is sectional drawing in which the source / drain 8 was formed, leaving the LDD area | region 5 by ion-implanting the high concentration impurity 7 in 1).
상기한 LDD 구조는 LDD 접합(Junction)을 이용하여 채널의 전계를 감소시킴으로 MOSFET 소자의 수명을 연장시키는데 사용되었다.The above-described LDD structure has been used to extend the life of the MOSFET device by reducing the electric field of the channel by using an LDD junction.
그러나, 반도체 소자가 고집적화됨에 따라 MOSFET의 채널 길이가 감소하면서 일반적으로 문턱 전압(Threshold Voltage) 등의 특성을 고려하여 채널의 불순물 농도가 증가한다.However, as semiconductor devices become more integrated, the channel length of the MOSFET decreases, and in general, the impurity concentration of the channel increases in consideration of characteristics such as a threshold voltage.
또한, 채널 길이가 감소됨에 따라 접합의 깊이가 줄어들게 되고, LDD 접합의 깊이도 감소됨으로써 LDD 접합에 의해서 채널 전계는 적게 감소되고, 핫 캐리어 발생을 억제하는 효과가 없어지게 되어 소자의 신뢰성이 떨어지는 문제점이 있다.In addition, as the channel length decreases, the depth of the junction decreases. As the depth of the LDD junction decreases, the channel electric field is reduced by the LDD junction, and the effect of suppressing hot carrier generation is eliminated. There is this.
따라서, 본 발명은 서브 마이크론(sub-μ) 이하의 작은 채널 길이를 갖는 MOSFET의 LDD 영역에 다른 타입의 저농도 불순물을 얕게 주입시켜 얕은 접합을 형성하여 LDD 영역의 유효 불순물 농도를 농도를 감소시켜 핫 캐리어 발생을 억제하여 소자 동작의 신뢰성을 향상시킬 수 있는 MOSFET 및 그 제조방법을 제공하는데 그 목적이 있다.Therefore, the present invention shallowly injects other types of low concentration impurities into the LDD region of the MOSFET having a small channel length of sub-micron or less to form a shallow junction, thereby reducing the concentration of the effective impurity concentration in the LDD region by reducing the concentration It is an object of the present invention to provide a MOSFET and a method of manufacturing the same, which can suppress the generation of carriers and improve the reliability of device operation.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제2a도 내지 2d도는 본 발명의 실시예에 의해 nMOSFET를 제조하는 단계를 도시한 단면도이다.2A through 2D are cross-sectional views illustrating steps of fabricating an nMOSFET in accordance with an embodiment of the present invention.
제2a도는 상기 제1a도와 같은 방법으로 P형 반도체 기판(1)의 상부에 게이트 산화막(2)과 폴리실리콘층 패턴으로 된 게이트 전극(3)을 형성한 다음, n형 저농도 불순물(4)을 주입하여 게이트 전극(3) 양측의 P형 반도체 기판(1)에 LDD 영역(5)을 형성한 상태의 단면도이다.FIG. 2A shows a gate electrode 3 having a gate oxide film 2 and a polysilicon layer pattern formed on the P-type semiconductor substrate 1 in the same manner as in FIG. 1A, and then n-type low concentration impurity 4 It is sectional drawing of the state in which the LDD region 5 was formed in the P-type semiconductor substrate 1 on both sides of the gate electrode 3 by injecting.
제2b도는 상기 게이트 전극(3)과 반도체 기판(1)을 열산화(Thermal Oxidation)시켜 산화막(11)을 형성하고, 상기 반도체 기판(1)상의 산화막(11)을 제거하여 게이트 전극(3)의 표면에만 산화막(11)이 남도록 한후, 전체 구조 상부에 폴리실리콘층을 증착하고, P형 불순물(15)인 붕소(Boron)를 폴리실리콘층에 이온주입시킨 상태의 단면도이다.2B illustrates an oxide film 11 formed by thermally oxidizing the gate electrode 3 and the semiconductor substrate 1, and removing the oxide film 11 on the semiconductor substrate 1 to remove the gate electrode 3. After the oxide film 11 is left only on the surface of the film, a polysilicon layer is deposited on the entire structure, and boron (P-type impurity 15) is implanted into the polysilicon layer.
제2c도는 상기 폴리실리콘층을 전면 이방성 식각하여 상기 게이트 전극(3)을 덮고 있는 산화막(11)의 측벽에 P형 불순물이 도포된 폴리실리콘 스페이서(12')를 형성하고, 어닐링 공정을 실시하여 폴리실리콘 스페이서(12') 저부의 LDD 영역(5)에 P얕은 접합(13)을 형성한 단면도이다. 상기 P얕은 접합(13)이 깊이는 어닐링 시간과 온도에 의하여 조절할 수 있다.In FIG. 2C, the polysilicon layer is anisotropically etched to form polysilicon spacers 12 ′ coated with P-type impurities on sidewalls of the oxide film 11 covering the gate electrode 3, and then subjected to an annealing process. P in the LDD region 5 at the bottom of the polysilicon spacer 12 ' It is sectional drawing in which the shallow junction 13 was formed. P above The depth of the shallow junction 13 can be controlled by the annealing time and temperature.
제2d도는 n형 고농도 불순물(7) 반도체 기판(1)로 이온 주입하여 n+접합인 소오스/드레인 영역(8)을 형성한 단면도이다.FIG. 2D is a cross-sectional view of the source / drain regions 8 which are n + junctions by ion implantation into the n-type high concentration impurity 7 semiconductor substrate 1.
본 발명의 얕은 접합 형성방법은 상기한 nMOSFET 대신에 pMOSFET에도 적용할 수 있다. 즉 상기한 공정 방법으로 하되, n형 기판에 p형 LDD 영역을 형성하고, p형 LDD 영역에 n-얕은 접합을 형성하며, n+접합인 소오스/드레인 영역을 형성하면 된다.The shallow junction formation method of the present invention can be applied to a pMOSFET instead of the nMOSFET. In other words, the process method described above may be performed by forming a p-type LDD region on an n-type substrate, an n-shallow junction on a p-type LDD region, and forming a source / drain region that is an n + junction.
상기한 본 발명은 전형적인 LDD 구조의 N접합내에 P얕은 접합이 형성되어 있다. P얕은 접합은 N접합내에 빌트-인(Built-in) 전압에 의한 공핍(Depletion) 영역을 가진다. 따라서, P-N 구조가 형성되어 부분적으로 기판 표면에 수직 방향의 전계가 형성되며 이에 따라 잔류(I)의 흐름은 제2d도와 같이 된다. 따라서 핫 캐리어 발생의 직접적인 원인인 채널내의 수평 전계는 감소하고 전계의 최대점이 기판 표면으로부터 깊은 곳에 존재한다.The present invention described above provides a typical LDD structure of N P in the junction Shallow junction is formed. P Shallow Junction N It has a depletion region due to built-in voltage in the junction. Thus, a PN structure is formed, which partially forms an electric field in the vertical direction on the surface of the substrate, whereby the residual I flows as shown in FIG. 2d. Thus, the horizontal electric field in the channel, which is a direct cause of hot carrier generation, is reduced and the maximum of the electric field is deep from the substrate surface.
핫 캐리어에 의한 소자 수명의 감소는 다음과 같다.The reduction of device life due to hot carrier is as follows.
수평 전계에 의해서 가속된 전자의 일부가 실리콘 원자와 충돌하여 전자-홀(Hole)쌍을 만들면 이들중 일부가 기판 표면으로 확산(Diffusion)하여 게이트 산화막에 트랩핑(Trapping)되어 MOSFET의 전기적 특성을 변화시킨다. 따라서 핫 캐리어에 의한 소자 특성의 열화는 수평 전계의 크기 뿐아니라 최대 전계의 위치에 크게 의존한다.When some of the electrons accelerated by the horizontal electric field collide with silicon atoms to form electron-hole pairs, some of them diffuse to the surface of the substrate and are trapped on the gate oxide layer to improve the electrical characteristics of the MOSFET. Change. Therefore, deterioration of device characteristics due to hot carriers depends not only on the magnitude of the horizontal electric field but also on the position of the maximum electric field.
본 발명은 수평 전계의 크기를 줄이고 최대 전계를 P얕은 접합 깊이 이하로 만들수 있기 때문에 소자수명을 일반적인 LDD 구조에 비해서 향상시킬 수 있다.The present invention reduces the magnitude of the horizontal electric field and increases the maximum electric field P. It can be made below the shallow junction depth, thus improving device life compared to conventional LDD structures.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930003733A KR960008736B1 (en) | 1993-03-12 | 1993-03-12 | Mosfet and the manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019930003733A KR960008736B1 (en) | 1993-03-12 | 1993-03-12 | Mosfet and the manufacturing method thereof |
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| KR940022918A KR940022918A (en) | 1994-10-22 |
| KR960008736B1 true KR960008736B1 (en) | 1996-06-29 |
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