KR100567030B1 - Methood for manufacturing Transistor - Google Patents

Abstract

The present invention relates to a method for manufacturing a transistor that can form a shallow junction and silicide to prevent short channel effects and parasitic resistance, and the method for manufacturing a transistor includes a first cleaning process of a semiconductor substrate on which a gate and a predetermined substructure are formed. Advancing, depositing a silicide forming material and a capping film after performing the cleaning process, performing a first annealing process on the silicide forming material, and unreacted silicide during the first annealing process Removing the material by the secondary cleaning process and proceeding with the secondary annealing process, after the secondary annealing process, and then performing a source / drain ion implantation process, and tertiary annealing to the resultant ion implantation process. And lowering the process immediately after the temperature is raised to the heat treatment temperature.

Silicide, shallow junction, heat treatment temperature, spike

Description

Transistor manufacturing method {Methood for manufacturing Transistor}             

1A to 1F illustrate a problem of a conventional transistor manufacturing method.

2A to 2E are cross-sectional views illustrating a method of manufacturing a transistor according to the present invention.

   -Explanation of symbols for the main parts of the drawings-

200: silicon substrate 210: field oxide film

220: gate oxide film 230: polysilicon

240: LDD region 250: halo ion implantation layer

260: buffer oxide film 270: gate spacer

280: silicide 290: source / drain

The present invention relates to a transistor manufacturing method, and more particularly, to a transistor manufacturing method that can improve the device characteristics by preventing the formation of short channel effect and parasitic resistance by forming a silicide together with the formation of a shallow junction.

As semiconductor devices become highly integrated, it is required to form finely the width of the gate pattern. However, the miniaturization of the gate pattern increases the resistance of the gate pattern, and as a result, adversely affects the speed of the semiconductor device. In order to solve this problem, a technique of further forming a silicide pattern having excellent conductivity on the gate pattern is commonly used.

When the silicide is formed by the prior art, a large portion of the heavily doped source / drain region silicon is consumed in the silicide, causing limitations in the formation of the shallow junction, causing a junction leakage current.

Hereinafter, the problem of the transistor manufacturing method according to the prior art will be described with reference to the following drawings.

1A to 1F illustrate a problem of a conventional transistor manufacturing method.

First, as shown in FIG. 1A, a field oxide film 110 is formed on a silicon substrate 100 to define an active region and a field region, and as shown in FIG. 1B, an n-type or p-type ion implantation is performed to perform wells. (Not shown).

Thereafter, as shown in FIG. 1C, the gate oxide layer 120 and the polysilicon 130 are formed, and then the gate electrode is patterned by an image photographing and etching process. After the low concentration impurity ion implantation is performed to form the LDD region 140, a halo ion implantation process is performed to form the halo ion implantation layer 150.

Subsequently, as shown in FIG. 1D, after forming the buffer oxide layer 160 and the gate spacer 170 on the sidewalls of the gate electrode, an ion implantation process is performed to form the source / drain junction region 180. In this case, the characteristics of the device may be degraded according to the depths of the LDD region 140 and the source / drain 180 junction layer, that is, a short channel phenomenon may be required, thereby forming a shallower junction region.

After forming the source / drain junction region, as shown in FIG. 1E, the cobalt 190 is deposited on the entire surface of the resultant, followed by two thermal processes, and as shown in FIG. 1F, the top of the gate electrode and the source are shown. A cobalt silicide film 190 'is formed in the / drain junction region. At this time, the cobalt has a characteristic of diffusing and moving into the silicon to form silicide, so silicon consumption is very high. As a result, there was a vulnerability that consumed silicon in a heavily doped source / drain junction region, causing junction leakage current.

In order to solve the above problems, the present invention proceeds with a silicide process first, followed by a source / drain ion implantation process, and a heat treatment process that raises and lowers the temperature momentarily close to 0 seconds at a heat treatment temperature. By proceeding to form a junction region to provide a method for manufacturing a transistor to prevent the consumption of silicon in a very highly doped region to form a shallow junction.

The present invention for achieving the above object comprises the steps of performing a first cleaning process of the semiconductor substrate formed with a gate and a predetermined substructure, depositing a silicide forming material and a capping film after the cleaning process; Performing a first annealing process on the silicide forming material, removing an unreacted silicide material by a second cleaning process during the first annealing process, and then performing a second annealing process, and the second annealing process And a source / drain ion implantation process, and a third annealing process on the resultant of the ion implantation, followed by the step of lowering the temperature immediately to a heat treatment temperature.

According to the transistor manufacturing method according to the present invention, the silicide process is first performed, and then the source / drain ion implantation process is performed, and the heat treatment process is performed to raise and lower the temperature instantaneously near the 0 second holding time at the heat treatment temperature. By forming the junction region to prevent the consumption of the silicon of the very highly doped region as well as damage to the silicide only by not affecting the substrate can improve the bonding characteristics.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.

2A to 2E are cross-sectional views illustrating a method of manufacturing a transistor according to the present invention.

First, as shown in FIG. 2A, the field oxide film 210 is formed by the STI process to reduce the electrical isolation region between devices in accordance with the high integration of the device without a buzz big phenomenon in the silicon substrate 200, thereby forming an active region and a field region. As shown in FIG. 2B, p wells are formed by an ion implantation process using boron in the case of an NMOSFET, and n wells are formed using phosphorus or arsenic in the case of a PMOSFET. Form.

Thereafter, as shown in FIG. 2C, the gate oxide layer 220 and the polysilicon 230 are formed, and then the gate electrode is patterned by a predetermined photo and etching process. In addition, low concentration impurity ion implantation is performed to form the LDD region 240 to control electric fields of carriers flowing between the source / drain formed subsequently. This is a problem that causes an undesired flow of the cable due to a reduction in the size of the device or consequently the operating voltage of the device is not reduced, so that a very high electric field is concentrated in a portion of the channel drain side, causing a failure in the operation of the device. It is to minimize.

Subsequently, in order to prevent a short channel effect in which the channel length is reduced and the threshold voltage is lowered as the LDD region 240 is formed, a halo ion implantation process is performed by forming a halo ion implantation layer 250 by giving a predetermined tilt.

Subsequently, as shown in FIG. 2D, a buffer oxide film 260 and a gate spacer 270 are formed on the sidewalls of the gate electrode, and then 60 to 180 seconds at 23 ± 0.5 ° C. using a mixed solution of HF: H 2 O = 1: 99. During the cleaning process, the native oxide film in the region where the silicide is to be formed is removed. Thereafter, cobalt is deposited very thinly with a thickness of 50-80 mm 3, and a titanium nitride film (not shown) is deposited with a thickness of 100-300 mm 3 with a capping film. At this time, if the thickness of cobalt is too thick, cobalt atoms may penetrate beyond the depth into which the nitrogen ions have been implanted, and thus non-ideal silicides may be formed at the depth of the nitrogen ions or more.

Then, the first annealing process is performed for 30 to 60 seconds at a temperature of 400 ~ 500 ℃ in the RTP equipment, wherein the chamber maintains 100% N ₂ atmosphere and the temperature increase rate is in the range of 30 ~ 50 ℃ / sec Keep it.

Then, in order to remove unreacted cobalt during the first annealing process, the primary cleaning process using the SC1 (NH ₄ : H ₂ O ₂ : H ₂ O = 0.2: 1: 10) solution was performed at 50 ± 5 ° C. After 5 to 10 minutes at the temperature using a SC2 (HCl: H ₂ O ₂ : H ₂ O = 1: 1: 5) solution to proceed with the secondary cleaning process for 5 to 10 minutes at a temperature of 50 ± 5 ℃ do.

Subsequently, the secondary heat treatment process is performed for 20 to 30 seconds at a temperature of 700 to 800 ° C., wherein the chamber maintains 100% N ₂ atmosphere and the temperature increase rate is in the range of 30 to 50 ° C./sec. The silicide film 280 is formed by performing the process.

Then, as shown in FIG. 2E, an ion implantation process and a heat treatment process for forming a junction region in the silicide film formation region are performed to form a source / drain junction region 290. In the ion implantation process, the ion implantation process is performed using energy of 20-30KeV and dose amount of 2.0E15 ~ 5.0E15 when using an acenic ion implantation, and 20-40KeV energy and 3.0 when using phosphorus. The ion implantation process is performed at a dose of E13 to 5.0E14. In addition, the P + side uses boron, but undergoes an ion implantation process under an energy of 3 to 5 KeV and an energy of 2.0E15 to 5.0E15.

In addition, the heat treatment process in the chamber atmosphere 100% N ₂ atmosphere using the RTP equipment in the temperature increase rate 150 ~ 400 ℃ / sec, the falling rate 60 ~ 90 ℃ / sec range in the range of 850 ~ 1050 ℃. . At this time, since the thermal stability is required to re-form silicide during the heat treatment process, there is a limit to high temperature heat treatment, and high temperature heat treatment is required to form a source / drain, so that a high temperature heat treatment is required. Thermal process should be carried out.

As described above, according to the transistor manufacturing method of the present invention, the silicide is first formed before the source / drain formation, and the source / drain ion implantation process and the heat treatment process are performed, but the doped by the spike annealing process is performed at a high temperature for a short time. Since ions are diffused from the silicide and diffused as much as necessary for source / drain formation, it is possible to prevent the consumption of silicon in the heavily doped portion, thereby enabling low junction formation.

In addition, by minimizing problems such as increased surface roughness when silicide is reformed by subsequent heat treatment, it is possible to form a silicide having a uniform and small grain size, and to damage the substrate by causing damage only in the silicide. It does not give, and joining property becomes excellent.

In addition, the interfacial doping concentration of the silicide and the junction region may be increased, thereby improving contact resistance characteristics.

As described above, the present invention is capable of forming a shallow junction by preventing silicon consumption of a heavily doped portion, and by forming a silicide having a uniform and small grain size, thereby improving short channel effect by improving short channel effect, thereby improving device performance. There is an advantage that can be improved.

Claims (5)

Forming a gate electrode on a semiconductor substrate on which a predetermined substructure is formed; Implanting low concentration impurities into the semiconductor substrates at both sides of the gate electrode to form an LDD region; Sequentially forming a buffer oxide layer and a gate spacer on both sidewalls of the gate electrode; Performing a first cleaning process on the semiconductor substrate; Depositing a silicide forming material and a capping film after the cleaning process; Performing a first annealing process on the silicide forming material; Removing the unreacted silicide material by a second cleaning process in the first annealing process and then performing a second annealing process; Performing a source / drain ion implantation process after the second annealing process; A step of lowering the third annealing process immediately after the temperature is increased to a heat treatment temperature to the resultant obtained by ion implant Transistor manufacturing method comprising a. The method of claim 1, wherein the first annealing process is performed in a 100% N ₂ atmosphere at 400 ° C. to 500 ° C. for 30 to 60 seconds at a temperature of 30 ° C. to 50 ° C./sec. The method of claim 1, wherein the first cleaning process is performed for 5 to 10 minutes at a temperature of 50 ± 5 ℃ using a SC1 (NH ₄ : H ₂ O ₂ : H ₂ O = 0.2: 1:10) solution Method for producing a transistor, characterized in that carried out for 5 to 10 minutes at a temperature of 50 ± 5 ℃ using a solution of SC2 (HCl: H ₂ O ₂ : H ₂ O = 1: 1: 5). The method of claim 1, wherein the secondary annealing process is performed for 20 to 30 seconds at a temperature increase rate of 30 to 50 ° C./sec in a 100% N ₂ atmosphere and a temperature of 700 to 800 ° C. 6. The method of claim 1, wherein the tertiary heat treatment is performed at an annealing temperature of 850 ° C. to 1050 ° C. using RTP equipment in an atmosphere of 100% N ₂ .

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