KR20050012948A - Method for manufacturing Transistor - Google Patents

Abstract

PURPOSE: A method for manufacturing a transistor is provided to improve uniformity of a silicide layer and to enhance short channel margin by implanting nitrogen ions before depositing a cobalt film. CONSTITUTION: Nitrogen ions are implanted into a silicon substrate(100) having a junction region(180), a gate(130) and a desired lower structure. Then, a cobalt film is deposited on the resultant structure. A first annealing process is carried out. A cleaning process is performed so as to remove the non-reacted cobalt residues. A second annealing process is then performed.

Description

Transistor manufacturing method {Method for manufacturing Transistor}

The present invention relates to a transistor manufacturing method, and more particularly to a transistor manufacturing method that can improve the reliability of the device by forming a very thin and uniform silicide film.

As semiconductor devices become highly integrated, it is required to form finely the width of the gate pattern. However, the miniaturization of the gate pattern increases the resistance of the gate pattern, and as a result, adversely affects the speed of the semiconductor device. In order to solve this problem, a technique of further forming a silicide pattern having excellent conductivity on the gate pattern is commonly used.

When the silicide is formed by the prior art, there is a problem of causing a junction leakage current because the diffusion mobility inside the silicon substrate is large and the consumption of silicon in the heavily doped source / drain regions becomes excessively large.

Hereinafter, the problem of the transistor manufacturing method according to the prior art will be described with reference to the following drawings.

1A to 1F illustrate a problem of a conventional transistor manufacturing method.

First, as shown in FIG. 1A, a field oxide film 110 is formed on a silicon substrate 100 to define an active region and a field region, and as shown in FIG. 1B, an n-type or p-type ion implantation is performed to perform wells. (Not shown).

Thereafter, as shown in FIG. 1C, the gate oxide layer 120 and the polysilicon 130 are formed, and then the gate electrode is patterned by an image photographing and etching process. After the low concentration impurity ion implantation is performed to form the LDD region 140, a halo ion implantation process is performed to form the halo ion implantation layer 150.

Subsequently, as shown in FIG. 1D, after forming the buffer oxide layer 160 and the gate spacer 170 on the sidewalls of the gate electrode, an ion implantation process is performed to form the source / drain junction region 180. In this case, the characteristics of the device may be degraded according to the depths of the LDD region 140 and the source / drain 180 junction layer, that is, a short channel phenomenon may be required, thereby forming a shallower junction region.

After forming the source / drain junction region, as shown in FIG. 1E, the cobalt 190 is deposited on the entire surface of the resultant, followed by two thermal processes, and as shown in FIG. 1F, the top of the gate electrode and the source are shown. A cobalt silicide film 190 'is formed in the / drain junction region. At this time, the cobalt has a characteristic of diffusing and moving into the silicon to form silicide, so silicon consumption is very high. As a result, there was a vulnerability that consumed silicon in a heavily doped source / drain junction region, causing junction leakage current.

This characteristic has a fatal disadvantage in realizing a very small device of less than 90nm technology because a small amount of nickel is used to improve this problem, but nickel has a problem that the deterioration characteristics according to the temperature during the subsequent heat treatment process.

The present invention is to provide a transistor manufacturing method for forming a very thin and uniform silicide film by injecting nitrogen ions prior to cobalt deposition by allowing the cobalt and the silicon substrate to react to the depth implanted with nitrogen ions. .

1A to 1F illustrate a problem of a conventional transistor manufacturing method.

2A to 2G are cross-sectional views illustrating a method of manufacturing a transistor according to the present invention.

-Explanation of symbols for the main parts of the drawings-

100 silicon substrate 110 field oxide film

120: gate oxide film 130: polysilicon

140: LDD region 150: halo ion implantation layer

160: gate oxide film 170: gate spacer

180: source / drain 190: cobalt

190 ': Silicide

The present invention for solving the above object is a step of performing nitrogen ion implantation on the semiconductor substrate formed with a junction region, a gate and a predetermined substructure, depositing cobalt on the result of the ion implantation, Performing a first annealing process on the cobalt-deposited product, performing a cleaning process for removing unreacted cobalt during the first annealing, and performing a second annealing process after the cleaning process. It relates to a transistor manufacturing method comprising a.

In the transistor manufacturing method according to the present invention, it is preferable that the surface oxide film of the silicide formation region is removed by further performing a pre-cobalt deposition cleaning process.

In addition, the cobalt is preferably deposited to a thickness of 50 ~ 80Å in order to prevent the formation of uneven silicide above the nitrogen ion implantation depth when deposited too thick.

According to the transistor manufacturing method according to the present invention, nitrogen ion implantation is performed before the cobalt deposition to reduce the diffusion movement rate of the cobalt reacted with the silicon substrate by the nitrogen element during the first and second heat treatment processes, and at the same time nitrogen Cobalt and the silicon substrate react to the point where a large amount of ions are present, thereby forming a uniform and thin cobalt silicide film.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.

2A to 2G are cross-sectional views illustrating a method of manufacturing a transistor according to the present invention.

First, as shown in FIG. 2A, a field oxide layer 110 is formed on the silicon substrate 100 to define an active region and a field region. As shown in FIG. 2B, an ion implantation process using boron is performed in the case of an NMOSFET. Proceeding to form a p well, in the case of a PMOSFET to form an n well using a phosphorus (Phosphorus) or arsenic (Arsenic).

Next, as shown in FIG. 2C, the gate oxide layer 120 and the polysilicon 130 are formed, and then the gate electrode is patterned by a predetermined photo and etching process. In addition, low concentration impurity ion implantation is performed to form the LDD region 140 to control electric fields of charges flowing between the source / drain formed subsequently. This is a problem that causes an undesired flow of the cable due to a reduction in the size of the device or consequently the operating voltage of the device is not reduced, so that a very high electric field is concentrated in a portion of the channel drain side, causing a failure in the operation of the device. It is to minimize.

Subsequently, in order to prevent a short channel effect in which the channel length is reduced and the threshold voltage is lowered as the LDD region 140 is formed, a halo ion implantation process is performed to form a halo ion implantation layer 150 by giving a predetermined tilt.

Subsequently, as shown in FIG. 2D, after forming the buffer oxide layer 160 and the gate spacer 170 on the sidewalls of the gate electrode, a high concentration of ion implantation is performed and a rapid heat treatment process is performed to form the source / drain junction region 180. Form. In this case, the characteristics of the device may be degraded according to the depths of the LDD region 140 and the source / drain 180 junction layer, that is, a short channel phenomenon may be required, thereby forming a shallower junction region.

Then, as shown in Fig. 2e, using a nitrogen ion without a mask process to give a tilt of 0 ~ 60 ° with energy of 10 ~ 25KeV and dose amount of 1.0E15 ~ 1.0E16 atom / ㎠ and rotate 0 ~ 360 ° To proceed with the ion implantation process. In this case, the thickness of the silicide layer may be limited when the subsequent silicide is formed by the nitrogen ion implantation.

Subsequently, after the ion implantation process, the cleaning process was performed for 60 to 180 seconds at a temperature of 23 ± 0.5 ° C using a cleaning solution of HF: H ₂ O = 1: 99 to remove the oxide film on the surface where silicide is to be formed. As shown in Figure 2f, cobalt is deposited very thinly with a thickness of 50-80 mm 3. In this case, if the thickness of the cobalt is too thick, cobalt atoms penetrate more than the depth into which the nitrogen ions are injected, and thus, non-ideal silicides may be formed at the nitrogen ion depth or more.

Then, the first annealing process is performed for 30 to 120 seconds at a temperature of 400 ~ 600 ℃ in the RTP equipment, the chamber maintains 100% N ₂ atmosphere and the temperature increase rate is in the range of 30 ~ 50 ℃ / sec Keep it.

Then, SC1 (NH ₄ : H ₂ O ₂ : H ₂ O = 0.2: 1: 10) solution and SC2 (HCl: H ₂ O ₂ ) solution to remove unreacted cobalt 190 in the first annealing process : H ₂ O = 1: 1: 5) Using a solution, the cleaning process is performed for 5 minutes at a temperature of 50 ± 5 ℃.

Subsequently, a second heat treatment process is performed at a temperature of 750 ° C. to 850 ° C. for 30 to 60 seconds to form a silicide layer 190 ′ as shown in FIG. 2G.

As described above, according to the method of manufacturing a semiconductor device according to the present invention, the diffusion of cobalt 190 reacted with the silicon substrate 100 by nitrogen element during the first and second heat treatment processes by injecting nitrogen ions before the heat treatment process. The cobalt and silicon substrates may be reacted to a point where a large amount of nitrogen ions are present while reducing the moving speed, thereby forming a uniform and thin cobalt silicide layer 190 ′.

As described above, in the present invention, it is possible to form a very shallow junction by injecting nitrogen ions prior to cobalt deposition so that the cobalt and the silicon substrate react to the depth to which the nitrogen ions are implanted to form a very thin and uniform silicide film. Accordingly, there is an advantage that the reliability of the device can be improved by increasing the short channel margin by reducing the contact resistance with the metal.

Claims (9)

Performing nitrogen ion implantation on a semiconductor substrate having a junction region, a gate, and a predetermined substructure; Depositing cobalt on the result of the ion implantation, Performing a first annealing process on the resultant of depositing the cobalt; Performing a cleaning process to remove unreacted cobalt during the first annealing; After the cleaning process the step of proceeding to the secondary annealing process Transistor manufacturing method comprising a. The method of claim 1, further comprising performing the pre-cobalt deposition cleaning process. The method of claim 2, wherein the cleaning process is performed at a temperature of 23 ± 0.5 ° C. for 60 to 180 seconds using a cleaning solution of HF: H ₂ O = 1: 99. The transistor of claim 1, wherein the ion implantation step is performed by rotating 0 to 360 ° with a tilt of 0 to 60 ° with an energy of 10 to 25 KeV and a dose of 1.0E15 to 1.0E16 atom / cm 2. Manufacturing method. The method of claim 1, wherein the cobalt is deposited to a thickness of 50 ~ 80Å. The method of claim 1, wherein the first annealing process is performed for 30 to 120 seconds at a temperature of 400 to 600 ° C. in an RTP apparatus. The method of claim 1, wherein the first annealing process is a transistor manufacturing method, characterized in that the temperature increase rate in the chamber of 100% N ₂ atmosphere in the range of 30 ~ 50 ℃ / sec. The method of claim 1, wherein the cleaning process is performed at a temperature of 50 ± 5 ° C. for 5 minutes using an SC1 solution and an SC2 solution. The method of claim 1, wherein the secondary annealing process is performed for 30 to 60 seconds at a temperature of 750 ~ 850 ℃.