KR100273323B1 - Semiconductor device and manufacturing method - Google Patents
Semiconductor device and manufacturing method Download PDFInfo
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- KR100273323B1 KR100273323B1 KR1019980051331A KR19980051331A KR100273323B1 KR 100273323 B1 KR100273323 B1 KR 100273323B1 KR 1019980051331 A KR1019980051331 A KR 1019980051331A KR 19980051331 A KR19980051331 A KR 19980051331A KR 100273323 B1 KR100273323 B1 KR 100273323B1
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- South Korea
- Prior art keywords
- drain
- source
- gate
- ion implantation
- nitrogen ion
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 32
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 29
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 27
- 238000005468 ion implantation Methods 0.000 claims abstract description 25
- 125000006850 spacer group Chemical group 0.000 claims abstract description 23
- 239000012535 impurity Substances 0.000 claims abstract description 20
- 150000002500 ions Chemical class 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 abstract description 17
- 230000002776 aggregation Effects 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 230000003405 preventing effect Effects 0.000 abstract description 4
- 230000006866 deterioration Effects 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 3
- -1 nitrogen ion Chemical class 0.000 abstract description 3
- 230000000593 degrading effect Effects 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 238000004220 aggregation Methods 0.000 abstract 2
- 239000002184 metal Substances 0.000 description 4
- 238000005054 agglomeration Methods 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
본 발명은 반도체소자 및 그 제조방법에 관한 것으로, 종래에는 실리사이드층의 형성시에 응집하려는 특성에 따라 어느정도의 저항값은 피할 수 없고, 또한 실리사이드층과 소스/드레인의 계면이 거칠어져 후속 콘택공정의 신뢰성이 저하되는 문제점과; 소스/드레인의 정션깊이가 얇아지게 되어 누설전류가 증가하는 문제점과; 후속 고온공정이 요구되는 경우에 실리사이드층의 저항이 증가됨과 아울러 소스/드레인에 주입된 고농도 불순물이 확산하여 반소체소자의 특성 및 신뢰성이 저하되는 문제점이 있었다. 따라서, 본 발명은 엘디디 및 실리사이드구조가 채택된 반도체소자에 있어서, 소스/드레인과 실리사이드층 및 소스/드레인과 반도체기판 사이에 제1,제2 질소이온 주입층이 각각 삽입 형성된 반도체소자를 제1도전형 반도체기판의 상부에 게이트를 형성하는 공정과; 상기 게이트를 마스크로 하여 반도체기판 내에 제2도전형 저농도 불순물이온을 주입하는 공정과; 상기 게이트의 양측면에 측벽스페이서를 형성하는 공정과; 상기 게이트 및 측벽스페이서를 마스크로 하여 반도체기판 내에 제2도전형 고농도 불순물이온을 주입하여 엘디디영역 및 소스/드레인을 형성하는 공정과; 상기 게이트 및 측벽스페이서를 마스크로 하여 소스/드레인 내에 질소이온의 주입조건을 다르게 하여 제1,제2 질소이온 주입층을 형성하는 공정과; 상기 게이트와 소스/드레인 상에 실리사이드층을 형성하는 공정으로 이루어지는 제조방법을 통해 제공함으로써, 제1 질소이온 주입층에 의해 소스/드레인의 표면 상에 형성되는 실리사이드층의 응집을 방지하여 실리사이드층과 소스/드레인 계면의 거칠기를 개선할 수 있어 저항감소 및 후속 콘택공정의 신뢰성을 향상시킬 수 있고, 또한 제1 질소이온 주입층의 질소이온이 Co 실리사이드의 열적안정성을 향상시키며, 제2 질소이온 주입층에 의해 누설전류를 최소화함과 아울러 소스/드레인에 주입된 고농도 불순물이온이 반도체기판으로 확산되는 것을 억제하여 소스/드레인 형성깊이를 조절할 수 있으므로, 고온공정에 따른 소자특성 변화를 방지하여 반도체소자의 신뢰성을 향상시킬 수 있는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same. In the related art, some resistance values are inevitable depending on the characteristics of aggregation during formation of the silicide layer. Problem of deterioration of reliability; The junction depth of the source / drain becomes thin and the leakage current increases; In the case where a subsequent high temperature process is required, the resistance of the silicide layer is increased and a high concentration of impurities injected into the source / drain is diffused, thereby degrading the characteristics and reliability of the semi-element. Accordingly, the present invention provides a semiconductor device having an LED and silicide structure, wherein the semiconductor device includes a source / drain and silicide layer and a first and second nitrogen ion implantation layers interposed between the source / drain and semiconductor substrate, respectively. Forming a gate over the first conductive semiconductor substrate; Implanting a second conductivity type low concentration impurity ion into the semiconductor substrate using the gate as a mask; Forming sidewall spacers on both sides of the gate; Implanting a second conductive high concentration impurity ion into a semiconductor substrate using the gate and sidewall spacers as a mask to form an LED region and a source / drain; Forming first and second nitrogen ion implantation layers by varying nitrogen ion implantation conditions in a source / drain using the gate and sidewall spacers as masks; By providing a method of forming a silicide layer on the gate and the source / drain, the silicide layer and the silicide layer formed on the surface of the source / drain by the first nitrogen ion implantation layer to prevent aggregation It is possible to improve the roughness of the source / drain interface, thereby improving the resistance and reliability of the subsequent contact process, and also the nitrogen ion of the first nitrogen ion implantation layer improves the thermal stability of the Co silicide and the second nitrogen ion implantation. By minimizing the leakage current by the layer and suppressing the diffusion of high concentration of impurity ions injected into the source / drain onto the semiconductor substrate, the depth of source / drain formation can be controlled, thereby preventing changes in device characteristics due to high temperature processes. There is an effect that can improve the reliability of.
Description
본 발명은 반도체소자 및 그 제조방법에 관한 것으로, 특히 고집적 반도체소자의 채널길이 감소에 따른 영향과 저항값의 증가를 줄이기 위하여 채택된 엘디디(lightly doped drain : LDD) 및 실리사이드(silicide)구조 반도체소자의 누설전류를 최소화하고, 후속 고온공정 및 콘택공정에 따른 특성저하 및 신뢰성저하를 방지할 수 있는 반도체소자 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for fabricating the same, and in particular, a lightly doped drain (LDD) and silicide structure semiconductor adopted to reduce the effect of the decrease in the channel length and increase in the resistance value. The present invention relates to a semiconductor device capable of minimizing leakage current of a device, and to preventing property deterioration and reliability deterioration due to subsequent high temperature and contact processes.
종래의 반도체소자를 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.A detailed description will be given of a conventional semiconductor device with reference to the accompanying drawings.
도1은 종래 반도체소자의 단면도로서, 이에 도시한 바와같이 반도체기판(1)의 상부에 적층 형성된 게이트산화막(2) 및 게이트전극(3)과; 상기 게이트산화막(2) 및 게이트전극(3)의 적층된 구조물 양측면에 형성된 측벽스페이서(4)와; 상기 측벽스페이서(4)의 하부 반도체기판(1) 내에 형성된 저농도 불순물영역(5)과; 상기 측벽스페이서(4)의 양측면 반도체기판(1) 내에 형성된 소스/드레인(6)과; 상기 게이트전극(3) 및 소스/드레인(6) 상에 형성된 실리사이드층(7)을 구비하여 이루어진다. 이하, 상기한 바와같은 종래 반도체소자의 제조방법을 상세히 설명한다.1 is a cross-sectional view of a conventional semiconductor device, as shown therein; a gate oxide film 2 and a gate electrode 3 formed on a semiconductor substrate 1 stacked thereon; Sidewall spacers (4) formed on both sides of the stacked structure of the gate oxide film (2) and the gate electrode (3); A low concentration impurity region 5 formed in the lower semiconductor substrate 1 of the side wall spacer 4; Source / drain (6) formed in both side semiconductor substrates (1) of the sidewall spacers (4); And a silicide layer 7 formed on the gate electrode 3 and the source / drain 6. Hereinafter, a method of manufacturing a conventional semiconductor device as described above will be described in detail.
먼저, 반도체기판(1)의 상부를 산화시켜 게이트산화막(2)을 형성한 후, 그 게이트산화막(2)의 상부에 게이트전극물질을 증착한다.First, the upper portion of the semiconductor substrate 1 is oxidized to form a gate oxide film 2, and then a gate electrode material is deposited on the gate oxide film 2.
그리고, 상기 게이트전극물질과 게이트산화막(2)을 패터닝하여 게이트산화막(2) 및 게이트전극(3)이 적층된 구조물을 형성한다.The gate electrode material and the gate oxide film 2 are patterned to form a structure in which the gate oxide film 2 and the gate electrode 3 are stacked.
그리고, 상기 게이트산화막(2) 및 게이트전극(3)의 적층 구조물을 마스크로 하여 반도체기판(1) 내에 저농도의 불순물이온을 주입함으로써, 저농도 불순물영역(5)을 형성한다. 이때, 도면상의 소스/드레인(6)도 저농도 불순물영역(5)으로 형성된다.The low concentration impurity region 5 is formed by implanting low concentration impurity ions into the semiconductor substrate 1 using the stacked structure of the gate oxide film 2 and the gate electrode 3 as a mask. At this time, the source / drain 6 on the drawing is also formed of the low concentration impurity region 5.
그리고, 상기 저농도 불순물영역(5)이 형성된 반도체기판(1)의 상부전면에 절연막으로서 질화막을 증착한 후, 에치-백(etch-back)하여 상기 적층 구조물의 측면에 측벽스페이서(4)를 형성한다.Then, a nitride film is deposited as an insulating film on the upper surface of the semiconductor substrate 1 on which the low concentration impurity region 5 is formed, and then etched back to form sidewall spacers 4 on the side surfaces of the stacked structure. do.
그리고, 상기 게이트산화막(2) 및 게이트전극(3)의 적층 구조물과 측벽스페이서(4)를 마스크로 하여 노출된 상기 반도체기판(1)에 형성된 저농도 불순물영역(5) 내에 고농도의 불순물이온을 주입함으로써, 상기 고농도 불순물영역으로 소스/드레인(6)을 형성한다.In addition, a high concentration of impurity ions are implanted into the low concentration impurity region 5 formed in the semiconductor substrate 1 exposed by using the stack structure of the gate oxide film 2 and the gate electrode 3 and the sidewall spacer 4 as a mask. Thus, the source / drain 6 is formed in the high concentration impurity region.
그리고, 상기 소스/드레인(6)이 형성된 반도체기판(1) 상에 Co 또는 Ti의 금속층을 증착한 후, 열처리하는 살리사이드(self aligned silicide : SALICIDE) 공정을 통해 실리사이드층(7)을 형성한다. 이때, 살리사이드 공정이란 열처리에 의해 금속과 실리콘은 반응하여 실리사이드층(7)으로 형성되지만, 금속과 측벽스페이서(4) 및 분리영역(도면 미도시)은 반응하지 않는 성질을 이용하여 소스/드레인(6) 및 게이트전극(3) 상에만 선택적으로 실리사이드층(7)을 형성하고, 반응하지 않은 금속층을 제거하는 일련의 공정을 지칭하며, 이와같은 실리사이드층(7)은 소스/드레인(6)의 저항값을 크게 감소시켜 반도체소자의 특성향상에 기여한다.In addition, a silicide layer 7 is formed by depositing a metal layer of Co or Ti on the semiconductor substrate 1 on which the source / drain 6 is formed, and then performing a heat treatment on a self-aligned silicide (SALICIDE) process. . In this case, the salicide process is performed by heat treatment, so that the metal and silicon react to form the silicide layer 7, but the metal and the sidewall spacer 4 and the isolation region (not shown) are not reacted. (6) and a series of processes for selectively forming the silicide layer 7 only on the gate electrode 3 and removing the unreacted metal layer, such silicide layer 7 being the source / drain 6 This greatly reduces the resistance value of and contributes to the improvement of the characteristics of the semiconductor device.
그러나, 상기한 바와같은 종래 반도체소자 및 그 제조방법은 실리사이드층의 형성시에 응집(agglomeration)하려는 특성에 따라 어느정도의 저항값은 피할 수 없고, 또한 실리사이드층과 소스/드레인의 계면이 거칠어져 후속 콘택공정의 신뢰성이 저하되는 문제점과; 소스/드레인의 정션깊이(junction depth)가 얇아지게 되어 누설전류가 증가하는 문제점과; 후속 고온공정이 요구되는 경우에 실리사이드층의 저항이 증가됨과 아울러 소스/드레인에 주입된 고농도 불순물이 확산하여 반소체소자의 특성 및 신뢰성이 저하되는 문제점이 있었다.However, according to the conventional semiconductor device and the manufacturing method as described above, a certain resistance value is inevitable depending on the property to be agglomerated during formation of the silicide layer, and the interface between the silicide layer and the source / drain becomes rough. A problem that the reliability of the contact process is lowered; The junction depth of the source / drain becomes thin and the leakage current increases; In the case where a subsequent high temperature process is required, the resistance of the silicide layer is increased and a high concentration of impurities injected into the source / drain is diffused, thereby degrading the characteristics and reliability of the semi-element.
본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 엘디디 및 실리사이드구조가 채택된 반도체소자의 누설전류를 최소화함과 아울러 고온공정 및 콘택공정시에 특성저하 및 신뢰성저하를 방지할 수 있는 고집적 반도체소자 및 그 제조방법을 제공하는데 있다.The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to minimize the leakage current of the semiconductor device adopting the LED and silicide structure, and to reduce the characteristics during the high temperature process and the contact process. And to provide a highly integrated semiconductor device and a method of manufacturing the same that can prevent the degradation of reliability.
도1은 종래 반도체소자의 단면도.1 is a cross-sectional view of a conventional semiconductor device.
도2는 본 발명의 일 실시예를 보인 수순단면도.Figure 2 is a cross-sectional view showing an embodiment of the present invention.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
11:반도체기판 12:게이트산화막11: semiconductor substrate 12: gate oxide film
13:게이트전극 14:측벽스페이서13: gate electrode 14: side wall spacer
15:엘디디영역 16:소스/드레인15: LED Area 16: Source / Drain
17,18:제1,제2 질소이온 주입층 19:실리사이드층17,18: first and second nitrogen ion injection layer 19: silicide layer
상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체소자의 바람직한 일 실시예는 반도체기판의 상부에 형성된 측벽스페이서를 갖는 게이트와; 상기 측벽스페이서의 하부 및 양측면 반도체기판 내에 형성된 엘디디영역 및 소스/드레인과; 상기 게이트와 소스/드레인 상에 형성된 실리사이드층을 구비하여 이루어지는 반도체소자에 있어서, 상기 소스/드레인과 실리사이드층 및 소스/드레인과 반도체기판 사이에 제1,제2 질소이온 주입층이 각각 삽입 형성된 것을 특징으로 한다.One preferred embodiment of a semiconductor device for achieving the object of the present invention as described above is a gate having a sidewall spacer formed on top of the semiconductor substrate; An LED region and a source / drain formed in the lower and opposite side semiconductor substrates of the sidewall spacers; A semiconductor device comprising a silicide layer formed on the gate and a source / drain, wherein a first and a second nitrogen ion implantation layer is inserted between the source / drain and silicide layer, and the source / drain and semiconductor substrate, respectively. It features.
또한, 상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체소자 제조방법의 바람직한 일 실시예는 제1도전형 반도체기판의 상부에 게이트를 형성하는 공정과; 상기 게이트를 마스크로 하여 반도체기판 내에 제2도전형 저농도 불순물이온을 주입하는 공정과; 상기 게이트의 양측면에 측벽스페이서를 형성하는 공정과; 상기 게이트 및 측벽스페이서를 마스크로 하여 반도체기판 내에 제2도전형 고농도 불순물이온을 주입하여 엘디디영역 및 소스/드레인을 형성하는 공정과; 상기 게이트 및 측벽스페이서를 마스크로 하여 소스/드레인 내에 질소이온의 주입조건을 다르게 하여 제1,제2 질소이온 주입층을 형성하는 공정과; 상기 게이트와 소스/드레인 상에 실리사이드층을 형성하는 공정을 구비하여 이루어지는 것을 특징으로 한다.In addition, a preferred embodiment of the semiconductor device manufacturing method for achieving the object of the present invention as described above comprises the steps of forming a gate on top of the first conductive semiconductor substrate; Implanting a second conductivity type low concentration impurity ion into the semiconductor substrate using the gate as a mask; Forming sidewall spacers on both sides of the gate; Implanting a second conductive high concentration impurity ion into a semiconductor substrate using the gate and sidewall spacers as a mask to form an LED region and a source / drain; Forming first and second nitrogen ion implantation layers by varying nitrogen ion implantation conditions in a source / drain using the gate and sidewall spacers as masks; And forming a silicide layer on the gate and the source / drain.
상기한 바와같은 본 발명에 의한 반도체소자 및 그 제조방법의 바람직한 일 실시예를 도2a 내지 도2c에 도시한 수순단면도를 참조하여 상세히 설명하면 다음과 같다.A preferred embodiment of the semiconductor device and a method of manufacturing the same according to the present invention as described above will be described in detail with reference to the cross-sectional view shown in FIGS. 2A to 2C.
먼저, 도2a는 반도체기판(11)의 상부에 게이트산화막(12)과 게이트전극(13)의 적층 구조물을 형성하고, 그 적층 구조물을 마스크로 하여 반도체기판(11) 상에 저농도 불순물이온을 주입한 후, 상기 적층 구조물의 측면에 측벽스페이서(14)를 형성하고, 그 적층 구조물과 측벽스페이서(14)를 마스크로 하여 반도체기판(11) 상에 고농도 불순물이온을 주입하여 엘디디영역(15) 및 소스/드레인(16)을 형성하는 통상적인 엘디디구조가 채택된 반도체소자를 도시하였다.First, FIG. 2A illustrates a stacked structure of the gate oxide film 12 and the gate electrode 13 formed on the semiconductor substrate 11, and implanted low concentration impurity ions onto the semiconductor substrate 11 using the stacked structure as a mask. Then, the sidewall spacers 14 are formed on the side surfaces of the stacked structure, and a high concentration of impurity ions are implanted onto the semiconductor substrate 11 by using the stacked structure and the sidewall spacers 14 as masks. And a semiconductor device in which a conventional LED structure for forming the source / drain 16 is adopted.
상기한 바와같이 엘디디구조가 채택된 반도체소자를 도2b에 도시한 바와같이 상기 적층 구조물과 측벽스페이서(14)를 마스크로 하여 소스/드레인(16) 내에 질소이온의 주입조건을 다르게 하여 소스/드레인(16)의 표면이 노출되도록 제1 질소이온 주입층(17)을 형성함과 아울러 그 제1 질소이온 주입층(17)과 소스/드레인(16)을 통해 이격되어 소스/드레인(16)과 반도체기판(11)의 계면에 제2 질소이온 주입층(18)을 형성한다. 이때, 제1 질소이온 주입층(17)의 질소이온 주입조건은 에너지 10KeV∼40KeV, 도우즈(dose) 1×1014cm-2∼6×1015cm-2로 실시하고, 제2 질소이온 주입층(18)의 질소이온 주입조건은 에너지 40KeV∼100KeV, 도우즈 1×1015cm-2∼5×1015cm-2로 실시하는 것이 바람직하다.As shown in FIG. 2B, a semiconductor device having an LED structure as described above is used as a mask for the stack structure and the sidewall spacers 14, so that the source / drain implantation conditions are different. The first nitrogen ion implantation layer 17 is formed to expose the surface of the drain 16, and the source / drain 16 is spaced apart from the first nitrogen ion implantation layer 17 and the source / drain 16. The second nitrogen ion implantation layer 18 is formed at the interface between the semiconductor substrate 11 and the semiconductor substrate 11. In this case, the nitrogen ion implantation conditions of the first nitrogen ion implantation layer 17 are performed at an energy of 10 KeV to 40 KeV, a dose of 1 × 10 14 cm -2 to 6 × 10 15 cm -2 , and the second nitrogen ion Nitrogen ion implantation conditions of the injection layer 18 is preferably performed at an energy of 40 KeV to 100 KeV and a dose of 1 × 10 15 cm −2 to 5 × 10 15 cm −2 .
그리고, 도2c에 도시한 바와같이 상기 노출된 소스/드레인(16)의 표면 및 게이트전극(13) 상에 통상적인 살리사이드공정을 통해 실리사이드층(19)을 형성함으로써, 본 발명의 일 실시예에 따른 반도체소자 및 그 제조를 완료한다.As shown in FIG. 2C, the silicide layer 19 is formed on the exposed surface of the source / drain 16 and the gate electrode 13 through a conventional salicide process, thereby providing an embodiment of the present invention. The semiconductor device according to the present invention and its manufacture are completed.
상기한 바와같은 본 발명에 의한 반도체소자 및 그 제조방법은 제1 질소이온 주입층에 의해 소스/드레인의 표면 상에 형성되는 실리사이드층의 응집(agglomeration)을 방지하여 실리사이드층과 소스/드레인 계면의 거칠기(morphology)를 개선할 수 있어 저항감소 및 후속 콘택공정의 신뢰성을 향상시킬 수 있고, 또한 제1 질소이온 주입층의 질소이온이 Co 실리사이드의 열적안정성을 향상시키며, 제2 질소이온 주입층에 의해 누설전류를 최소화함과 아울러 소스/드레인에 주입된 고농도 불순물이온이 반도체기판으로 확산되는 것을 억제하여 소스/드레인 형성깊이를 조절할 수 있으므로, 고온공정에 따른 소자특성 변화를 방지하여 반도체소자의 신뢰성을 향상시킬 수 있는 효과가 있다.As described above, the semiconductor device and the method of manufacturing the same according to the present invention prevent agglomeration of the silicide layer formed on the surface of the source / drain by the first nitrogen ion implantation layer, thereby preventing the agglomeration of the silicide layer and the source / drain interface. It is possible to improve the morphology, reduce the resistance and improve the reliability of the subsequent contact process, and also the nitrogen ion of the first nitrogen ion implantation layer improves the thermal stability of the Co silicide and the second nitrogen ion implantation layer. By minimizing leakage current and suppressing the diffusion of high concentration of impurity ions injected into the source / drain into the semiconductor substrate, the depth of source / drain formation can be controlled, thereby preventing the change of device characteristics due to high temperature process, thereby ensuring the reliability of the semiconductor device. There is an effect to improve.
Claims (4)
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