WO2019059441A1

WO2019059441A1 - High temperature operating transistor and manufacturing method therefor

Info

Publication number: WO2019059441A1
Application number: PCT/KR2017/010836
Authority: WO
Inventors: 조일환
Original assignee: 명지대학교 산학협력단
Priority date: 2017-09-21
Filing date: 2017-09-28
Publication date: 2019-03-28

Abstract

Embodiments of the present invention provide: a high temperature operating transistor, which has a wide bandgap semiconductor material locally formed in a silicon substrate, can reduce leakage current in a high temperature environment and can provide compatibility with a silicon-based semiconductor manufacturing process, thereby enabling the difficulty level of production to be lower while saving manufacturing costs; and a manufacturing method therefor.

Description

High-temperature operation transistor and manufacturing method thereof

Embodiments of the present invention relate to a high-temperature operating transistor and a method of manufacturing the same.

The following description merely provides the background information related to the embodiments of the present invention and does not constitute the prior art.

Conventional silicon-based metal oxide silicon field-effect transistors (MOSFETs) increase the operating temperature to increase the intrinsic carrier concentration, thereby increasing the leakage current and increasing the power consumption The performance of the transistor device is seriously affected. In recent years, the degree of integration of semiconductor devices is further increased, and the heat and power consumption problems caused thereby are more serious. For this reason, various devices capable of stable operation without generating a leakage current in a high temperature extreme environment have been developed.

Among these semiconductor devices, a wide bandgap semiconductor device based on gallium nitride (GaN) and silicon carbide (SiC) is used for high temperature operation due to high thermal conductivity and excellent bandgap characteristics. It is recognized as a suitable device.

However, these devices are relatively expensive compared to silicon-based devices, and the manufacturing process is complicated. For example, silicon carbide (SiC) materials have various problems such as inherent defect structures of silicon carbide materials called micro-pipe defects. Since gallium nitride (GaN) has a lattice mismatch with silicon (Si), an intermediate buffer layer such as an aluminum gallium nitride (AlGaN) compound layer is required to be used as a semiconductor device.

A silicon-on-insulator substrate-based high temperature operating transistor has been proposed as a way to overcome these problems of wide bandgap semiconductor devices. However, this SOI substrate based high temperature operating transistor still exhibited high leakage current in high temperature operating environment.

Therefore, there is a need for a transistor having advantages over a Si-based semiconductor manufacturing process while exhibiting excellent operating characteristics in a high temperature operating environment.

Embodiments of the present invention have a main purpose in providing a transistor of a new structure which is advantageous in manufacturing process as compared with a transistor using a wide bandgap semiconductor as a main material and can operate at a high temperature.

Embodiments of the present invention have an object to provide a transistor capable of reducing charge injection in a high temperature environment by using a semiconductor substrate with an insulating layer buried therein, thereby reducing a leakage current.

Embodiments of the present invention aim to provide a method of manufacturing a transistor capable of reducing a leakage current in a high temperature environment by locally forming a wide bandgap semiconductor material on a silicon substrate.

One embodiment of the present invention is a semiconductor device comprising: a first region formed in a region of a substrate formed of a first material and separated from the substrate; A second region formed in another region of the substrate and formed in a region separated from the first region; A first insulating layer formed on at least one side of the substrate; A third region in which the first insulating layer is formed on a surface different from a surface in contact with the substrate; A fourth region formed of a second material having a larger energy bandgap than the first material, the fourth region being in contact with at least one surface of the first insulating layer; A first electrode formed on the first region so as to be electrically connected to the first region; A second electrode formed on the second region so as to be electrically connected to the second region; And a third electrode formed on the third region to be electrically connected to the third region.

According to an embodiment of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a fourth region of a second material, which is a material having a larger energy bandgap than the first material, on a region of a substrate formed of a first material; Forming a first insulating layer on at least one side of the substrate such that the first insulating layer is in contact with at least a portion of the fourth region; Forming a first region and a second region separated from each other in the region separated from the substrate; Forming a third region on a surface of the first insulating layer that is different from a surface of the first insulating layer in contact with the substrate; And forming a first electrode, a second electrode and a third electrode so as to be electrically connected to the first region, the second region, and the third region, respectively. do.

According to an embodiment of the present invention, a transistor having a new structure that can be operated at a high temperature while having an advantage in a manufacturing process as compared with a transistor using a wide bandgap semiconductor as a main material is provided.

According to another aspect of the present invention, there is provided an effect of providing a transistor manufacturing method capable of reducing a leakage current in a high-temperature environment by locally forming a wide bandgap semiconductor material on a semiconductor substrate having an insulating layer embedded therein have.

According to another aspect of an embodiment of the present invention, compatibility with the silicon-based semiconductor manufacturing process can be enjoyed, thereby reducing fabrication cost and lowering fabrication difficulty.

1 is a conceptual diagram of a high-temperature operation transistor according to an embodiment of the present invention.

2 is a conceptual diagram of a double gate transistor according to an embodiment of the present invention.

FIGS. 3A, 3B, 3C, 3D, 3E and 3F are diagrams showing steps of the method for manufacturing a high-temperature operating transistor of FIG. 1, and FIG. 4 is a flowchart briefly showing the method.

FIG. 5 is a graph illustrating a gate voltage-drain current of the high-temperature operation transistor shown in FIG. 1 according to a type of a wide bandgap material formed locally.

6 and 7 are simulation results of an energy band diagram of the high-temperature operation transistor shown in FIG.

FIG. 8 is a graph showing the on-off current ratio according to the energy barrier height of the high-temperature operation transistor shown in FIG.

Each of Figs. 9A, 9B and 9C is a conceptual diagram of a high-temperature operating transistor according to an embodiment of the present invention, a simulated gate voltage-drain current graph and an energy It is a band diagram.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that, in the drawings, like reference numerals are used to denote like elements in the drawings, even if they are shown in different drawings. In the following description of the present invention, detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the constituent elements of the embodiment according to the present invention, the first, second, i), ii), a), b) and the like can be used. Such a code is intended to distinguish the constituent element from other constituent elements, and the nature of the constituent element, the order or the order of the constituent element is not limited by the code. It is also to be understood that when an element is referred to as being "comprising" or "comprising", it should be understood that it does not exclude other elements unless explicitly stated to the contrary, do.

Hereinafter, a high-temperature operation transistor and a method of manufacturing the same according to embodiments of the present invention will be described with reference to the accompanying drawings.

The high temperature operation transistor according to an embodiment of the present invention includes a substrate 110, a first region 142, a second region 144, a third region 150, a

fourth region

120, 132, a buried insulating layer 134, a first electrode 162, a second electrode 164, and a third electrode 170.

The substrate 110 may be a semiconductor substrate. In addition, the substrate 110 may be an SOI substrate further comprising a silicon (Si) substrate or a buried insulating layer 134. The substrate 110 may be a wafer formed of a single material such as silicon (Si) and germanium (Ge) wafers, or a compound wafer composed of at least two materials. Further, the substrate 110 may be formed of a single crystal wafer such as a silicon single crystal wafer. However, the substrate 110 is not limited to monocrystalline wafers, and various types of wafers, such as epitaxial wafers, polished wafers, annealed wafers, bonded wafers, . &Lt; / RTI > Here, the epitaxial wafer means a wafer in which a material is crystal-grown on a single crystal silicon substrate.

The buried insulating layer 134 may be formed of an oxide such as SiO ₂ or a nitride such as Si _x N _y . Here, x and y are natural numbers. In addition, the buried insulating layer 134 may be formed of a high-k dielectric material having a large dielectric constant value. For example, the buried insulating layer 134 may be a material comprising or selected from the group consisting of HfO ₂ , ZrO ₂ , TiO ₂ , Ta ₂ O ₅ , Al ₂ O _3, and the like.

A substrate used in a semiconductor device such as a MOSFET is typically doped with n-type or p-type to provide electrons or holes as a charged carrier. In one embodiment of the present invention, the substrate 110 is doped with a p-type dopant and the doping concentration is 1 x 10 ¹⁷ cm ^-3 . The substrate 110 according to an embodiment of the present invention is doped with a p-type dopant to have a doping concentration of 1 x 10 ¹⁷ cm ^-3 , but the dopant type and the doping concentration are not limited thereto (S410).

The fourth region 120 is formed by depositing a material different from the substrate 110 on a trench formed by etching a predetermined region of the substrate 110 to a desired depth.

In the method for manufacturing a high-temperature operating transistor according to an embodiment of the present invention, the etching may be an etching process using a focused ion beam. A hard mask is mainly used for the etching process using the focused ion beam. A hard mask is formed by a method such as spin coating or vapor deposition (S420), and a portion to be etched in the hard mask is patterned. Thereafter, a trench is formed using a focused ion beam, and a fourth region 120 is formed by depositing a material different from the substrate 110 on the formed trench. In addition, by performing a chemical mechanical polishing (CMP) process or an etching process, a process of planarizing a portion of the substrate 110 other than the portion where the fourth region 120 is formed and the fourth region 120 is followed, So that it can be performed smoothly. In addition to the CMP or etching process, this planarization process may be performed by combining various physical polishing processes or chemical etching processes (S430).

As described above, the shape of the fourth region 120 is determined by an etching process using a focused ion beam. Here, when the substrate 110 is an SOI substrate further including a buried insulating layer 134, the fourth region 120 may be formed to contact one surface of the buried insulating layer 134.

Thereafter, the first region 142 and the second region 144 are formed in a partial region on the substrate 110 (S440).

The first region 142 may be formed to have a region separated from the substrate 110 by doping a portion of the substrate 110 with a dopant of a type different from the dopant doped to the substrate 110.

On the other hand, the substrate 110 can be divided into two regions by the buried insulating layer 134. In some of the areas including the first area 142 and the second area 144, a part of the area where the first area 142 and the second area 144 are not included is higher than the area not including the first area 142 and the second area 144 Additional doping may be performed to have a doping concentration to form a fifth region 112 that is distinct from the portion where no further doping is performed. This additional doping may be performed at any time prior to the process of forming the first region 142 and the second region 142. When the substrate 110 is doped with a p-type dopant to have a doping concentration of 1 × 10 ¹⁷ cm ^-3 , the fifth region 112 may be doped to have a doping concentration of 1 × 10 ¹⁷ cm ^-3 or more.

In one embodiment of the present invention, the first region 142 is doped n-type because the substrate 110 is doped p-type. Doping can be performed through various methods such as a diffusion process, an ion implantation process, and the like. Doping methods such as the ion implantation process are preferred for precise doping to the designed area.

The second region 144 may be formed to have a region separated from the substrate 110 by doping a portion of the substrate 110 with a dopant of a type different from that doped to the substrate 110. [ The second region 144 may be formed to be spaced a predetermined distance horizontally from the first region 142. In one embodiment according to the present invention, the second region 144 may be formed using the same doping process under the same doping conditions as the first region 142. However, the second region 142 may be formed under different conditions using a dopant different from the dopant used in the first region 141. [ Each of the first region 142 and the second region 144 may function as a source and a drain or a drain and a source. In one embodiment of the present invention, the doping concentrations of the first region 132 and the second region 134 are all 1 × 10 ²⁰ cm ^-3 .

The first insulating layer 132 is formed to cover at least a part of the exposed region of the fourth region 120. Here, the exposed region of the fourth region 120 refers to the side of the CMP process.

The first insulating layer 132 may be formed to cover the entirety of the fourth region 120 as the case may be. The first insulating layer 132 may be formed to a thickness of 10 nm or less, but is not limited thereto.

The first insulating layer 132 may be formed by a chemical vapor deposition (CVD) method, a low pressure chemical vapor deposition (LPCVD) method, an atmospheric pressure chemical vapor deposition (APCVD) method, Various atomic or molecular deposition methods such as low temperature chemical vapor deposition (LTCVD), plasma enhanced chemical vapor deposition (PECVD), and atomic layer chemical vapor deposition (ALCVD) As shown in FIG.

The third region 150 may be formed by depositing a semiconductor material or a metal material on the first insulating layer 132. A third region 150 of the high temperature operating transistor according to an embodiment of the present invention may be formed by depositing polysilicon (S450).

A third electrode 170 electrically connected to the third region 150 is formed to apply a voltage to the third region 150, that is, the first insulating layer 132 formed under the third region 150 .

The third region 150 controls the on / off of the current flowing through the semiconductor region located under the first insulating layer 132, that is, the channel region, through the control of the voltage applied through the third electrode 166 So that it can function as a gate. The gate may have a structure including the third electrode 150 in the third region 150 or the third region 150. According to the embodiment, the third electrode 170 may be omitted.

Although a portion of the substrate 110 functions as a channel region in one embodiment of the present invention, the substrate 110 may be formed of a different material. In addition, the channel region may be doped with a different concentration using a dopant of a type different from that of the dopant doped to the substrate 110.

The first electrode 162 and the second electrode 164 may have a first region 142 and a second region 144 to electrically connect the first region 142 and the second region 144 to the outside, As shown in Fig. The first electrode 162 and the second electrode 164 may be formed so as to cover the entire first region 142 and the second region 144 in order to reduce a resistance component such as a contact resistance.

Since the buried insulating layer 134 is formed of an insulating material through which a charged carrier can not pass, when the fourth region 120 is formed to contact one surface of the buried insulating layer 134, The current path connecting the first region 142 and the second region 144 must be formed so as to pass through the fourth region 120.

The lower end of the fourth region 120 need not contact the buried insulating layer 134 if the first region 142 and the second region 144 are sufficiently far away from the buried insulating layer 134. That is, a current path between the first region 142 and the second region 144 is formed immediately below the first insulating layer 132, and no matter how much voltage is applied to the third electrode 170, The depth of the fourth region 120 may be shorter than that shown in FIG. 1 when the path is formed only in a portion directly under the first insulating layer 132. [

The current path formed between the first region 142 and the second region 144 is a current path between the first electrode 162 and the third electrode 164, It depends on the potential difference.

A double gate transistor according to an embodiment of the present invention includes a substrate 210, a first region 242, a second region 244, a

third region

252, 254, a fourth region 220,

Layers

232 and 234, a first electrode 262, a second electrode 264 and a

third electrode

272 and 274.

A double gate transistor according to an embodiment of the present invention can be manufactured by applying a process of forming a fourth region 220 to a conventional process for fabricating a conventional double gate transistor.

A fourth region 220 of the double gate transistor according to an embodiment of the present invention is formed by depositing a material other than the substrate 210 on a trench formed by etching to penetrate a predetermined region of the substrate 210. The subsequent steps are the same as in the method for manufacturing a high-temperature operating transistor shown in Fig.

3A shows a process of preparing the substrate 110 including the buried insulating layer 134 (S410).

FIG. 3B illustrates a process of preparing a mask to form a trench in a portion of the substrate 110 including the buried insulating layer 134. FIG. When using focused ion beam etching, a hard mask is preferred.

3C shows a state after removing a part of the substrate 110 using a focused ion beam etching. In order to form the fourth region 120 in contact with the buried insulating layer 134, the depth of the trench is formed so as to contact the top surface of the buried insulating layer 134 (S420).

FIG. 3D shows the shape of the high-temperature operation transistor after forming the substrate 110 and another material in the formed trench and performing the process of planarizing the surface using the CMP process or the etching process. As shown in the figure, the lower end of the fourth region 120 contacts the upper surface of the buried insulating layer 134, and the upper end of the fourth region 120 is exposed to the outside (S430).

FIG. 3E illustrates a process of forming the first region 142 and the second region 144 in a part of the substrate 110. FIG. When the substrate 110 is a p-type semiconductor material, the first region 142 and the second region 144 may be formed by doping with n-type through an ion implantation process (S440).

In addition, the process of forming the first region 142 and the second region 144 may further include a process of forming a carrier having a charge different from that of the substrate 110 by using an ion implantation process and a heat treatment process can do.

3F illustrates a process of forming the first insulating layer 132, the third region 150, the first electrode 162, the second electrode 164, and the third electrode 170. Referring to FIG. The first insulating layer 132 is formed to cover at least a part of the exposed region of the fourth region 120. The first insulating layer 132 may be formed to cover the entirety of the fourth region 120 as the case may be. The first insulating layer 132 may be formed to a thickness of about 10 nm or less, but is not limited thereto. The third region 150 may be formed by depositing a semiconductor material or a metal material on the first insulating layer 132. Here, the semiconductor material may be one semiconductor material or one or more compound semiconductor materials. Further, the metal material may be a single metal material or a mixed metal material including at least two metal materials. Also, the metal material may be an alloy including at least two metal materials. A third region 150 of the high temperature operating transistor in accordance with an embodiment of the present invention is formed by depositing polycrystalline silicon on the first insulating layer 132. The first electrode 162 and the second electrode 164 may have a first region 142 and a second region 144 to electrically connect the first region 142 and the second region 144 to the outside, As shown in Fig. The first electrode 162 and the second electrode 164 may be formed so as to cover the entire first region 142 and the second region 144 in order to reduce a resistance component such as a contact resistance (S450) .

In order to optimize the device structure, simulation was carried out in Thermode using Synopsys Sentaurus TCAD to examine the change of electrical characteristics according to temperature of a high temperature operation transistor according to an embodiment of the present invention. Shockley-Read-Hall recombination, Fermi statistics, as well as doping and field-dependent mobility. For the sake of simulation, the gate length, that is, the length of the first insulating layer 132 was set to 100 nm, and the thickness of the first insulating layer 132 was set to 3 nm. The thickness of the buried insulating layer 134 was set at 10 nm, and the width of the fourth region was set at 10 nm. The doping concentration of the substrate 110 is a SOI substrate doped with p-type is 1 × 10 ¹⁷ cm ^- was set to ^3, the doping concentration of the first region 132 and second region 134 is 1 × 10 ²⁰ cm ^{- 3} was set.

In order to examine the electrical operation characteristics of the high temperature operation transistor according to an embodiment of the present invention, the temperature was set to 573 K and the drain voltage V _D was set to 0.2 V. [ The materials used in the fourth region 120 for the simulation are silicon (Conventional SOI MOSFET), 6H structure silicon carbide (SiC-6H SOI MOSFET), 4H structure silicon carbide (SiC-4H SOI MOSFET), GaP SOI MOSFET) and AlP (AlP SOI MOSFET).

Referring to FIG. 5, when the GaP or AlP compound is used as the material of the fourth region 120, it can be seen that the on / off current ratio is much larger than that of the transistor using the conventional SOI substrate. The energy band along the channel direction is shown in order to examine why the ON / OFF current ratio of the SOI transistor using the compound such as GaP or AlP is much larger.

The energy band diagram shown in FIG. 6 is an energy band diagram when the gate voltage V _G is 0 V, that is, when the high-temperature operation transistor according to an embodiment of the present invention is in an off state. 6, it can be seen that an electron energy barrier is formed between the source and the channel region. This is because the fourth region 120 (see the inner figure at the bottom right of FIG. 6) . The electron energy barrier formed by the fourth region 120 serves to prevent electrons from the source from moving to the channel region in the off state.

The energy band diagram shown in FIG. 7 is an energy band diagram when the gate voltage V _G is 15 V, that is, when the high-temperature operation transistor according to an embodiment of the present invention is on-state. As shown in Fig. 7, when a voltage is applied to the gate, the electron energy barrier formed between the source and the channel region is lowered, electrons can be injected into the channel region, and current can flow accordingly. 7 is determined to be due to the trap charge existing at the boundary between the first region 132 and the fourth region 120. In this case,

Here, the on current and the off current are the measured currents when the gate voltages are 14 V and -2 V, respectively. As can be seen in Fig. 8, as the height of the energy barrier increases, the on-off current ratio also increases substantially proportionally.

Assuming that A is the length of the portion where the fourth region 120 overlaps the first insulating layer 132 and B is the entire width of the fourth region 120, the overlap ratio (OR) is A / B .

In this case, the substrate 110 is a p-type doped SOI substrate, and the fourth region 120 is GaP. As shown in FIG. 9A, it can be seen that the larger the portion where the fourth region 120 and the first insulating layer 132 overlap, the larger the on-off current ratio is.

In addition, when the overlap ratio is 100% or less, it can be seen that a large energy barrier is still formed near the source, and this energy barrier is considered to prevent the increase of the on current.

In FIGS. 3 and 4, it is described that each process is sequentially executed, but it is not limited thereto. In other words, it can be applied to changing the processes described in FIG. 3 and FIG. 4 or executing one or more processes in parallel. Thus, FIGS. 3 and 4 are not limited to time series.

3 and 4 may be implemented as computer-readable codes in a computer-readable recording medium. A computer-readable recording medium includes all kinds of recording apparatuses in which data that can be read by a computer system is stored. That is, a computer-readable recording medium includes a magnetic storage medium (e.g., ROM, floppy disk, hard disk, etc.), an optical reading medium (e.g., CD ROM, And the like). In addition, the computer-readable recording medium may be distributed over a network-connected computer system so that computer-readable code can be stored and executed in a distributed manner.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims. Modifications and variations will be possible. Therefore, the embodiments according to the present invention are not intended to limit the scope of the technical idea of the present embodiment, but are intended to be illustrative, and the scope of the technical idea of the present embodiment is not limited by these embodiments. The scope of protection of an embodiment according to the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be interpreted as being included in the scope of the embodiment of the present invention.

(Explanation of Symbols)

110, 210: substrate 112: fifth region

120, 220:

fourth region

132, 232, 234: first insulating layer

134: second insulating layer 142, 242: first region

144, 244:

second area

150, 252, 254: third area

160, 290: fourth region 162, 262: first electrode

164, 264:

second electrode

170, 272, 274: third electrode

CROSS-REFERENCE TO RELATED APPLICATION

This patent application claims priority under 35 USC § 119 (a) to U.S. Patent Application No. 119 (a), U.S. Patent Application No. 10-2017-0122034, filed on September 21, 2017, All content is incorporated herein by reference. In addition, this patent application claims priority to the countries other than the United States for the same reason as above, and the entire contents of which are incorporated herein by reference.

Claims

A first region formed in a region of the substrate formed of the first material and separated from the substrate;

A second region formed in another region of the substrate and formed in a region separated from the first region;

A first insulating layer formed on at least one side of the substrate;

A third region in which the first insulating layer is formed on a surface different from a surface in contact with the substrate;

A fourth region formed of a second material having a larger energy bandgap than the first material, the fourth region being in contact with at least one surface of the first insulating layer;

A first electrode formed on the first region so as to be electrically connected to the first region;

A second electrode formed on the second region so as to be electrically connected to the second region; And

A third electrode formed on the third region so as to be electrically connected to the third region,

Lt; RTI ID = 0.0 > 1, < / RTI >
The method according to claim 1,

Wherein the fourth region comprises:

Wherein a current path formed between the first region and the second region is formed so as to pass through the fourth region.
3. The method of claim 2,

Wherein the first region and the second region are arranged in a matrix,

Lt; RTI ID = 0.0 > 1, < / RTI > is doped to provide the same charged carrier.
The method of claim 3,

Wherein:

Lt; RTI ID = 0.0 > 1, < / RTI > wherein the first region and the second region are doped to provide carriers with different charges.
5. The method of claim 4,

A second insulating layer is added to a surface other than a surface in contact with the first insulating layer so that a current path formed between the first and second regions can pass through the fourth path through the minimum path. Temperature transistor.
6. The method of claim 5,

Wherein:

And a fifth region in which a doping concentration is higher than that of the remaining one region by performing additional doping in a region to which the first region and the second region belong, out of two regions separated by the second insulating layer Features a high temperature operating transistor.
The method according to claim 6,

And a current path formed between the first region and the second region,

Wherein the first electrode and the second electrode are different from each other depending on a magnitude of a voltage applied to the third electrode and a potential difference between the first electrode and the third electrode.
5. The method of claim 4,

Wherein:

Wherein the substrate is a substrate including an insulating layer at a predetermined position inside the substrate.
3. The method of claim 2,

Wherein the fourth region comprises:

Wherein the first insulating layer is formed so as to maximize an area in contact with the first insulating layer.
10. The method of claim 9,

Wherein the first region and the second region are simultaneously formed in a single process.
Forming a fourth region from a second material that is a material having a larger energy band gap than the first material in a region of the substrate formed of the first material;

Forming a first insulating layer on at least one side of the substrate such that the first insulating layer is in contact with at least a portion of the fourth region;

Forming a first region and a second region separated from each other in the region separated from the substrate;

Forming a third region on a surface of the first insulating layer that is different from a surface of the first insulating layer in contact with the substrate; And

Forming a first electrode, a second electrode, and a third electrode so as to be electrically connected to the first region, the second region, and the third region, respectively;

Gt; a < / RTI > high-temperature operation transistor.
12. The method of claim 11,

The forming of the fourth region may include:

The process of preparing and etching the mask;

Depositing the second material; And

Removing at least a portion of the portion including the second material by using a chemical or physical method

Gt; a < / RTI > high-temperature operation transistor.
13. The method of claim 12,

The process of forming the first region and the second region may include:

And forming a carrier having a charge different from that of the substrate by using an ion implantation process and a heat treatment process.
13. The method of claim 12,

The etching process may include:

And forming a pattern at a nm level using a focused ion beam.