CN111710713B - Fin type field effect transistor, manufacturing method thereof and electronic equipment - Google Patents
Fin type field effect transistor, manufacturing method thereof and electronic equipment Download PDFInfo
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- CN111710713B CN111710713B CN202010399407.1A CN202010399407A CN111710713B CN 111710713 B CN111710713 B CN 111710713B CN 202010399407 A CN202010399407 A CN 202010399407A CN 111710713 B CN111710713 B CN 111710713B
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention discloses a fin field effect transistor, a manufacturing method thereof and electronic equipment, and relates to the technical field of semiconductors. The fin field effect transistor includes a substrate, an isolation layer, a fin structure, and a gate stack structure. An isolation layer is formed on the substrate. The fin structure is formed on the isolation layer. The fin structure extends in a first direction. The fin structure includes a source region, a drain region, and a channel region in contact with the source region and the drain region, respectively. The area of the isolation layer covering the substrate is smaller than or equal to the area of the fin structure covering the substrate. The gate stack structure is formed at an outer periphery of the channel region. The gate stack extends in a second direction. The manufacturing method of the fin field effect transistor is used for manufacturing the fin field effect transistor provided by the technical scheme. The fin field effect transistor provided by the invention is applied to electronic equipment.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a fin field effect transistor, a manufacturing method thereof, and an electronic device.
Background
In the fabrication of a fin field effect transistor, a Silicon-On-Insulator (SOI) substrate is generally selected as a substrate of the fin field effect transistor in order to suppress parasitic channel and source-drain leakage. The source region, the drain region and other structures in the fin field effect transistor are formed on the buried oxide layer. The buried oxide layer is a non-conductive insulating layer, so that the leakage problem of a parasitic channel and a source drain can be solved.
However, the cost of the existing SOI substrate is high, so that the manufacturing cost of the fin field effect transistor is high.
Disclosure of Invention
The invention aims to provide a fin field effect transistor, a manufacturing method thereof and electronic equipment, wherein an isolation layer is formed between a fin structure and a substrate to inhibit parasitic channels and source-drain leakage, and an SOI substrate with higher cost is not required to be used, so that the manufacturing cost of the fin field effect transistor is reduced.
In order to achieve the above object, the present invention provides a fin field effect transistor including:
the substrate is provided with a plurality of holes,
an isolation layer formed on the substrate;
the fin structure is formed on the isolation layer and extends along a first direction, the fin structure comprises a source region, a drain region and a channel region, the channel region is positioned between the source region and the drain region, the channel region is respectively contacted with the source region and the drain region, and the area of the isolation layer covering the substrate is smaller than or equal to that of the fin structure covering the substrate;
and a gate stack structure formed at an outer periphery of the channel region, the gate stack structure extending in the second direction.
Compared with the prior art, the fin field effect transistor provided by the invention has the advantages that the isolation layer is formed between the substrate and the fin structure. Under the condition that the grid stacking structure is loaded with proper voltage, the source region and the drain region can be conducted only through the channel region and cannot be conducted with a substrate positioned under the isolation layer, so that the problems of parasitic channels and source-drain leakage can be solved. Meanwhile, the isolation layer is a film layer formed on the substrate subsequently and does not form a part of the substrate, so that in the process of manufacturing the fin field effect transistor, the parasitic channel and source-drain leakage problems can be solved by adopting other substrates meeting requirements, such as a silicon substrate or a germanium-silicon substrate, which have lower cost than an SOI substrate, and the manufacturing cost of the fin field effect transistor can be reduced.
The invention also provides a manufacturing method of the fin field effect transistor, which comprises the following steps:
providing a substrate;
forming an isolation layer on a substrate;
forming a fin structure on the isolation layer, wherein the fin structure extends along a first direction and comprises a source region, a drain region and a channel region, the channel region is positioned between the source region and the drain region, the channel region is respectively contacted with the source region and the drain region, and the area of the isolation layer covering the substrate is smaller than or equal to that of the fin structure covering the substrate;
a gate stack structure is formed at an outer periphery of the channel region, the gate stack structure extending in the second direction.
Compared with the prior art, the fin field effect transistor manufacturing method has the advantages that the fin field effect transistor manufacturing method is the same as the fin field effect transistor manufacturing method provided by the technical scheme, and details are omitted here.
The invention also provides electronic equipment which comprises the fin field effect transistor provided by the technical scheme.
Compared with the prior art, the beneficial effects of the electronic device provided by the invention are the same as those of the fin field effect transistor provided by the technical scheme, and the description is omitted here.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:
fig. 1 is a schematic structural diagram of a fin field effect transistor according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a structure of a substrate with a material layer to be oxidized and a pre-semiconductor material layer formed thereon according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a structure after forming a material layer to be oxidized, a pre-semiconductor material layer and a silicon material layer on a substrate according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a structure after forming a layer to be oxidized, a semiconductor material layer and a hard mask pattern on a substrate according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a structure after forming a layer to be oxidized, a semiconductor material layer, a silicon layer and a hard mask pattern on a substrate according to an embodiment of the present invention;
FIG. 6 is a cross-sectional view of the structure of FIG. 4 taken along the line B-B;
FIG. 7 is a cross-sectional view of the structure of FIG. 5 taken along the line B-B;
FIG. 8 is a cross-sectional view of the structure of FIG. 4 taken along the line A-A;
FIG. 9 is a cross-sectional view of the structure of FIG. 5 taken along the line A-A;
FIG. 10 is a cross-sectional view of the structure along the B-B direction after forming the spacer in accordance with an embodiment of the present invention;
FIG. 11 is a cross-sectional view of another embodiment of the present invention taken along the B-B direction after forming the spacer;
FIG. 12 is a cross-sectional view of the structure taken along the direction A-A after forming the spacer in accordance with an embodiment of the present invention;
FIG. 13 is a cross-sectional view of another embodiment of the present invention taken along the A-A direction after forming the spacer;
FIG. 14 is a cross-sectional view of a structure taken along line B-B in an embodiment of the present invention after removal of the hard mask pattern and oxidized portions of the semiconductor material layer;
FIG. 15 is a cross-sectional view of a rear edge B-B structure with portions of the hard mask pattern, semiconductor material layer and silicon layer oxidized removed in accordance with an embodiment of the present invention;
FIG. 16 is a cross-sectional view of a structure along A-A after removing the hard mask pattern and oxidized portions of the semiconductor material layer in accordance with an embodiment of the present invention;
FIG. 17 is a cross-sectional view of a rear edge A-A of an embodiment of the invention in which the hard mask pattern, semiconductor material layer, and oxidized portion of the silicon layer are removed;
FIG. 18 is a cross-sectional view of the structure taken along the direction B-B after shallow trench isolation is formed in accordance with an embodiment of the present invention;
FIG. 19 is a cross-sectional view of another embodiment of the present invention taken along the B-B direction after shallow trench isolation is formed;
FIG. 20 is a cross-sectional view of the structure taken along the direction A-A after shallow trench isolation is formed in accordance with an embodiment of the present invention;
FIG. 21 is a cross-sectional view of another embodiment of the present invention taken along the A-A direction after shallow trench isolation is formed;
FIG. 22 is a cross-sectional view of the structure along the B-B direction after forming a sacrificial gate in accordance with an embodiment of the present invention;
FIG. 23 is a cross-sectional view of another embodiment of the present invention taken along the B-B direction after forming a sacrificial gate;
FIG. 24 is a cross-sectional view of the structure taken along the A-A direction after forming a sacrificial gate in an embodiment of the present invention;
FIG. 25 is a cross-sectional view of another embodiment of the present invention taken along the A-A direction after forming a sacrificial gate;
FIG. 26 is a cross-sectional view of the structure taken along the A-A direction with the source and drain region forming regions removed in an embodiment of the present invention;
FIG. 27 is a cross-sectional view of another embodiment of the present invention taken along the A-A direction after the source and drain region formation regions have been removed;
FIG. 28 is a cross-sectional view of the latter configuration along the A-A direction, after forming source and drain regions in an embodiment of the present invention;
FIG. 29 is a cross-sectional view of another embodiment of the present invention taken along the A-A direction after forming source and drain regions;
FIG. 30 is a cross-sectional view of the first dielectric layer and the second dielectric layer formed in accordance with an embodiment of the present invention taken along the A-A direction;
FIG. 31 is a cross-sectional view of another embodiment of the present invention taken along the A-A direction after forming a first dielectric layer and a second dielectric layer;
FIG. 32 is a cross-sectional view of the gate stack structure along the A-A direction in accordance with an embodiment of the present invention;
FIG. 33 is a cross-sectional view of another embodiment of the present invention taken along the A-A direction after forming a gate stack;
FIG. 34 is a cross-sectional view of another embodiment of the present invention taken along the B-B direction after forming a gate stack;
fig. 35 is a flowchart of a method for fabricating a fin field effect transistor according to an embodiment of the present invention.
Reference numerals:
1 is a substrate, 2 is an isolation layer, 3 is a fin structure, 31 is a source region, 32 is a drain region, 33 is a channel region, 4 is a gate stack structure, 41 is a gate dielectric layer, 42 is a gate, 5 is a layer to be oxidized, 6 is a semiconductor material layer, 61 is a source region forming region, 62 is a drain region forming region, 7 is a silicon layer, 8 is a hard mask pattern, 9 is a sacrificial gate, 10 is a first sidewall, 11 is a second sidewall, 12 is a first dielectric layer, 13 is a second dielectric layer, and 14 is shallow trench isolation.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned. In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise. The meaning of "a number" is one or more than one unless specifically defined otherwise.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
The problem of parasitic channel and source drain leakage has been one of the major factors affecting the performance of fin field effect transistors. In the prior art, the following two methods are generally adopted to solve the leakage problem of the parasitic channel and the source drain:
specifically, an SOI substrate is selected as a substrate of a fin field effect transistor, and at this time, structures such as a source region and a drain region in the fin field effect transistor are formed on a buried oxide layer of the SOI substrate. Because the buried oxide layer is a non-conductive insulating layer, the leakage problem of a parasitic channel and a source drain can be solved. However, the cost of the existing SOI substrate is high, so that the manufacturing cost of the fin field effect transistor is high.
Another is to perform an anti-punch-through implantation process on the fin after the fin is formed (the fin is composed of a semiconductor material layer) to form a punch-through barrier layer at the bottom of the fin. The source region, the drain region, the channel region and other structures in the fin field effect transistor are formed on the punch-through barrier layer, and impurities with high concentration and opposite impurity types to those in the source region and the drain region are injected into the punch-through barrier layer, so that leakage current can be isolated through a PN junction with reverse bias, and parasitic channels and source-drain leakage are restrained. However, during the formation of the punch-through blocking layer, the anti-punch-through implant may cause an uneven impurity concentration profile in regions within the channel region. For example: impurities in the punch-through barrier layer are affected by the subsequent high-temperature annealing to diffuse into the channel region, resulting in degradation of carrier mobility inside the channel region, so that the driving performance of the fin field effect transistor is reduced.
In order to solve the technical problems, the embodiment of the invention provides a fin field effect transistor, a manufacturing method thereof and electronic equipment. In the fin field effect transistor provided by the embodiment of the invention, an isolation layer is formed between the substrate and the fin structure. The existence of the isolation layer can solve the problem of leakage of a parasitic channel and a source drain. And the isolation layer is a film layer formed on the substrate later, and an SOI substrate with higher cost is not needed, so that the manufacturing cost of the fin field effect transistor is reduced.
The embodiment of the invention provides a fin field effect transistor, and particularly referring to fig. 1, 33 and 34, the fin field effect transistor comprises a substrate 1, an isolation layer 2, a fin structure 3 and a gate stack structure 4. The substrate 1 may be a semiconductor substrate having a low cost, such as a silicon substrate or a silicon germanium substrate. In some cases, shallow trench isolations 14 are formed on the substrate 1 to define the respective active regions. The material of the shallow trench isolation 14 may be SiN or Si 3 N 4 、SiO 2 Or an insulating material such as SiCO.
As shown in fig. 1, 33 and 34, the above-described isolation layer 2 is formed on the substrate 1, that is, the isolation layer 2 in the embodiment of the present invention is a film layer formed subsequently on the substrate 1, and does not constitute a part of the substrate 1. In this case, a semiconductor substrate such as a silicon substrate having a low cost can be used in the process of manufacturing the fin field effect transistor. And the isolation layer 2 is formed on the semiconductor substrate, so that the leakage problem of a parasitic channel and a source drain can be solved without using an SOI substrate containing a buried oxide layer.
As to whether the separator 2 is of a single-layer structure or a multi-layer structure, the material contained in the separator 2, and the layer thickness of the separator 2 may be designed according to practical application scenarios, and are not particularly limited herein. The material contained in the isolation layer 2 is illustratively silicon oxide or silicon germanium oxide. The thickness of the isolation layer 2 is 5nm to 50nm. Further, the preferable layer thickness of the spacer layer 2 is 10nm to 20nm.
The shallow trench isolation 14 is formed on a portion of the substrate 1 where the isolation layer 2 is not formed.
As shown in fig. 1, 33 and 34, the fin structure 3 is formed on the isolation layer 2. The fin structure 3 extends in a first direction, and the fin structure 3 includes a source region 31, a drain region 32, and a channel region 33. A channel region 33 is located between the source region 31 and the drain region 32, the channel region 33 being in contact with the source region 31 and the drain region 32, respectively. The area of the isolation layer 2 covering the substrate 1 is smaller than or equal to the area of the fin structure 3 covering the substrate 1. It should be understood that in the process of manufacturing the fin field effect transistor, if, after the sacrificial gate 9, the first sidewall 10 and the second sidewall 11 are formed, the source region 31 and the drain region 32 are formed directly based on the source region formation region 61 and the drain region formation region 62 included in the semiconductor material layer 6 (or based on the regions of the semiconductor material layer 6 and the silicon layer 7 corresponding to the source region formation region 61 and the drain region formation region 62), respectively, then the area of the spacer layer 2 covering the substrate 1 is equal to the area of the fin structure 3 covering the substrate 1. In another case, as shown in fig. 26 to 29, in the process of manufacturing the fin field effect transistor described above, if the source region formation region 61 and the drain region formation region 62 included in the semiconductor material layer 6 (or the regions of the semiconductor material layer 6 and the silicon layer 7 corresponding to the source region formation region 61 and the drain region formation region 62) are removed after the formation of the sacrificial gate 9, the first sidewall 10, and the second sidewall 11. Thereafter, the source region 31 and the drain region 32 are formed epitaxially at positions corresponding to the source region formation region 61 and the drain region formation region 62, and on part of the shallow trench isolation 14, respectively. The area of the subsequently formed source region 31 covering the substrate 1 is larger than the area of the source region forming region 61 covering the substrate 1, and the area of the subsequently formed drain region 32 covering the substrate 1 is larger than the area of the drain region forming region 62 covering the substrate 1. At this time, the area of the isolation layer 2 covering the substrate 1 is smaller than the area of the fin structure 3 covering the substrate 1. As is clear from the above, the spacer 2 is formed only under the fin structure 3 in any of the above-described modes for forming the source region 31 and the drain region 32. Meanwhile, the bottoms of the source region 31 and the drain region 32 are both in contact with the spacer 2, or are both in contact with the spacer 2 and the shallow trench isolation 14. The isolation layer 2 and the shallow trench isolation 14 are made of non-conductive insulating materials, so that the existence of the isolation layer 2 can solve the problem of parasitic channel and source-drain leakage.
As for the material contained in the source region 31 and the drain region 32, a semiconductor material may be Si, siGe, ge, or the like. The source region 31 and the drain region 32 may be made of the same material or different materials. The channel region 33 may comprise Si or Si 1-x Ge x Wherein x is more than 0 and less than or equal to 0.6. The specific content of Ge in the channel region 33 may be selected according to the actual situation. Specifically, the higher the Ge content in the channel region 33, the higher the carrier mobility possessed by the channel region 33.
Note that, the first direction may be set according to practical situations, and is not specifically limited herein.
As shown in fig. 1, 33 and 34, the portion of the spacer 2 under the source region 31 and the portion of the spacer 2 under the drain region 32 may be flush with each other, or the heights of the tops of the two portions may be slightly different. Specifically, the heights of the portions of the isolation layer 2 may be designed according to practical application scenarios, so long as the isolation layer can be applied to the fin field effect transistor provided in the embodiment of the present invention. It should be noted that when the tops of the two portions are level, variations in junction depth can be avoided. In addition, the isolation layer 2 is of a solid structure, and the position of the isolation layer is not changed due to the influence of high-temperature annealing and the like, namely, the problem that impurities in the similar punch-through barrier layer are affected by subsequent high-temperature annealing and diffused into the channel region 33 is avoided, so that the working performance of the fin field effect transistor is more stable.
As shown in fig. 1, 33, and 34, the gate stack structure 4 described above is formed on the outer periphery of the channel region 33. And, the gate stack structure 4 extends in the second direction. Specifically, the gate stack structure 4 may include a gate dielectric layer 41 and a gate electrode 42 formed on the periphery of the channel region 33. The gate dielectric layer 41 may be made of HfO 2 、ZrO 2 、TiO 2 Or Al 2 O 3 A material having a relatively high dielectric constant. The material contained in the gate electrode 42 may be a conductive material such as TiN, taN, or TiSiN. Further, the second direction intersects the first direction. For example: the second direction is orthogonal to the first direction.
The following describes in detail the manufacturing process of the fin field effect transistor according to the embodiment of the present invention with reference to fig. 35:
step S101: a substrate 1 is provided.
Step S102: an isolation layer 2 is formed on a substrate 1.
Step S103: fin structures 3 are formed on the isolation layer 2. The fin structure 3 extends in a first direction. Fin structure 3 includes a source region 31, a drain region 32, and a channel region 33, channel region 33 being located between source region 31 and drain region 32. The channel region 33 is in contact with the source region 31 and the drain region 32, respectively. The area of the isolation layer 2 covering the substrate 1 is smaller than or equal to the area of the fin structure 3 covering the substrate 1.
Step S104: a gate stack structure 4 is formed at the outer periphery of the channel region 33. The gate stack 4 extends in the second direction.
Based on the structure and the manufacturing process of the fin field effect transistor provided by the embodiment of the invention, the isolation layer 2 is formed between the substrate 1 and the fin structure 3 in the fin field effect transistor provided by the embodiment of the invention. Under the condition that the gate stack structure 4 is loaded with proper voltage, the existence of the isolation layer 2 can lead the source region 31 and the drain region 32 to be conducted only through the channel region 33 and not to be conducted with the substrate 1 positioned under the isolation layer 2, so that the parasitic channel and source-drain leakage problems can be solved. Meanwhile, the isolation layer 2 is a film layer subsequently formed on the substrate 1, and does not constitute a part of the substrate 1. Under the above circumstances, in the process of manufacturing the fin field effect transistor, a silicon substrate or a germanium-silicon substrate with lower cost than the SOI substrate or other substrates meeting the requirements can be adopted, and the problem of electric leakage of a parasitic channel and a source drain can be solved without using the SOI substrate with higher cost, so that the manufacturing cost of the fin field effect transistor is reduced.
In an alternative manner, as shown in fig. 1, 33 and 34, the fin field effect transistor further includes a first sidewall 10 and a second sidewall 11 formed on the substrate 1. The first side wall 10 and the second side wall 11 extend in the second direction. The gate stack structure 4 is formed between the first sidewall 10 and the second sidewall 11.
For the first sidewall 10 and the second sidewall 11, the material contained in the first sidewall 10 and the second sidewall 11 may be SiN or SiO 2 And insulating materials. The widths of the first side wall 10 and the second side wall 11 may be designed according to practical application scenarios, and are not particularly limited herein.
In an alternative manner, as shown in fig. 1, 33 and 34, the fin field effect transistor further includes a first dielectric layer 12 and a second dielectric layer 13. The first dielectric layer 12 overlies the source region 31. The second dielectric layer 13 overlies the drain region 32. It will be appreciated that the presence of the first dielectric layer 12 and the second dielectric layer 13 during fabrication of the fin field effect transistor may protect the source region 31 and the drain region 32 from etching, cleaning, etc. operations when etching the sacrificial gate 9.
As for the material contained in the first dielectric layer 12 and the second dielectric layer 13, siO may be used 2 Or an insulating material such as SiN.
The embodiment of the invention also provides a manufacturing method of the fin field effect transistor, as shown in fig. 35, the manufacturing method further comprises the following steps:
step S101: a substrate 1 is provided. Reference is made to the foregoing for selection of the substrate 1, and no further description is given here.
Step S102: as shown in fig. 2 to 17, an isolation layer 2 is formed on a substrate 1.
Specifically, as shown in fig. 2 to 17, forming the isolation layer 2 on the substrate 1 includes:
step S102.1: as shown in fig. 2 and 4, a layer 5 to be oxidized, and a semiconductor material layer 6 on the layer 5 to be oxidized are formed on the substrate 1. The semiconductor material layer 6 includes a source region formation region 61, a drain region formation region 62, and a channel region 33. The channel region 33 is located between the source region formation region 61 and the drain region formation region 62.
Illustratively, as shown in fig. 2, a layer of a material to be oxidized covering the substrate 1 and a layer of a pre-semiconductor material covering the layer of the material to be oxidized are sequentially formed on the substrate 1 by chemical vapor deposition or the like. A hard mask covering the pre-semiconductor material layer is formed on the pre-semiconductor material layer, and the hard mask is etched by adopting photoetching and etching processes according to a preset scheme to form a hard mask pattern 8. Then, etching is performed on the substrate 1, the material layer to be oxidized and the pre-semiconductor material layer based on the hard mask pattern 8, so as to form a first fin portion. As shown in fig. 4, in a bottom-up direction, the first fin portion includes a second fin portion formed by etching a portion of the substrate 1, a layer to be oxidized 5 formed by etching a layer of material to be oxidized, and a layer of semiconductor material 6 formed by etching a layer of pre-semiconductor material.
For the layer 5 to be oxidized, a certain oxidation selectivity is required between the material contained in the layer 5 to be oxidized and the material contained in the semiconductor material layer 6. Specifically, the material contained in the layer to be oxidized 5 may be Si 1-y Ge y Wherein y is more than or equal to 0.2 and less than or equal to 0.8. Of course, the material contained in the layer to be oxidized 5 may be set according to the actual situation. The spacer layer 2 is formed correspondingly after the oxide layer 5 is formed, so the thickness of the oxide layer 5 can be set with reference to the thickness of the spacer layer 2. For the semiconductor material layer 6, the material contained in the semiconductor material layer 6 may be Si or Si 1-x Ge x Wherein x is more than 0 and less than or equal to 0.6. The layer thickness of the semiconductor material layer 6 determines the height of the channel region 33 to be formed later, so that the layer thickness of the semiconductor material layer 6 can be set according to the height of the channel region 33. The layer thickness of the semiconductor material layer 6 is, for example, 15nm to 70nm.
If the material contained in the semiconductor material layer 6 is Si 1-x Ge x In order to oxidize the layer 5 to be oxidized later, without having a large influence on the semiconductor material layer 6, it is required that the Ge content in the semiconductor material layer 6 is at least 20% lower than the Ge content in the layer to be oxidized.
In addition, as shown in fig. 3 and 5, when the semiconductor material layer 6 contains Si as a material 1-x Ge x In this case, after the material layer to be oxidized and the pre-semiconductor material layer covering the substrate 1 are sequentially formed on the substrate 1, a silicon material layer may be formed on the pre-semiconductor material layer before the hard mask is formed on the pre-semiconductor material layer. In the above case, the obtained first fin portion includes the second fin portion formed by etching part of the substrate 1, the layer to be oxidized 5 formed by etching the layer to be oxidized, the semiconductor material layer 6 formed by etching the pre-semiconductor material layer, and the silicon layer 7 formed by etching the silicon material layer, based on the hard mask pattern 8. The silicon layer 7 can protect the channel region 33 from the subsequent etching, cleaning and other processes, and avoid the channel region 33 from being damaged. Specifically, the thickness of the silicon layer 7 may be set according to the actual situation. The layer thickness of the silicon layer 7 is, for example, 2nm to 10nm.
Step S102.2: as shown in fig. 10 to 17, the layer to be oxidized 5 is oxidized to obtain the isolation layer 2.
In one example, the gas used in oxidizing the layer 5 to be oxidized may be O 2 And N 2 Or, can be a mixed gas containing O 3 Is a gas of (a) a gas of (b). In addition, the oxidation of the layer 5 to be oxidized may be performed by a furnace tube oxidation process or may be performed by a rapid thermal process.
When the furnace tube oxidation treatment mode is selected to oxidize the layer 5 to be oxidized, the treatment conditions of the furnace tube oxidation treatment mode are as follows: the treatment temperature is 500-850 ℃, and the treatment time is 10-60 min. Specifically, the processing temperature and the processing time can be set in combination with the actual application scenario.
When the rapid thermal processing method is selected to oxidize the layer 5 to be oxidized, the processing conditions of the rapid thermal processing method are as follows: the treatment temperature is 600-850 ℃, the treatment time is 30-60 s, and the treatment period is 1-10. Specifically, the processing temperature, processing time and processing period can be set in combination with the actual application scenario.
As shown in fig. 10 to 13, when the layer to be oxidized 5 is oxidized, the surfaces of the semiconductor material layer 6 and the substrate 1 (when the silicon layer 7 is formed, the surface of the silicon layer 7 is also included) are not oxidized or are partially oxidized. When the above structure is partially oxidized, it is necessary to remove the oxidized portions of the semiconductor material layer 6 and the substrate 1 (or the semiconductor material layer 6, the substrate 1 and the silicon layer 7) at the same time as removing the hard mask pattern 8 as shown in fig. 14 to 17 after forming the isolation layer 2.
It is noted that the isolation layer 2 is obtained by oxidizing a layer to be oxidized 5 formed on the substrate 1. That is, the isolation layer 2 is a film layer subsequently formed on the substrate 1, and does not constitute a part of the substrate 1. In this case, a semiconductor substrate such as a silicon substrate having a low cost can be used in the process of manufacturing the fin field effect transistor. And the isolation layer 2 is formed on the semiconductor substrate, so that the leakage problem of a parasitic channel and a source drain can be solved, and an SOI substrate containing a buried oxide layer is not required, thereby reducing the manufacturing cost of the fin field effect transistor.
Further, as shown in fig. 18 to 21, after the above operation is performed and before the lower operation is performed, it is also necessary to form shallow trench isolations 14 in the recesses between the first fins. The shallow trench isolation 14 may comprise a material as described above. The top height of the shallow trench isolation 14 may be less than or equal to the top height of the isolation layer 2. Of course, the height of the shallow trench isolation 14 may also be set according to the actual application scenario, which is not specifically limited herein.
In an alternative manner, as shown in fig. 22 to 25, after forming the isolation layer 2 on the substrate 1, before forming the fin structure 3 on the isolation layer 2, the method for manufacturing the fin field effect transistor further includes:
step S102-3: as shown in fig. 22 to 25, the sacrificial gate 9 is formed in a region of the semiconductor material layer 6 corresponding to the channel region 33, or in a region of the isolation layer 2 and the semiconductor material layer 6 corresponding to the channel region 33.
Specifically, when the top height of the shallow trench isolation 14 is equal to the top height of the isolation layer 2, the gate material of the sacrificial gate 9 needs to be formed on the semiconductor material layer 6. And the gate material is etched to form the sacrificial gate 9 only in the region of the semiconductor material layer 6 corresponding to the channel region 33. When the top height of the shallow trench isolation 14 is smaller than the top height of the isolation layer 2, it is necessary to form a gate material of the sacrificial gate 9 on the semiconductor material layer 6 and the exposed isolation layer 2. And the gate material is etched to form a sacrificial gate 9 in the isolation layer 2 and the semiconductor material layer 6 in the region corresponding to the channel region 33.
The gate material of the sacrificial gate 9 may be polysilicon, amorphous silicon, or the like. The sacrificial gate 9 extends in the second direction. For the specific direction of the second direction, reference may be made to the foregoing, and details are not described here.
When the silicon layer 7 is formed on the semiconductor material layer 6, as shown in fig. 23 and 25, the sacrificial gate 9 needs to be formed in a region corresponding to the channel region 33 of the silicon layer 7 and the semiconductor material layer 6 or in a region corresponding to the channel region 33 of the silicon layer 7, the semiconductor material layer 6 and the isolation layer 2.
Further, after the sacrificial gate 9 is formed, and before the subsequent operation is performed, the first side wall 10 and the second side wall 11 extending in the second direction may be formed. The sacrificial gate 9 is located between the first sidewall 10 and the second sidewall 11. As for the materials contained in the first sidewall 10 and the second sidewall 11 and the widths of the two, reference is made to the foregoing, and no description is given here.
Step S103: as shown in fig. 22 to 28, fin structures 3 are formed on the isolation layer 2. The fin structure 3 extends in a first direction. Fin structure 3 includes source region 31, drain region 32, and channel region 33. Channel region 33 is located between source region 31 and drain region 32. The channel region 33 is in contact with the source region 31 and the drain region 32, respectively. The area of the isolation layer 2 covering the substrate 1 is smaller than or equal to the area of the fin structure 3 covering the substrate 1. For the specific direction of the first direction, the area of the isolation layer 2 covering the substrate 1, and the like, reference is made to the foregoing, and details thereof will not be repeated here.
In an alternative manner, as shown in fig. 26 to 28, forming the fin structure 3 on the isolation layer 2 includes:
step S103.1: as shown in fig. 26 and 27, portions of the semiconductor material layer 6 located in the source region formation region 61 and the drain region formation region 62 are removed. Illustratively, the portions of the semiconductor material layer 6 located in the source region forming region 61 and the drain region forming region 62 may be etched by wet etching or dry etching, so as to facilitate the subsequent epitaxial formation of the source region 31 and the drain region 32.
When the silicon layer 7 is formed on the semiconductor material layer 6, as shown in fig. 25 and 27, portions of the silicon layer 7 and the semiconductor material layer 6 corresponding to the source region formation region 61 and the drain region formation region 62 need to be removed.
Step S103.2: as shown in fig. 28 and 29, the source region 31 and the drain region 32 are formed in the source region formation region 61 and the drain region formation region 62, respectively, and the channel region 33 is in contact with the source region 31 and the drain region 32, respectively.
For example, as shown in fig. 28 and 29, the source region 31 may be epitaxially formed in the source region forming region 61 and the drain region 32 may be formed in the drain region forming region 62. The channel region 33 is in contact with the source region 31 and the drain region 32, respectively. For details, the source region 31 and the drain region 32 may be made of the materials described above, and will not be described here.
Note that, as shown in fig. 30 and 31, after the source region 31 and the drain region 32 are formed, and before the sacrificial gate 9 is removed, a dielectric material may be deposited on the formed structure. And planarizes the dielectric material until the top of the sacrificial gate 9 is exposed. At this time, the remaining dielectric material on the source region 31 correspondingly forms the first dielectric layer 12. The remaining dielectric material on the drain region 32 correspondingly forms the second dielectric layer 13.
Step S104: as shown in fig. 32 to 34, the gate stack structure 4 is formed at the outer periphery of the channel region 33. The gate stack 4 extends in the second direction. Illustratively, after the first dielectric layer 12 and the second dielectric layer 13 described above are formed, the sacrificial gate 9 is removed. Thereafter, the gate dielectric layer 41 and the gate electrode 42 may be sequentially formed on the outer periphery of the channel region 33 by atomic layer deposition (Atomic layer deposition, abbreviated as ALD) or the like. Reference is made to the foregoing for the materials contained in gate dielectric layer 41 and gate electrode 42.
It should be noted that, as described above, if the silicon layer 7 is formed on the semiconductor material layer 6, after the sacrificial gate 9 is removed and before the gate stack structure 4 is formed, the remaining silicon layer 7 on the channel region 33 should be removed.
The embodiment of the invention also provides electronic equipment, which comprises the fin field effect transistor provided by the embodiment. The electronic device may be a terminal device or a communication device, but is not limited thereto. Further, the terminal device includes a mobile phone, a smart phone, a tablet computer, a computer, an artificial intelligent device, a mobile power supply, and the like. The communication device includes a base station and the like, but is not limited thereto.
The beneficial effects of the electronic device provided by the embodiment of the present invention are the same as those of the fin field effect transistor provided by the above embodiment, and are not described here in detail.
In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.
The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.
Claims (13)
1. A fin field effect transistor, comprising:
the substrate is provided with a plurality of holes,
an isolation layer formed on the substrate; the isolation layer is formed by adopting selective oxidation treatment, and the object of the selective oxidation treatment is a layer to be oxidized; the material contained in the layer to be oxidized is Si 1-y Ge y Wherein y is more than or equal to 0.2 and less than or equal to 0.8;
a fin structure formed on the isolation layer, the fin structure extending in a first direction, the fin structure including a source region, a drain region, and a channel region, the channel region being located between the source region and the drain region, the channel region being in contact with the source region and the drain region, respectively, the area of the isolation layer covering the substrate being less than or equal to the area of the fin structure covering the substrate; the channel region contains Si or Si as material 1-x Ge x Wherein x is more than 0 and less than or equal to 0.6; when the material of the channel region is Si 1-x Ge x When the content of Ge in the channel region is at least 20% lower than the content of Ge in the layer to be oxidized;
and a gate stack structure formed at an outer circumference of the channel region, the gate stack structure extending in the second direction.
2. The fin field effect transistor of claim 1, wherein the substrate is a silicon substrate, a silicon germanium substrate.
3. The finfet of claim 1, wherein a portion of the spacer under the source region is flush with a top of a portion of the spacer under the drain region.
4. The fin field effect transistor of any one of claims 1-3, wherein the isolation layer comprises a material selected from the group consisting of silicon oxide, silicon germanium oxide; and/or the number of the groups of groups,
the thickness of the isolation layer is 5 nm-50 nm.
5. The fin field effect transistor of claim 1, wherein the channel region comprises a material that is Si or Si 1-x Ge x Wherein x is more than 0 and less than or equal to 0.6.
6. A method for fabricating a fin field effect transistor, comprising:
providing a substrate;
forming an isolation layer on the substrate;
forming a fin structure on the isolation layer, wherein the fin structure extends along a first direction and comprises a source region, a drain region and a channel region, the channel region is positioned between the source region and the drain region, the channel region is respectively contacted with the source region and the drain region, and the area of the isolation layer covering the substrate is smaller than or equal to the area of the fin structure covering the substrate;
forming a gate stack structure located at the periphery of the channel region, the gate stack structure extending in a second direction; wherein,
the forming an isolation layer on the substrate includes:
forming a layer to be oxidized and a semiconductor material layer positioned on the layer to be oxidized on the substrate, wherein the semiconductor material layer comprises a source region forming region, a drain region forming region and a channel region, and the channel region is positioned between the source region forming region and the drain region forming region; by a means ofThe material contained in the layer to be oxidized is Si 1-y Ge y Wherein y is more than or equal to 0.2 and less than or equal to 0.8; the semiconductor material layer contains Si or Si 1-x Ge x Wherein x is more than 0 and less than or equal to 0.6; when the material of the semiconductor material layer is Si 1-x Ge x The Ge content in the semiconductor material layer is at least 20% lower than the Ge content in the layer to be oxidized
Selectively oxidizing the layer to be oxidized to obtain the isolation layer.
7. The method of claim 6, wherein when the semiconductor material layer contains Si 1-x Ge x After the step of providing the substrate and before the step of oxidizing the layer to be oxidized, the manufacturing method of the fin field effect transistor further comprises the following steps:
a silicon layer is formed on the semiconductor material layer.
8. The method of claim 6, wherein the gas used to oxidize the layer to be oxidized is O 2 And N 2 Or, O 3 And (3) gas.
9. The method of manufacturing a fin field effect transistor according to claim 6, wherein the method of oxidizing the layer to be oxidized is a furnace tube oxidation method or a rapid thermal processing method;
the treatment conditions of the furnace tube oxidation treatment mode are as follows: the treatment temperature is 500-850 ℃ and the treatment time is 10-60 min;
the treatment conditions of the rapid thermal treatment mode are as follows: the treatment temperature is 600-850 ℃, the treatment time is 30-60 s, and the treatment period is 1-10.
10. The method for fabricating a finfet according to any one of claims 6-9, wherein after forming an isolation layer on the substrate, before forming a fin structure on the isolation layer, the method for fabricating a finfet further comprises:
and forming a sacrificial gate in a region of the semiconductor material layer corresponding to the channel region, or in a region of the isolation layer and the semiconductor material layer corresponding to the channel region.
11. The method of claim 10, wherein forming a fin structure on the spacer layer comprises:
removing portions of the semiconductor material layer located in the source region forming region and the drain region forming region;
and forming a source region and a drain region in the source region forming region and the drain region forming region respectively, wherein the channel region is respectively contacted with the source region and the drain region.
12. An electronic device comprising a fin field effect transistor according to any one of claims 1 to 5.
13. The electronic device of claim 12, wherein the electronic device comprises a communication device or a terminal device.
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