CN113013164B - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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CN113013164B
CN113013164B CN202110174750.0A CN202110174750A CN113013164B CN 113013164 B CN113013164 B CN 113013164B CN 202110174750 A CN202110174750 A CN 202110174750A CN 113013164 B CN113013164 B CN 113013164B
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transistor
region
material portion
channel
forming
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CN113013164A (en
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李永亮
赵飞
程晓红
王文武
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

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Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductors, and aims to simplify the manufacturing process of the semiconductor device and improve the yield and the performance of the semiconductor device under the condition of ensuring that a first transistor and a second transistor have different threshold voltages. The semiconductor device includes: the transistor includes a substrate, a first transistor, and a second transistor. The substrate includes a first well region and a second well region. The first transistor is formed on the first well region. The first transistor includes a channel region having a first material portion. The second transistor is formed on the second well region. The second transistor and the first transistor are of different conductivity types. The second transistor includes a channel region having a first material portion and a second material portion formed on an outer periphery of the first material portion. The material of the second material portion is different from the material of the first material portion. The second transistor and the first transistor are both fin field effect transistors. The manufacturing method of the semiconductor device is used for manufacturing the semiconductor device.

Description

Semiconductor device and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.
Background
In an actual manufacturing process of a Semiconductor device, gate stack structures with different thicknesses or different materials are usually formed on the peripheries of channel regions included in an NMOS (N-Metal-Oxide-Semiconductor) device and a PMOS (P-Metal-Oxide-Semiconductor) device, so that the NMOS device and the PMOS device have different threshold voltages.
However, the manufacturing process of the semiconductor device is complicated by the method of forming gate stack structures of different thicknesses or different materials at the peripheries of the channel regions included in the NMOS device and the PMOS device to make the NMOS device and the PMOS device have different threshold voltages.
Disclosure of Invention
The invention aims to provide a semiconductor device and a manufacturing method thereof, which are used for simplifying the manufacturing process of the semiconductor device and improving the yield and the performance of the semiconductor device under the condition of ensuring that the threshold voltages of a first transistor and a second transistor are different.
In order to achieve the above object, the present invention provides a semiconductor device comprising:
a substrate; the substrate comprises a first well region and a second well region;
a first transistor formed on the first well region; the first transistor includes a channel region having a first material portion;
a second transistor formed on the second well region; the second transistor and the first transistor are different in conductivity type; the second transistor includes a channel region having a first material portion and a second material portion formed on an outer periphery of the first material portion; the material of the second material part is different from that of the first material part; the second transistor and the first transistor are both fin field effect transistors; the second transistor has a thickness and a width of the first material portion that are less than a thickness and a width of the first material portion, respectively, of the first transistor.
Compared with the prior art, the semiconductor device provided by the invention has the advantages that the conductivity types of the first transistor formed on the first well region and the second transistor formed on the second well region are different. The first transistor includes a channel region having a first material portion. The second transistor includes a channel region having a first material portion and a second material portion formed on an outer periphery of the first material portion. Meanwhile, the material of the second material part is different from that of the first material part. That is, the material of the channel region included in the first transistor is not completely the same as the material of the channel region included in the second transistor. The channel regions made of different materials have different carrier mobility and conductivity, so that under the condition that the materials of the channel region included by the first transistor and the channel region included by the second transistor are not completely the same, the first transistor and the second transistor are favorable for obtaining different threshold voltages. Therefore, in the process of manufacturing the semiconductor device provided by the invention, after the corresponding first material parts are formed on the first well region and the second well region, the first transistor and the second transistor can have different threshold voltages only by forming the second material part on the periphery of the first material part of the second well region, and gate stack structures with different thicknesses or materials are not required to be formed on the peripheries of channel regions included in different transistors in a multiple deposition-etching-deposition mode, so that the manufacturing process of the semiconductor device can be simplified, and the yield and the performance of the semiconductor device are improved.
The present invention also provides a method of manufacturing a semiconductor device, the method of manufacturing the semiconductor device including:
providing a substrate, wherein the substrate comprises a first well region and a second well region;
forming a first transistor on the first well region and a second transistor on the second well region; the first transistor includes a channel region having a first material portion; the second transistor and the first transistor are different in conductivity type; the second transistor includes a channel region having a first material portion and a second material portion formed on an outer periphery of the first material portion; the material of the second material part is different from that of the first material part; the second transistor and the first transistor are both fin field effect transistors; wherein the content of the first and second substances,
forming a first transistor over the first well region and a second transistor over the second well region, comprising:
forming a channel region included in the first transistor over the first well region, and forming a channel formation region over the second well region; the channel region and the channel forming region each have a first material portion formed on the substrate;
thinning the channel forming region under the mask action of the mask layer, so that the thickness and the width of a first material part of the channel forming region are respectively smaller than those of the first material part of the channel region; the mask layer covers the first well region and a channel region included by the first transistor;
and forming a second material portion on the outer periphery of the thinned channel formation region to obtain a channel region included in the second transistor.
Compared with the prior art, the manufacturing method of the semiconductor device provided by the invention has the same beneficial effects as those of the semiconductor device provided by the technical scheme, and the details are not repeated here.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic structural diagram of a first semiconductor film formed on a substrate according to an embodiment of the present invention;
figure 2base:Sub>A isbase:Sub>A cross-sectional view ofbase:Sub>A first fin structure andbase:Sub>A second fin structure formed in accordance with an embodiment of the present invention alongbase:Sub>A directionbase:Sub>A-base:Sub>A;
figure 2B is a cross-sectional view of a structure taken along direction B-B after forming the first and second fin structures in accordance with an embodiment of the present invention;
figure 3base:Sub>A isbase:Sub>A cross-sectional view of another structure alongbase:Sub>A-base:Sub>A after formingbase:Sub>A first fin structure andbase:Sub>A second fin structure in an embodiment of the present invention;
figure 3B is a cross-sectional view of another structure taken along direction B-B after forming the first and second fin structures in accordance with an embodiment of the present invention;
FIG. 4base:Sub>A isbase:Sub>A cross-sectional view ofbase:Sub>A structure taken along line A-A after shallow trench isolation is formed in an embodiment of the present invention;
FIG. 4B is a cross-sectional view of a structure along the direction B-B after forming shallow trench isolation in an embodiment of the present invention;
FIG. 5base:Sub>A isbase:Sub>A cross-sectional view of an alternative structure taken along the direction A-A after shallow trench isolation is formed in an embodiment of the present invention;
FIG. 5B is a cross-sectional view of another structure taken along line B-B after shallow trench isolation is formed in an embodiment of the present invention;
FIG. 6base:Sub>A isbase:Sub>A cross-sectional view ofbase:Sub>A structure along the A-A direction after formingbase:Sub>A sacrificial gate,base:Sub>A first sidewall andbase:Sub>A second sidewall in an embodiment of the present invention;
fig. 6B is a structural cross-sectional view along the direction B-B after the sacrificial gate, the first sidewall, and the second sidewall are formed in the embodiment of the present invention;
FIG. 7base:Sub>A isbase:Sub>A cross-sectional view of another structure along the A-A direction after formingbase:Sub>A sacrificial gate,base:Sub>A first sidewall andbase:Sub>A second sidewall in an embodiment of the present invention;
FIG. 7B is a cross-sectional view of another structure along the direction B-B after forming the sacrificial gate, the first sidewall and the second sidewall in the embodiment of the present invention;
FIG. 8 is a cross-sectional view of a structure taken along direction B-B after forming source and drain regions in accordance with an embodiment of the present invention;
FIG. 9 is a cross-sectional view of another structure taken along the direction B-B after forming source and drain regions in accordance with an embodiment of the present invention;
FIG. 10 is a cross-sectional view of a structure along the direction B-B after forming a first dielectric layer and a second dielectric layer in accordance with an embodiment of the present invention;
FIG. 11 is a cross-sectional view of another structure taken along the direction B-B after forming a first dielectric layer and a second dielectric layer in accordance with an embodiment of the present invention;
fig. 12 isbase:Sub>A cross-sectional view ofbase:Sub>A structure taken along the directionbase:Sub>A-base:Sub>A after formingbase:Sub>A channel region andbase:Sub>A channel formation region in the embodiment of the present invention;
FIG. 13 isbase:Sub>A sectional view of another structure in the direction A-A after formingbase:Sub>A channel region andbase:Sub>A channel formation region in the embodiment of the present invention;
fig. 14 isbase:Sub>A sectional view ofbase:Sub>A structure taken along the directionbase:Sub>A-base:Sub>A after thinning-processingbase:Sub>A channel formation region in the embodiment of the present invention;
FIG. 15 isbase:Sub>A sectional view of another structure taken along the direction A-A after thinningbase:Sub>A channel formation region in the embodiment of the present invention;
FIG. 16 isbase:Sub>A cross-sectional view ofbase:Sub>A structure taken along line A-A after formingbase:Sub>A second material portion in accordance with an embodiment of the present invention;
FIG. 17 isbase:Sub>A cross-sectional view of an alternative construction taken along the direction A-A after formingbase:Sub>A second material portion in accordance with an embodiment of the present invention;
FIG. 18 isbase:Sub>A cross-sectional view ofbase:Sub>A structure taken along the direction A-A afterbase:Sub>A gate stack structure is formed in accordance with an embodiment of the present invention;
fig. 19 isbase:Sub>A cross-sectional view of another structure taken along the directionbase:Sub>A-base:Sub>A afterbase:Sub>A gate stack structure is formed in an embodiment of the invention.
Reference numerals: 11 is a substrate, 111 is a first well region, 112 is a second well region, 12 is a first semiconductor film, 13 is a first fin structure, 131 is a first fin portion, 1311 is a source region formation region, 1312 is a drain region formation region, 1313 is a gate formation region, 1314 is a first semiconductor layer, 1315 is a second semiconductor layer, 14 is a second fin structure, 141 is a second fin portion, 15 is a shallow trench isolation, 16 is a sacrificial gate, 17 is a first sidewall, 18 is a second sidewall, 19 is a source region, 20 is a drain region, 21 is a first dielectric layer, 22 is a second dielectric layer, 23 is a channel region, 24 is a channel formation region, 25 is a mask layer, 26 is a first material portion, 27 is a second material portion, 28 is a third material portion, 29 is a gate stack structure, 291 is a gate dielectric layer, 292 is a gate electrode, 30 is a first transistor, and 31 is a second transistor.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed. In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise. The meaning of "a number" is one or more unless specifically limited otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood according to specific situations by those of ordinary skill in the art.
In an actual manufacturing process of a Semiconductor device, gate stack structures with different thicknesses or different materials are usually formed on the peripheries of channel regions included in an NMOS (N-Metal-Oxide-Semiconductor) device and a PMOS (P-Metal-Oxide-Semiconductor) device, so that the NMOS device and the PMOS device have different threshold voltages.
In the case where the NMOS device and the PMOS device are both fin field effect transistors, the NMOS device and the PMOS device having different threshold voltages are manufactured as follows: at least one fin structure extending along a first direction is first formed on the N-well region and the P-well region, respectively. Shallow trench isolation is then formed between adjacent fin structures. And forming a fin part on the part of each fin structure exposed outside the shallow trench isolation. And then, forming a sacrificial gate extending along the second direction and forming a source region and a drain region which are positioned at two sides of the sacrificial gate along the width direction of the sacrificial gate on the periphery of the at least two fin parts. Wherein the second direction is different from the first direction. The part of the fin part between the source region and the drain region is a channel region. The sacrificial gate is then removed to expose the channel region. And forming a gate stack structure corresponding to the NMOS device (or the PMOS device) at the periphery of the channel region included by the NMOS device and the PMOS device. And under the mask action of the mask layer covering the NMOS device (or the PMOS device), removing the gate stack structure corresponding to the NMOS device (or the PMOS device) formed on the periphery of the channel region included in the PMOS device (or the NMOS device). And finally, forming a gate stack structure corresponding to the PMOS device on the periphery of a channel region included by the PMOS device, thereby obtaining the NMOS device and the PMOS device with different threshold voltages in a mode of 'deposition-etching-deposition' for multiple times.
As can be seen from the above, the manufacturing process of the semiconductor device is complicated by forming the gate stack structures with different thicknesses or different materials on the peripheries of the channel regions included in the NMOS device and the PMOS device to make the NMOS device and the PMOS device have different threshold voltages. Also, with the development of semiconductor technology, an integrated circuit having higher performance and higher functionality requires greater element density, and the size, and space of each component, between elements, or each element itself also needs to be further reduced. The difficulty of forming gate stack structures of different thicknesses or different materials in a smaller space is large, which results in the reduction of yield and performance of semiconductor devices.
In addition, in general, for the PMOS device, when the channel region in the PMOS device is made of high mobility materials such as silicon germanium or germanium, the carrier mobility of the channel region included in the PMOS device can be increased, and the performance of the PMOS device is improved. For NMOS devices, the channel region included in the NMOS device is typically formed using strained silicon, lower germanium content silicon germanium, or iii-v materials. That is, in order to obtain a CMOS device having a high operation performance, it is necessary that channel regions included in a PMOS device and an NMOS device in the CMOS device have different materials. In the STI last scheme in the prior art, a layer of high-mobility material covering the surface of the substrate extends on the surface of the substrate, and a channel region suitable for one device (such as a PMOS device) is manufactured and formed on the basis of the same high-mobility material, so that a channel region suitable for another device (such as an NMOS device) cannot be obtained, and the STI last scheme is not suitable for the integration of the CMOS device. For the existing STI first scheme, although the PMOS device and the NMOS device with different channel materials can be obtained by using the STI first scheme, the process of manufacturing the CMOS device by using the STI first scheme is complicated and is difficult to control, so that the performance of the semiconductor device is poor.
In order to solve the above technical problem, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same. In the semiconductor device provided by the embodiment of the invention, the channel region included in the first transistor has the first material portion. The second transistor includes a channel region having a first material portion and a second material portion formed on an outer periphery of the first material portion. Meanwhile, the material of the second material part is different from that of the first material part. Therefore, in the process of manufacturing the semiconductor device provided by the embodiment of the invention, after the corresponding first material portions are formed on the first well region and the second well region, the threshold voltages of the first transistor and the second transistor can be different by only forming the second material portion on the periphery of the first material portion of the second well region, so that the manufacturing process of the semiconductor device can be simplified, and the yield and the performance of the semiconductor device can be improved.
The embodiment of the invention provides a semiconductor device. As shown in fig. 18 and 19, the semiconductor device includes: a substrate 11, a first transistor 30 and a second transistor 31.
As shown in fig. 18 and 19, the substrate 11 includes a first well region 111 and a second well region 112.
Specifically, the substrate may be a semiconductor substrate such as a silicon substrate or a silicon-on-insulator substrate. The first well region may be an N-well region or a P-well region. For the second well region, when the first well region is an N-well region, the second well region is a P-well region. When the first well region is a P well region, the second well region is an N well region. In some cases, a shallow trench isolation is formed on the substrate to define an active region. As for the material contained in the shallow trench isolation, siN and Si can be used 3 N 4 、SiO 2 Or an insulating material such as SiCO.
As shown in fig. 18 and 19, the first transistor 30 is formed over the first well region 111. The first transistor 30 comprises a channel region 23 having a first material portion 26.
Specifically, when the first well region is an N-well region, the first transistor is a PMOS transistor. When the first well region is a P well region, the first transistor is an NMOS transistor. The first transistor has a first material portion made of a semiconductor material. The semiconductor material includes silicon, silicon germanium, and the like. The content of germanium in the silicon germanium (the content of germanium appearing here and below is the concentration of germanium) may be set according to the actual application scenario, and is not specifically limited here.
As shown in fig. 18 and 19, the second transistor 31 is formed over the second well region 112. The second transistor 31 and the first transistor 30 are of different conductivity types. The channel region 23 included in the second transistor 31 has a first material portion 26 and a second material portion 27 formed on the outer periphery of the first material portion 26. The material of the second material portion 27 is different from the material of the first material portion 26. The second transistor 31 and the first transistor 30 are both fin field effect transistors.
Specifically, since the conductivity types of the second transistor and the first transistor are different, when the second transistor is a PMOS transistor and the second well region is an N-well region, the first well region is a P-well region and the first transistor is an NMOS transistor. When the second transistor is an NMOS transistor and the second well region is a P well region, the first well region is an N well region and the first transistor is a PMOS transistor.
The second material portion of the second transistor is made of a semiconductor material different from that of the first material portion. The semiconductor material includes silicon, silicon germanium, and the like. When the first material portion and the second material portion are both made of germanium, the content of germanium in the first material portion and the second material portion are different from each other. Specifically, the difference between the germanium contents in the first material portion and the second material portion may be set according to the requirement of the practical application scenario on the threshold voltages of the first transistor and the second transistor, and is not specifically limited herein. Wherein the larger the difference in germanium content between the first material portion and the second material portion, the larger the difference in threshold voltage between the first transistor and the second transistor.
For example: when the second material portion is made of silicon, the first material portion may be made of silicon germanium or germanium. In this case, the preferred second transistor is an NMOS transistor. The first transistor is a PMOS transistor.
Another example is: when the material of the second material portion is silicon germanium, the material of the first material portion may be silicon, silicon germanium or germanium. Wherein, when the material of the second material portion is silicon germanium (Si) 1-x Ge x ) And the first material portion is made of silicon germanium (Si) 1-y Ge y ) When 0 < x < 1,0 < y < 1, and x ≠ y. In this case, when the material of the second material portion is silicon germanium and the material of the first material portion is silicon, the second transistor is preferably a PMOS transistor. The first transistor is an NMOS transistor. In the case where the content of germanium in the first material portion is larger than the content of germanium in the second material portion, it is preferable that the first transistor is a PMOS transistor and the second transistor is an NMOS transistor.
For another example: when the second material portion is made of germanium, the first material portion may be made of silicon or silicon germanium. In this case, when the material of the second material portion is germanium and the material of the first material portion is silicon, the second transistor is preferably a PMOS transistor. The first transistor is an NMOS transistor. When the material of the second material portion is germanium and the material of the first material portion is germanium-silicon, the second transistor is preferably a PMOS transistor. The first transistor is an NMOS transistor.
It is worth noting that when the channel region of the PMOS transistor is made of the sige or ge high mobility material, the carrier mobility of the channel region can be improved, thereby improving the performance of the PMOS transistor. However, when a channel region in an NMOS transistor is fabricated using a silicon germanium or germanium high mobility material, there are problems of poor interface state, high source-drain contact resistance, low solid concentration of N-type impurities, and rapid diffusion. Based on this, in the case where the content of germanium in the first material portion is larger than the content of germanium in the second material portion, the first transistor is a PMOS transistor, and the second transistor is an NMOS transistor. Or, in the case where the content of germanium in the first material portion is smaller than the content of germanium in the second material portion, the first transistor is an NMOS transistor, and the second transistor is a PMOS transistor, so that the performance of the semiconductor device can be improved.
In some cases, as shown in fig. 10 and 11, and fig. 18 and 19, the first transistor 30 and the second transistor 31 further include: source region 19, drain region 20, and gate stack structure 29. The channel region 23 is located between the source region 19 and the drain region 20, and the channel region 23 is in contact with the source region 19 and the drain region 20, respectively. A gate stack structure 29 is formed at the outer periphery of the channel region 23.
Specifically, the source region and the drain region are made of a semiconductor material (e.g., silicon germanium, etc.). The source region and the drain region may be made of the same material or different materials. Specifically, the material of the source region and the drain region may be set according to an application scenario, and is not specifically limited herein.
As for the above-described gate stack structure, as shown in fig. 18 to 19, the gate stack structure 29 may include a gate dielectric layer 291 formed at the outer periphery of the channel region 23, and a gate electrode 292 formed on the gate dielectric layer 291. The gate dielectric layer 291 may be made of HfO 2 、ZrO 2 、TiO 2 Or Al 2 O 3 And materials with higher dielectric constants. The gate electrode 292 may be made of a conductive material such as TiN, taN, or TiSiN.
As can be seen from the above, in the semiconductor device provided in the embodiments of the present invention, the conductivity types of the first transistor formed on the first well region and the second transistor formed on the second well region are different. The first transistor includes a channel region having a first material portion. The second transistor includes a channel region having a first material portion and a second material portion formed at an outer periphery of the first material portion. Meanwhile, the material of the second material part is different from that of the first material part. That is, the material of the channel region included in the first transistor is not completely the same as the material of the channel region included in the second transistor. The channel regions made of different materials have different carrier mobility and conductivity, so that under the condition that the materials of the channel region included by the first transistor and the channel region included by the second transistor are not completely the same, the first transistor and the second transistor are favorable for obtaining different threshold voltages. Therefore, in the process of manufacturing the semiconductor device provided by the embodiment of the invention, after the corresponding first material portions are formed on the first well region and the second well region, the first transistor and the second transistor can have different threshold voltages only by forming the second material portion on the periphery of the first material portion of the second well region, and a gate stack structure with different thicknesses or materials does not need to be formed on the periphery of the channel regions included in the different transistors in a multiple deposition-etching-deposition manner, so that the manufacturing process of the semiconductor device can be simplified, and the yield and the performance of the semiconductor device can be improved.
In one example, as shown in fig. 18, the above-described first material portion 26 is formed on the surface of the substrate 11. Alternatively, as shown in fig. 19, the channel region 23 included in the first transistor 30 and the second transistor 31 further has the third material portion 28. A third material portion 28 is formed between the substrate 11 and the first material portion 26. The second material portion 27 is formed on the outer periphery of the first material portion 26 and the third material portion 28.
Specifically, in the process of manufacturing the semiconductor device according to the embodiment of the present invention, as shown in fig. 2a, fig. 2b and fig. 18, on the premise that the first fin structure 13 located on the first well region 111 and the second fin structure 14 located on the second well region 112 are manufactured by directly etching the substrate 11, the channel region 23 formed by performing corresponding operations on the exposed portions of the first fin structure 13 and the second fin structure 14 outside the shallow trench isolation 15 only has the first material portion 26. The first material portion 26 is a portion of the substrate 11 exposed outside the shallow trench isolation 15 after being etched and located in the gate formation region 1313.
Or, on the premise that the first fin-shaped structure located on the first well region and the second fin-shaped structure located on the second well region are manufactured by etching the first semiconductor film and the top of the substrate, when the top of the shallow trench isolation is flush with or slightly higher than the top of the substrate after etching, the subsequently formed channel region also only has the first material portion. The first material portion is a portion of the first semiconductor film exposed outside the shallow trench isolation and located in the gate formation region after being etched. As shown in fig. 5a, 5b and 19, when the top of the shallow trench isolation 15 is lower than the top of the substrate 11 after etching, the subsequently formed channel region 25 has not only the first material portion 26 but also the third material portion 28. The third material portion 28 is a portion of the substrate 11 exposed outside the shallow trench isolation 15 after being etched and located in the gate forming region 1313.
For example, in the case where the first transistor or the second transistor further includes a third material portion, a material of the third material portion is a semiconductor material. The semiconductor material may be one of silicon, silicon germanium, and germanium. The first material portion and the third material portion may be made of the same material or different materials. In addition, the doping conditions of the impurities in the first material portion and the third material portion may be the same or different.
Specifically, when the first material portion and the third material portion are made of the same material, the first material portion and the third material portion may be made of silicon, silicon germanium, or the like. In the case where the first material portion and the third material portion are made of different materials, when the first material portion is silicon, the third material portion may be silicon germanium or germanium. Alternatively, when the first material portion is silicon germanium, the third material portion may be silicon, silicon germanium, or germanium. Wherein, when the material of the first material portion is germanium-silicon (Si) 1-y Ge y ) And the second material portion is made of silicon germanium (Si) 1-z Ge z ) When 0 < y < 1,0 < z < 1, and y ≠ z. Alternatively, when the first material portion is germanium, the third material portion may be silicon or silicon germanium. Specifically, the difference between the germanium contents in the first material portion and the third material portion may be set according to a practical application scenario, and is not specifically limited herein.
In one example, as shown in fig. 18 and 19, the thickness and the width of the channel region 23 included in the first transistor 30 described above are equal to the thickness and the width of the channel region 23 included in the second transistor 31, respectively. It is to be understood that the gate stack structure 29 included in the first transistor 30 and the second transistor 31 is formed at the outer periphery of the channel region 23. And, the largest area where the gate stack structure 29 is formed is the area released after removing the sacrificial gate 16. When the thickness and the width of the channel region 23 included in the second transistor 31 are equal to the thickness and the width of the channel region 23 included in the first transistor 30, respectively, it is explained that the second material portion 27 formed at the outer periphery of the first material portion 26 does not occupy the above-described region. At this time, the gate stack structure 29 included in the second transistor 31 has a larger formation area, which facilitates formation of the gate stack structure 29 included in the second transistor 31. In practical applications, the thickness and the width of the first material portion 26 of the second transistor 31 may be smaller than the thickness and the width of the first material portion 26 of the first transistor 30, respectively, so that the thickness and the width of the channel region 23 included in the first transistor 30 are equal to the thickness and the width of the channel region 23 included in the second transistor 31, respectively.
Of course, the thickness and the width of the first material portion of the second transistor may be equal to the thickness and the width of the first material portion of the first transistor, respectively. At this time, the thickness and width of the channel region included in the first transistor are smaller than those of the channel region included in the second transistor, respectively.
In one example, in the case where the first material portion contains germanium, the first transistor may further include a first passivation layer formed at an outer periphery of the channel region. It is to be understood that in case the first material portion contains germanium, if the gate dielectric layer formed at the periphery of the channel region comprised by the first transistor is HfO 2 When the high-k dielectric layer is high, a severe interface state is generated between the high-k dielectric layer and the germanium interface, and the electron mobility of germanium is further influenced. And forming a first passivation layer on the periphery of the channel region of the first transistor to isolate the high-k dielectric layer from the first material portion, thereby improving the interface state of the first material portion and improving the quality of the semiconductor device. The material of the first passivation layer may be silicon oxide, silicon, or the like. The thickness of the first passivation layer may be set according to an actual application scenario, and is not particularly limited herein. For example: when the material of the first passivation layer is silicon, the thickness of the first passivation layer may be 1nm.
In one example, in the case where the second material portion contains germanium, the second transistor may further include a second passivation layer formed on an outer periphery of the channel region. In particular, in a similar manner, the high-k dielectric layer and the second material portion can be isolated by the second passivation layer, so that the interface state of the second material portion is improved, and the quality of the semiconductor device is improved. The material and thickness of the second passivation layer may refer to the material and thickness of the first passivation layer, which are not described herein again.
In one example, as shown in fig. 10 and 11, the first transistor 30 and the second transistor 31 may further include: a first dielectric layer 21 and a second dielectric layer 22. A first dielectric layer 21 is formed on the surface of the source region 19 facing away from the substrate 11. A second dielectric layer 22 is formed on the surface of drain region 20 facing away from substrate 11. It will be appreciated that the presence of the first and second dielectric layers 21, 22 described above may ensure that a planarization process is employed to obtain the exposure of the sacrificial gate 16 and to protect the source and drain regions 19, 20, respectively, from the sacrificial gate 16 removal, cleaning, etc. In addition, the first dielectric layer 21 and the second dielectric layer 22 included in the second transistor 31 can protect the source region 19 and the drain region 20 from the thinning process when the thinning process is performed on the channel formation region 24, and the yield of the semiconductor device can be improved.
Specifically, the first dielectric layer and the second dielectric layer may be made of an insulating material such as silicon oxide. The thicknesses of the first dielectric layer and the second dielectric layer may be set according to practical application scenarios, and are not specifically limited herein.
The embodiment of the invention also provides a manufacturing method of the semiconductor device. The manufacturing process will be described below with reference to the perspective or cross-sectional views of the operation shown in fig. 1 to 19. Specifically, the manufacturing method of the semiconductor device includes:
first, a substrate is provided. The substrate includes a first well region and a second well region. The specific structure of the substrate and the types of the first well region and the second well region may refer to the foregoing, and are not described herein again.
As shown in fig. 18 and 19, the first transistor 30 is formed over the first well region 111, and the second transistor 31 is formed over the second well region 112. The first transistor 30 comprises a channel region 23 having a first material portion 26. The second transistor 31 and the first transistor 30 are of different conductivity types. The channel region 23 included in the second transistor 31 has a first material portion 26 and a second material portion 27 formed on the outer periphery of the first material portion 26. The material of the second material portion 27 is different from the material of the first material portion 26. The second transistor 31 and the first transistor 30 are both fin field effect transistors.
For details, the conductive types of the first transistor and the second transistor, and the materials of the first material portion and the second material portion may refer to the foregoing, and are not described herein again.
In one example, the forming the first transistor on the first well region and the forming the second transistor on the second well region may include:
as shown in fig. 2a to 5b, the first and second fins 131 and 141 extending in the first direction may be formed on the substrate 11. The first fin portion 131 is located on the first well region 111. The second fin portion 141 is located on the second well region 112. Each of the first and second fins 131 and 141 includes a source region formation region 1311, a drain region formation region 1312, and a gate formation region 1313 between the source region formation region 1311 and the drain region formation region 1312. It should be noted that fig. 2B and 3B are two structural cross-sectional views along the direction B-B and at the first fin structure 13 after the first fin structure 13 and the second fin structure 14 are formed. At this time, the two cross-sectional views of the structure along the direction B-B and at the second fin structure 14 are the same as those of the two figures. In addition, fig. 4B and 5B are cross-sectional views of the two structures along the direction B-B and at the first fin portion 131 after the first fin portion 131 and the second fin portion 141 are formed. At this time, the cross-sectional views of the two structures along the direction B-B and at the second fin portion 141 are respectively the same as those of the two figures.
Specifically, the first direction may be any direction parallel to the surface of the substrate. The specific structures and materials of the first fin portion and the second fin portion can be set according to practical application scenes. Illustratively, the first fin portion and the second fin portion are first semiconductor layers formed on the surface of the substrate. Or the first fin part and the second fin part comprise a first semiconductor layer and a second semiconductor layer which are stacked on the substrate along the thickness direction of the substrate. The first semiconductor layer is located on the second semiconductor layer. The first material portion is formed on a portion of the first semiconductor layer located in the gate formation region, and the material and the layer thickness of the first semiconductor layer may be set according to the material and the layer thickness of the first material portion. The second semiconductor layer is formed on the gate electrode forming region, and the second material portion is formed on the second semiconductor layer.
Furthermore, as described above, in the case where the shallow trench isolation for defining the active region is also formed on the substrate, the shallow trench isolation is formed on a portion of the substrate between the first fin portion and the second fin portion. And the first fin portion and the second fin portion are exposed outside the shallow trench isolation.
In practical applications, as shown in fig. 1, a first semiconductor film 12 may be first epitaxially grown on a substrate 11 along the thickness direction of the substrate 11. The material and thickness of the first semiconductor film 12 can be set by referring to the material and thickness of the first semiconductor layer described above. As shown in fig. 3a and 3b, the first semiconductor film 12 and the top of the substrate 11 may be etched from top to bottom through photolithography and etching processes to form a first fin structure 13 and a second fin structure 14 extending in a first direction. Wherein the first fin structure 13 is formed on the first well region 111. The second fin structure 14 is formed on the second well region 112. The depth of the substrate 11 to be etched may be set according to the thickness of the subsequently formed shallow trench isolation 15 and the practical application scenario, and is not limited herein. As shown in fig. 5a and 5b, an isolation material may be deposited between the adjacent first fin structure 13 and second fin structure 14, and etched back to form a shallow trench isolation 15. The top of the shallow trench isolation 15 may be flush with the top of the etched portion of the substrate 11 or may be lower or slightly higher than the top of the etched portion of the substrate 11. Accordingly, the exposed portion of the first fin structure 13 outside the shallow trench isolation 15 forms a first fin 131. The exposed portion of the second fin structure 14 outside the shallow trench isolation 15 forms a second fin 141. When the top of the shallow trench isolation 15 is flush with the top of the etched portion of the substrate 11, or slightly higher than the top of the etched portion of the substrate 11, the first fin 131 and the second fin 141 are both the first semiconductor layer 1314 formed on the surface of the substrate 11. The first semiconductor layer 1314 is a portion remaining after the first semiconductor film 12 is etched. When the top of the shallow trench isolation 15 is lower than the top of the etched portion of the substrate 11, the first fin 131 and the second fin 141 include a portion of the substrate 11 (i.e., the second semiconductor layer 1315) that is etched and exposed outside the shallow trench isolation 15, in addition to the first semiconductor layer 1314.
Note that, as shown in fig. 2a and 2b, the first fin structure 13 and the second fin structure 14 may be formed by etching only the substrate 11, in addition to etching the first semiconductor film 12 and the top of the substrate 11. The material of the substrate 11 is the same as that of the first material portion 26. At this time, as shown in fig. 4a and 4b, the first fin 131 and the second fin 141 are only the first semiconductor layer 1314 formed on the surface of the substrate 11. At this time, the first semiconductor layer 1314 is a portion of the substrate 11 that is etched and exposed outside the shallow trench isolation 15.
As shown in fig. 6a to 7b, a sacrificial gate 16 extending in the second direction is formed at the outer periphery of the gate forming region 1313. The second direction is different from the first direction.
Specifically, the second direction may be any direction parallel to the surface of the substrate and different from the first direction. Preferably, the second direction is orthogonal to the first direction.
In a practical application process, referring to fig. 6a to 7b, a gate material for forming the sacrificial gate 16 may be deposited on the first fin 131, the second fin 141 and the shallow trench isolation 15 by using a chemical vapor deposition method. Then, the gate material may be etched by dry etching, and only a portion of the gate material located at the periphery of the gate forming region 1313 is remained, so as to obtain the sacrificial gate 16 extending along the second direction. The gate material may be amorphous silicon, polysilicon, or other materials that are easily removed. Further, after the sacrificial gate 16 is formed, the first and second sidewalls 17 and 18 may be formed on the sidewalls of the sacrificial gate 16 in the above-described manner. The first and second side walls 17 and 18 are distributed on both sides of the sacrificial gate 16 in the width direction of the sacrificial gate 16. The first side wall 17 and the second side wall 18 may be made of an insulating material such as silicon nitride.
As shown in fig. 8 and 9, a source region 19 and a drain region 20 are formed in the source region formation region 1311 and the drain region formation region 1312, respectively. The gate formation region 1313 is located between the source region 19 and the drain region 20.
For example, if the portions of the first fin portion and the second fin portion located in the source region formation region and the drain region formation region are not removed after the sacrificial gate, the first sidewall and the second sidewall are formed, the source region and the drain region may be respectively formed in the source region formation region and the drain region formation region by directly adopting an ion implantation method or the like. If the parts of the first fin portion and the second fin portion, which are located in the source region forming region and the drain region forming region, are removed after the sacrificial gate, the first side wall and the second side wall are formed, epitaxial growth can be performed in the source region forming region and the drain region forming region respectively to obtain the source region and the drain region. At this time, the gate formation region is located between the source region and the drain region. Of course, the source region and the drain region may be formed in other satisfactory manners besides the above-described formation manner.
As shown in fig. 10 and 11, in an example, in the case where the first transistor 30 and the second transistor 31 further include the first dielectric layer 21 and the second dielectric layer 22, as described above, after the source region formation region 1311 and the drain region formation region 1312 form the source region 19 and the drain region 20, respectively, and before the sacrificial gate 16 is removed, the manufacturing method of the semiconductor device described above further includes: a first dielectric layer 21 is formed on the surface of the source region 19 facing away from the substrate 11 and a second dielectric layer 22 is formed on the surface of the drain region 20 facing away from the substrate 11.
Illustratively, as shown in fig. 10 and 11, a dielectric material covering the source region 19, the drain region 20 and the sacrificial gate 16 may be formed by chemical vapor deposition or the like. The dielectric material may then be thinned by chemical mechanical polishing or the like until the top of the sacrificial gate 16 is exposed. Accordingly, the remaining dielectric material only covers the source region 19 and the drain region 20, thereby obtaining a first dielectric layer 21 and a second dielectric layer 22. The materials and thicknesses of the first dielectric layer 21 and the second dielectric layer 22 can be referred to above.
As shown in fig. 12 and 13, the sacrificial gate 16 is removed. And a channel region 23 included in the first transistor 30 is formed over the first well region 111 and a channel formation region 24 is formed over the second well region 112. The channel region 23 and the channel forming region 24 each have a first material portion 26 formed on the substrate 11.
Specifically, the sacrificial gate located at the periphery of the gate formation region may be selectively removed by wet etching or the like. The first transistor and the second transistor are both fin field effect transistors. The fin field effect transistor includes a channel region that is a fin structure formed on a surface of the substrate. Based on this, after the sacrificial gate is removed, the portions of the first fin portion and the second fin portion located in the gate formation region are exposed. At this time, the gate formation region included in the first fin portion forms a channel region included in the first transistor. The gate forming region included in the second fin portion forms a channel forming region. As shown above, when the first fin portion and the second fin portion are the first semiconductor layer formed on the surface of the substrate, a portion of the first semiconductor layer located in the gate forming region forms the first material portion. And when the first fin part and the second fin part comprise a first semiconductor layer and a second semiconductor layer which are stacked on the substrate along the thickness direction of the substrate, the part of the first semiconductor layer, which is positioned in the grid electrode forming area, forms a first material part. The portion of the second semiconductor layer located within the gate forming region forms a third material portion.
As shown in fig. 14 and 15, the channel formation region 24 is subjected to thinning treatment by the mask action of the mask layer 25. A mask layer 25 covers the first well region 111 and the channel region 23 comprised by the first transistor 30.
Illustratively, as shown in fig. 14 and fig. 15, a mask layer 25 covering the first well region 111 and the channel region 23 included in the first transistor 30 may be formed by deposition, spin coating, or the like. The mask layer 25 may be made of Spin-On-Glass (SOG), spin-On-Carbon (SOC), or amorphous silicon. Next, under the mask action of the mask layer 25, the channel formation region 24 located on the second well region 112 may be oxidized, and the oxide layer may be removed, so as to implement the thinning process on the channel formation region 24. Alternatively, the thinning process for the channel formation region 24 may be performed by an isotropic etching process. Alternatively, when the channel region 23 on the first well region 111 and the channel formation region 24 on the second well region 112 include only the first material portion 26 formed on the surface of the substrate 11, the channel formation region 24 may be thinned by performing isotropic etching of the first material portion 26 using high-temperature HCL gas in an epitaxial process chamber.
In the case where the channel region 23 on the first well region 111 and the channel formation region 24 on the second well region 112 each include the third material portion 28 formed on the surface of the substrate 11 and the first material portion 26 located on the third material portion 28, when the channel formation region 24 is subjected to the thinning process, only the first material portion may be subjected to the thinning process. Alternatively, the first material portion 26 and the third material portion 28 may be thinned at the same time, and the thicknesses to be removed by the thinning may be the same or different.
Specifically, the thickness of the channel formation region subjected to the thinning treatment may be set according to the thickness of the second material portion to be formed later. Wherein the greater the thickness of the channel formation region subjected to the thinning process, the greater the thickness of the second material portion without affecting the formation region range of the gate stack structure. In this case, since the material of the second material portion is different from the material of the first material portion, the greater the thickness of the second material portion is, the less the materials of the channel regions included in the first transistor and the second transistor are, and the greater the difference between the threshold voltages of the first transistor and the second transistor is.
As shown in fig. 16 and 17, the second material portion 27 is formed on the outer periphery of the channel formation region 24 after the thinning process, and the channel region 23 included in the second transistor 31 is obtained.
Specifically, the material of the second material portion may be any one of silicon, silicon germanium, and germanium. In this case, the magnitude of the threshold voltage which the second transistor has can be adjusted by adjusting the content of germanium in the second material portion and the doping concentration of the impurity. In addition, after the second material portion is formed, the mask layer covering the first well region and the channel region included in the first transistor may be removed by dry etching or wet etching, so as to facilitate subsequent operations.
In one example, in a case where the first material portion contains germanium, after the second material portion is formed on the outer periphery of the channel formation region after the thinning process to obtain the channel region included in the second transistor, before the gate stack structure is formed on the outer periphery of the channel regions included in the first transistor and the second transistor, the method of manufacturing a semiconductor device may further include: a first passivation layer is formed at an outer periphery of a channel region included in the first transistor.
Illustratively, O may be used under the action of a mask 3 A first passivation layer may be formed on an outer circumference of a channel region included in the first transistor in a passivation manner or in a selective epitaxy manner. The mask covers the second well region and a channel region included by the second transistor. In addition, reference may be made to the material and the layer thickness of the first passivation layer.
Of course, in the case where the second material portion contains germanium, after the second material portion is formed on the outer periphery of the channel formation region after the thinning process to obtain the channel region included in the second transistor, before the gate stack structure is formed on the outer periphery of the channel regions included in the first transistor and the second transistor, the method of manufacturing the semiconductor device may further include: a second passivation layer is formed at an outer periphery of a channel region included in the second transistor.
For example, the mask layer overlying the first well region and the channel region included in the first transistor may not be removed after the second material portion is formed. And adopting O under the action of the mask layer 3 A second passivation layer may be formed on an outer circumference of the channel region included in the second transistor in a passivation manner or in a selective epitaxy manner. The material and the layer thickness of the second passivation layer can be referred to above.
In addition, in the case where the first material portion and the second material portion both contain germanium, the first passivation layer may be formed on the outer periphery of the channel region included in the first transistor, and the second passivation layer may be formed on the outer periphery of the channel region included in the second transistor at the same time, without forming the mask or continuously retaining the mask layer.
As shown in fig. 18 and 19, a gate stack structure 29 is formed on the outer periphery of the channel region 23 included in the first transistor 30 and the second transistor 31.
For example, a gate stack structure may be formed around the channel region included in the first transistor and the second transistor by atomic layer deposition or the like. Specifically, the specific structure and material of the gate stack structure can refer to the foregoing, and are not described herein again.
As can be seen from the above, in the method for manufacturing a semiconductor device according to the embodiment of the present invention, after the first material portion is formed on the first well region and the second well region, the first transistor and the second transistor have different threshold voltages only by forming the second material portion on the periphery of the first material portion of the second well region, and it is not necessary to form gate stack structures with different thicknesses or materials on the peripheries of channel regions included in the different transistors by multiple deposition-etching-deposition methods, so that the manufacturing process of the semiconductor device can be simplified, and the yield and performance of the semiconductor device can be improved.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, the person skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims (15)

1. A semiconductor device, comprising:
a substrate; the substrate comprises a first well region and a second well region;
a first transistor formed on the first well region; the first transistor includes a channel region having a first material portion;
a second transistor formed on the second well region; the second transistor and the first transistor are different in conductivity type; a channel region included in the second transistor includes a first material portion and a second material portion formed on an outer periphery of the first material portion; the material of the second material part is different from that of the first material part; the second transistor and the first transistor are both fin field effect transistors; the second transistor has a thickness and a width of the first material portion that are less than a thickness and a width of the first material portion, respectively, of the first transistor.
2. The semiconductor device according to claim 1, wherein the first material portion is formed on a surface of the substrate; or the like, or, alternatively,
the channel region included in the first transistor and the second transistor further has a third material portion; the third material portion is formed between the substrate and the first material portion; the second material portion is formed on the outer periphery of the first material portion and the third material portion.
3. The method according to claim 2, wherein when the channel regions included in the first transistor and the second transistor further include the third material portion, the third material portion is made of one of silicon, silicon germanium, and germanium.
4. A semiconductor device according to any one of claims 1 to 3, wherein a thickness and a width of a channel region included in the first transistor are equal to a thickness and a width of a channel region included in the second transistor, respectively.
5. The semiconductor device according to any one of claims 1 to 3, wherein a material of the first material portion or the second material portion is one of silicon, silicon germanium, and germanium;
when the material of the first material portion and the material of the second material portion both contain germanium, the content of germanium in the first material portion and the content of germanium in the second material portion are different from each other.
6. The semiconductor device according to claim 5, wherein in the case where a content of germanium in the first material portion is larger than a content of germanium in the second material portion, the first transistor is a PMOS transistor and the second transistor is an NMOS transistor.
7. The semiconductor device according to claim 5, wherein in a case where the first material portion contains germanium, the first transistor further comprises a first passivation layer formed in a periphery of the channel region; and/or the presence of a gas in the atmosphere,
in the case where the second material portion contains germanium, the second transistor further includes a second passivation layer formed on an outer periphery of the channel region.
8. The semiconductor device according to any one of claims 1 to 3, wherein the first transistor and the second transistor further include: a source region, a drain region and a gate stack structure; the channel region is positioned between the source region and the drain region and is respectively contacted with the source region and the drain region; the gate stack structure is formed at the outer periphery of the channel region.
9. The semiconductor device according to claim 8, wherein the first transistor and the second transistor further comprise: a first dielectric layer and a second dielectric layer; the first dielectric layer is formed on the surface of the source region, which faces away from the substrate; the second dielectric layer is formed on a surface of the drain region facing away from the substrate.
10. A method of manufacturing a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises a first well region and a second well region;
forming a first transistor on the first well region and a second transistor on the second well region; the first transistor includes a channel region having a first material portion; the second transistor and the first transistor are different in conductivity type; a channel region included in the second transistor includes a first material portion and a second material portion formed on an outer periphery of the first material portion; the material of the second material part is different from that of the first material part; the second transistor and the first transistor are both fin field effect transistors; wherein the content of the first and second substances,
the forming a first transistor over the first well region and a second transistor over the second well region includes:
forming a channel region included in the first transistor over the first well region, and forming a channel formation region over the second well region; the channel region and the channel formation region each have the first material portion formed on a substrate;
thinning the channel forming region under the mask action of the mask layer, so that the thickness and the width of a first material part of the channel forming region are respectively smaller than those of the first material part of the channel region; the mask layer covers the first well region and a channel region included by the first transistor;
and forming the second material portion on the periphery of the thinned channel forming region to obtain a channel region included in the second transistor.
11. The method of manufacturing a semiconductor device according to claim 10, wherein after the providing a substrate, before forming a channel region included in the first transistor over the first well region and forming a channel formation region over the second well region, the method further comprises:
forming a first fin portion and a second fin portion extending along a first direction on the substrate; the first fin portion is located on the first well region, and the second fin portion is located on the second well region; the first fin portion and the second fin portion respectively comprise a source region forming region, a drain region forming region and a grid electrode forming region located between the source region forming region and the drain region forming region;
forming a sacrificial gate extending along a second direction on the periphery of the gate forming region; the second direction is different from the first direction;
forming a source region and a drain region in the source region forming region and the drain region forming region, respectively; the grid electrode forming region is positioned between the source region and the drain region;
removing the sacrificial gate;
after the second material portion is formed on the outer periphery of the channel formation region after the thinning process to obtain the channel region included in the second transistor, the method for manufacturing a semiconductor device further includes:
a gate stack structure is formed at an outer periphery of a channel region included in the first transistor and the second transistor.
12. The method of manufacturing a semiconductor device according to claim 11, wherein a shallow trench isolation is formed in a portion of the substrate between the first fin portion and the second fin portion; the first fin portion and the second fin portion are exposed outside the shallow trench isolation;
the first fin part and the second fin part are first semiconductor layers formed on the surface of the substrate; or the first fin part and the second fin part comprise a first semiconductor layer and a second semiconductor layer which are stacked on the surface of the substrate along the thickness direction of the substrate; the first semiconductor layer is located on the second semiconductor layer.
13. The method according to claim 12, wherein the forming a channel region included in the first transistor over the first well region and forming a channel formation region over the second well region includes:
after the sacrificial gate is removed, the channel region is formed in a gate forming region included in the first fin portion; the gate forming region included in the second fin portion forms the channel forming region; wherein the content of the first and second substances,
when the first fin portion and the second fin portion are the first semiconductor layer formed on the surface of the substrate, the first material portion is formed on the portion, located in the gate forming region, of the first semiconductor layer;
when the first fin portion and the second fin portion comprise the first semiconductor layer and the second semiconductor layer which are stacked on the surface of the substrate along the thickness direction of the substrate, the first material portion is formed on the portion, located in the grid electrode forming area, of the first semiconductor layer; the portion of the second semiconductor layer located within the gate forming region forms a third material portion.
14. The method according to claim 11, wherein in a case where the first material portion contains germanium, after the second material portion is formed on an outer periphery of the channel formation region after the thinning process to obtain a channel region included in the second transistor, before the outer peripheries of the channel regions included in the first transistor and the second transistor form a gate stack structure, the method further comprises:
forming a first passivation layer at an outer periphery of a channel region included in the first transistor; and/or the presence of a gas in the gas,
in a case where the second material portion contains germanium, the method for manufacturing a semiconductor device may further include, after the second material portion is formed on the outer periphery of the channel formation region after the thinning process to obtain the channel region included in the second transistor, before the gate stack structure is formed on the outer peripheries of the channel regions included in the first transistor and the second transistor:
a second passivation layer is formed at an outer periphery of a channel region included in the second transistor.
15. The method for manufacturing a semiconductor device according to claim 11, wherein after the source region formation region and the drain region formation region respectively form a source region and a drain region, and before the sacrificial gate is removed, the method for manufacturing a semiconductor device further comprises:
and forming a first dielectric layer on the surface of the source region, which faces away from the substrate, and forming a second dielectric layer on the surface of the drain region, which faces away from the substrate.
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Publication number Priority date Publication date Assignee Title
CN110828458A (en) * 2018-08-13 2020-02-21 三星电子株式会社 Semiconductor device with a plurality of transistors
CN110896055A (en) * 2019-11-19 2020-03-20 中国科学院微电子研究所 Preparation method of stacked nanowire or wafer ring gate CMOS (complementary metal oxide semiconductor) device
CN111710713A (en) * 2020-05-12 2020-09-25 中国科学院微电子研究所 Fin type field effect transistor, manufacturing method thereof and electronic equipment

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110828458A (en) * 2018-08-13 2020-02-21 三星电子株式会社 Semiconductor device with a plurality of transistors
CN110896055A (en) * 2019-11-19 2020-03-20 中国科学院微电子研究所 Preparation method of stacked nanowire or wafer ring gate CMOS (complementary metal oxide semiconductor) device
CN111710713A (en) * 2020-05-12 2020-09-25 中国科学院微电子研究所 Fin type field effect transistor, manufacturing method thereof and electronic equipment

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