CN115662992A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
- Publication number
- CN115662992A CN115662992A CN202211375981.9A CN202211375981A CN115662992A CN 115662992 A CN115662992 A CN 115662992A CN 202211375981 A CN202211375981 A CN 202211375981A CN 115662992 A CN115662992 A CN 115662992A
- Authority
- CN
- China
- Prior art keywords
- transistor
- layer
- region
- isolation
- channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention discloses a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductors, and aims to improve the control capability of a first transistor and a second transistor on channel current. The semiconductor device includes: the semiconductor device comprises a semiconductor substrate, a first isolation dielectric wall, a first transistor and a second transistor. The first isolation dielectric wall is formed on the first dielectric layer included in the semiconductor substrate. The first transistor is formed on the first dielectric layer and located on one side of the first isolation dielectric wall in the width direction. The first transistor comprises a first channel region and a first isolation dielectric wall which are arranged at intervals and are provided with at least two first channel parts. At least two first channel parts are distributed at intervals along the width direction parallel to the first isolation medium wall. The second transistor is formed on the first dielectric layer and is positioned on one side of the first isolation dielectric wall, which is far away from the first transistor. The second transistor includes a second channel region spaced apart from the first isolation dielectric wall. The second transistor is of opposite conductivity type to the first transistor.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.
Background
Fork (forskhet, abbreviated as FSH) devices are advantageous for miniaturization of semiconductor devices by introducing "dielectric walls" between the P-type and N-type transistors prior to gate patterning to further reduce the pitch between the P-type and N-type transistors.
However, in the conventional forkshet device, the control capability of a P-type transistor and an N-type transistor on channel current is poor, and the improvement of the electrical performance of the forkshet device is not facilitated.
Disclosure of Invention
The invention aims to provide a semiconductor device and a manufacturing method thereof, which are used for improving the control capability of a first transistor and a second transistor on channel current and are beneficial to improving the electrical performance of a Forksheet device.
In a first aspect, the present invention provides a semiconductor device. The semiconductor device includes: the transistor comprises a semiconductor substrate, a first isolation dielectric wall, a first transistor and a second transistor.
The semiconductor base comprises a semiconductor substrate and a first dielectric layer positioned on the semiconductor substrate. The first isolation dielectric wall is formed on the first dielectric layer. The first transistor is formed on the first dielectric layer and located on one side of the first isolation dielectric wall in the width direction. The first transistor comprises a first channel region and a first isolation dielectric wall which are arranged at intervals and are provided with at least two first channel parts. At least two first channel parts are distributed at intervals along the width direction parallel to the first isolation medium wall. Each first channel portion has a gap with the first dielectric layer, and the first transistor includes a first gate stack structure surrounding an outer circumference of each first channel portion. The second transistor is formed on the first dielectric layer and is positioned on one side of the first isolation dielectric wall, which is far away from the first transistor. The second transistor includes a second channel region spaced apart from the first isolation dielectric wall. The second transistor is of opposite conductivity type to the first transistor.
Compared with the prior art, the semiconductor device provided by the invention has the advantages that the first isolation dielectric wall is formed on the first dielectric layer included by the semiconductor substrate. The first transistor and the second transistor are respectively formed on two sides of the first isolation dielectric wall along the width direction, and the conductivity types of the first transistor and the second transistor are opposite, so that the semiconductor device provided by the invention is a Forksheet device. In addition, the first transistor includes a first channel region spaced apart from the first isolation dielectric wall. And at least two first channel parts included in the first channel region are distributed at intervals along the width direction parallel to the first isolation dielectric wall. A gap is formed between each first channel portion and the first dielectric layer, and at the moment, the top surface, the bottom surface and the side surface in the width direction of each first channel portion included in the first channel region are exposed outside, so that the first gate stacking structure included in the first transistor can surround the periphery of each first channel portion, the problem that the gate stacking structure cannot cover the side wall, close to the dielectric wall, of the channel region due to the fact that the channel regions included in the P-type transistor and the N-type transistor are in contact with the dielectric wall in the existing Forksheet device can be solved, and the control capacity of the first gate stacking structure included in the first transistor on each first channel portion is improved. Similarly, the second channel region included by the second transistor is spaced from the first isolation dielectric wall, so that the second gate stack structure included by the second transistor can also cover the side wall of the second channel portion close to the first isolation dielectric wall, thereby improving the control capability of the second gate stack structure on the second channel portion and improving the electrical performance of the semiconductor device.
In addition, in the semiconductor device provided by the invention, the first transistor and the second transistor are both formed on the first dielectric layer, and the first dielectric layer is a non-conductive insulating layer, so that the existence of the first dielectric layer can prevent parasitic channel leakage, and the gate control capability of the first gate stack structure and the second gate stack structure is further improved.
In a second aspect, the present invention also provides a method of manufacturing a semiconductor device, the method comprising:
a semiconductor substrate is provided. The semiconductor base comprises a semiconductor substrate and a first dielectric layer positioned on the semiconductor substrate.
And forming a first isolation dielectric wall on the first dielectric layer.
A first transistor and a second transistor are formed on the first dielectric layer. The first transistor is located on one side of the first isolation dielectric wall along the width direction. The first transistor comprises a first channel region and a first isolation dielectric wall which are arranged at intervals and are provided with at least two first channel parts. At least two first channel parts are distributed at intervals along the width direction parallel to the first isolation medium wall. Each first channel portion has a gap with the first dielectric layer, and the first transistor includes a first gate stack structure surrounding an outer periphery of each first channel portion. The second transistor is located on a side of the first isolation dielectric wall facing away from the first transistor. The second transistor includes a second channel region spaced apart from the first isolation dielectric wall. The second transistor is of opposite conductivity type to the first transistor.
Compared with the prior art, the beneficial effects of the manufacturing method of the semiconductor device provided by the invention can be analyzed by referring to the beneficial effects of the semiconductor device provided by the invention, and are not repeated herein.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic longitudinal cross-sectional view of a conventional Forksheet device;
figure 2 is a schematic diagram illustrating a first structure after forming a first fin structure in accordance with an embodiment of the present invention;
figure 3 is a schematic diagram illustrating a second structure after forming a first fin structure in accordance with an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a first semiconductor layer and a second semiconductor layer after being formed according to an embodiment of the present invention;
FIG. 5 is a schematic structural diagram of a first semiconductor layer, a sacrificial layer and a second semiconductor layer after forming the first semiconductor layer, the sacrificial layer and the second semiconductor layer according to the embodiment of the present invention;
fig. 6 is a schematic structural view of the embodiment of the invention after the first fin structure is removed;
FIG. 7 is a schematic structural diagram illustrating the formation of an isolation dielectric material in an embodiment of the present invention;
FIG. 8 is a schematic structural diagram of the first insulating medium wall formed in the embodiment of the present invention;
FIG. 9 is a schematic structural diagram of a first insulating dielectric wall, a first insulating material and a second insulating material after forming an embodiment of the present invention;
FIG. 10 is a schematic diagram of a first structure after forming a sacrificial gate according to an embodiment of the present invention;
FIG. 11 is a diagram illustrating a second structure after forming a sacrificial gate according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram after forming a gate sidewall spacer in the embodiment of the present invention;
fig. 13 is a schematic structural diagram of the first semiconductor layer and the second semiconductor layer in the first region and the second region after removing portions of the first semiconductor layer and the second semiconductor layer in the embodiment of the present invention;
fig. 14 is a schematic longitudinal cross-sectional view of the structure at the first material layer along the length direction of the first dielectric isolation wall after removing portions of the first semiconductor layer and the second semiconductor layer in the first region and the second region according to the embodiment of the present invention;
FIG. 15 is a schematic longitudinal cross-sectional view of a first structure after forming first and second source/drain regions in an embodiment of the invention;
FIG. 16 is a schematic longitudinal cross-sectional view of a second structure after forming first and second source/drain regions in accordance with an embodiment of the invention;
FIG. 17 is a structural diagram illustrating a second dielectric layer formed in an embodiment of the invention;
FIG. 18 is a schematic longitudinal cross-sectional view of the first structure at the third region after the sacrificial gate is removed in an embodiment of the present invention;
FIG. 19 is a schematic longitudinal cross-sectional view of a second structure at a third region after removal of the sacrificial gate in an embodiment of the present invention;
fig. 20 is a schematic longitudinal cross-sectional view of the structure after the first material layer included in the first semiconductor layer and the second semiconductor layer is removed simultaneously in the embodiment of the present invention;
FIG. 21 is a schematic longitudinal cross-sectional view of a structure after selectively removing a first material layer included in a first semiconductor layer according to an embodiment of the invention;
FIG. 22 is a schematic longitudinal cross-sectional view of a structure after further selective removal of the sacrificial layer and the second material layer included in the second semiconductor layer in an embodiment of the present invention;
FIG. 23 is a schematic longitudinal cross-sectional view of a structure after forming a first channel region and a second channel region of different materials in an embodiment of the invention;
FIG. 24 is a schematic longitudinal cross-sectional view of the structure after selective removal of the sacrificial layer and the second material layer included in the second semiconductor layer in accordance with an embodiment of the present invention;
FIG. 25 is a schematic longitudinal cross-sectional view of a structure after further selective removal of a first material layer included in a first semiconductor layer according to an embodiment of the invention;
fig. 26 is a schematic longitudinal cross-sectional view of a structure after performing etching back treatment on a portion of the first dielectric layer, which is located near the first channel region, of the first isolation dielectric wall in the embodiment of the present invention;
FIG. 27 is a schematic longitudinal cross-sectional view of the structure after removal of the corresponding mask layer in an embodiment of the present invention;
fig. 28 is a schematic longitudinal cross-sectional view of a structure after performing etching back processing on portions of the first dielectric layer on both sides of the first insulating dielectric wall in the width direction according to the embodiment of the present invention;
FIG. 29 is a schematic longitudinal cross-sectional view of the first structure after forming a first gate stack structure and a second gate stack structure in an embodiment of the invention;
FIG. 30 is a schematic longitudinal cross-sectional view of a second structure after forming a first gate stack structure and a second gate stack structure in accordance with an embodiment of the present invention;
fig. 31 is a schematic cross-sectional view illustrating a structure after a first gate stack structure and a second gate stack structure are formed according to an embodiment of the present invention;
fig. 32 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
Reference numerals: 11 is a semiconductor base, 111 is a semiconductor substrate, 112 is a first dielectric layer, 12 is a first fin-shaped structure, 13 is a first semiconductor layer, 14 is a second semiconductor layer, 15 is a stack, 151 is a first material layer, 152 is a second material layer, 16 is a sacrificial layer, 17 is an isolation region, 18 is an isolation dielectric material, 181 is a first isolation dielectric wall, 182 is a first isolation material, 1821 is a second isolation dielectric wall, 183 is a second isolation material, 1831 is a third isolation dielectric wall, 19 is a second fin-shaped structure, 191 is a first region, 192 is a second region, 193 is a third region, 20 is a sacrificial gate, 21 is a gate sidewall, 22 is a first source/drain region, 23 is a second source/drain region, 24 is a second dielectric layer, 25 is a first channel region, 251 is a first channel portion, 26 is a second channel region, 261 is a second channel portion, 27 is a first gate stack structure, and 28 is a second gate stack structure; 29 is an N-type transistor, 30 is a P-type transistor, 31 is a dielectric wall, 32 is a gate stack structure, and 33 is a channel region.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that these descriptions are illustrative only and are not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and some details may be omitted for clarity of presentation. The shapes of the various regions, layers and their relative sizes, positional relationships are shown in the drawings as examples only, and in practice deviations due to manufacturing tolerances or technical limitations are possible, and a person skilled in the art may additionally design regions/layers with different shapes, sizes, relative positions according to the actual needs.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed. In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise. The meaning of "a number" is one or more unless specifically limited otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or may be connected through the use of two elements or the interaction of two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
With the rapid development of the integrated circuit industry, the demand for high-speed and high-voltage circuit design is increasing. At the same time, the number of transistors per unit area is increasing. Among them, the forkshet device can reduce the pitch of N-type transistors and P-type transistors, which can further reduce the chip area while retaining the structure of horizontally stacked nanowires/sheets, so the forkshet device becomes one of the best choices for next-generation new structure devices. Specifically, as shown in fig. 1, the conventional forkshet device is advantageous to miniaturize the semiconductor device by introducing a "dielectric wall 31" between the P-type transistor 30 and the N-type transistor 29 before gate patterning, so that the pitch between the P-type transistor 30 and the N-type transistor 29 is further reduced.
However, as shown in fig. 1, the channel regions 33 included in the P-type transistor 30 and the N-type transistor 29 in the conventional forkheet device are both in contact with the dielectric wall 31, so that the gate stack structure 32 included in the P-type transistor 30 and the N-type transistor 29 does not cover the sidewall of the channel close to the dielectric wall 31, which reduces the control capability of the P-type transistor 30 and the N-type transistor 29 on the channel current, and is not favorable for improving the electrical performance of the forkheet device.
In order to solve the above technical problem, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same. In the semiconductor device provided in the embodiment of the present invention, the first channel region included in the first transistor and the second channel region included in the second transistor are respectively disposed at an interval from the first isolation dielectric wall, so as to improve the control capability of the first gate stack structure on each first channel portion, improve the control capability of the second gate stack structure on the second channel portion, and improve the electrical performance of the semiconductor device.
As shown in fig. 29 to 31, an embodiment of the present invention provides a semiconductor device. The semiconductor device includes: a semiconductor substrate 11, a first isolation dielectric wall 181, a first transistor and a second transistor.
As shown in fig. 29 to 31, the semiconductor base 11 includes a semiconductor substrate 111 and a first dielectric layer 112 on the semiconductor substrate 111. First insulating dielectric walls 181 are formed on the first dielectric layer 112. The first transistor is formed on the first dielectric layer 112 and is located on one side of the first isolation dielectric wall 181 in the width direction. The first transistor includes a first channel region 25 spaced apart from the first insulating dielectric wall 181 and having at least two first channel portions 251. At least two first channel portions 251 are spaced apart in a direction parallel to the width direction of the first separating dielectric wall 181. Each of the first channel portions 251 has a space with the first dielectric layer 112, and the first transistor includes a first gate stack structure 27 surrounding the outer circumference of each of the first channel portions 251. The second transistor is formed on the first dielectric layer 112 and on a side of the first isolation dielectric wall 181 facing away from the first transistor. The second transistor comprises a second channel region 26 spaced apart from the first insulating dielectric wall 181. The second transistor is of opposite conductivity type to the first transistor.
In particular, the specific structure and material of the semiconductor substrate can be set according to the actual application scenario. For example: as shown in fig. 2, the semiconductorThe bulk substrate 11 may be a silicon-on-insulator substrate, a germanium-silicon-on-insulator substrate, or a germanium-on-insulator substrate. At this time, the first dielectric layer 112 is a buried oxide layer on the semiconductor substrate 111. Another example is: the first dielectric layer 112 included in the semiconductor substrate 11 is a shallow trench isolation formed on the semiconductor substrate 111 by a chemical vapor deposition process or the like. In this case, the semiconductor substrate 111 may be a semiconductor substrate such as a silicon substrate, a silicon germanium substrate, or a germanium substrate. As shown in fig. 3, after forming the first fin structure 12 on the semiconductor substrate 111, a first dielectric layer 112 may be formed on the exposed portion of the semiconductor substrate 111 outside the first fin structure 12 by using chemical vapor deposition and etch-back processes. The thickness of the first dielectric layer 112 may be set according to actual requirements, and is not particularly limited herein. The material of the first dielectric layer 112 may be SiN, si 3 N 4 、SiO 2 Or an insulating material such as SiCO.
As for the first isolation dielectric wall, the shape and specification of the first isolation dielectric wall can be set according to practical application scenarios as long as the first transistor and the second transistor with opposite conduction types can be isolated by the first isolation dielectric wall. For example: as shown in fig. 29 to 31, the first isolation dielectric wall 181 may be a fin-shaped structure formed on the first dielectric layer 112. The first isolation medium wall 181 may be a linear isolation medium wall, a wavy isolation medium wall, an arc isolation medium wall, or the like. The first isolation dielectric wall 181 may be made of SiN or Si 3 N 4 、SiO 2 Or an insulating material such as SiCO.
For the first transistor and the second transistor, the first transistor may be an N-type transistor in terms of conductivity type, and the second transistor may be a P-type transistor in this case. Alternatively, the first transistor may be a P-type transistor, and in this case, the second transistor may be an N-type transistor.
In terms of the device type, as shown in fig. 29 and 30, the first transistor is a gate-all-around transistor. The second transistor may be a fin field effect transistor or a gate-all-around transistor.
Specifically, the number of the first channel portions of the first channel region included in the first transistor may be set according to actual requirements, and is not particularly limited herein. In addition, the distance between every two adjacent first channel portions, the minimum distance between the first channel portions and the first isolation dielectric walls, and the distance between each first channel portion and the first dielectric layer in all the first channel portions included in the first channel region may be determined according to the specification of the first gate stack structure included in the first transistor, and are not specifically limited herein. In addition, the material of the at least two first channel portions included in the first channel region may be the same. For example: the first channel region may include all of the first channel portion of a material that is silicon, silicon germanium, or germanium. Alternatively, the first channel region includes all of the first channel portions, and at least one of the first channel portions is different from the remaining first channel portions in material. For example: in the case where the first channel region includes two first channel portions, a material of one of the first channel portions may be silicon, and a material of the other first channel portion may be silicon germanium.
As for the first source/drain region and the first gate stack structure included in the first transistor, the material of the first source/drain region may be silicon, silicon germanium, or semiconductor material such as group iii-v semiconductor material. The first gate stack structure includes a gate dielectric layer formed at least at an outer periphery of each of the first channel portions, and a gate electrode formed on the gate dielectric layer. The gate dielectric layer may be made of insulating material with low dielectric constant such as silicon oxide or silicon nitride, or may be made of HfO 2 、ZrO 2 、TiO 2 Or Al 2 O 3 And insulating materials with higher dielectric constants. The gate may be made of polysilicon, tiN, taN, tiSiN or other conductive materials.
As for the second transistor, the second transistor includes second source/drain regions formed at both sides of the second channel region in the length direction. The material of the second source/drain region may be the same as or different from the material of the first source/drain region. The specific structure of the second channel region and the second gate stack structure included in the second transistor may be determined according to the device type of the second transistor. Illustratively, as shown in fig. 29, in the case where the second transistor is a fin field effect transistor, the second channel region 26 includes at least one second channel portion 261 formed on the first dielectric layer 112. Also, the second gate stack structure 28 included in the second transistor is formed on the top of each second channel portion 261 and on both sides in the width direction. The width direction of the second channel portion 261 is parallel to the width direction of the first insulating dielectric wall 181.
Alternatively, as shown in fig. 30, in the case where the second transistor is a gate-all-around transistor, the second channel region 26 includes at least one second channel portion 261 formed over the first dielectric layer 112 and spaced apart from the first dielectric layer 112. Also, the second transistor includes a second gate stack structure 28 surrounding an outer circumference of each second channel portion 261.
The number of the second channel portions included in the second channel region may be one or more than one, regardless of whether the device type of the second transistor is a fin field effect transistor or a gate all around transistor. The specific number of the second channel portions included in the second channel region may be set according to an actual application scenario, and is not specifically limited herein. Illustratively, in a case where the second channel region includes at least two second channel portions, the at least two second channel portions are spaced apart in a direction parallel to the width direction of the first dielectric separation wall.
Specifically, the minimum distance between all the second channel portions included in the second channel region and the first isolation dielectric wall, and the distance between two adjacent second channel portions when the second channel region includes a plurality of second channel portions, may be set according to the specification of the second gate stack structure, and are not limited herein.
In addition, when the second channel region includes a plurality of second channel portions, all the second channel portions may have the same material, or at least one of the second channel portions may have a material different from the remaining second channel portions. Next, as shown in fig. 20, the material of the first channel region 25 may be the same as the material of the second channel region 26. Alternatively, as shown in fig. 29 and 30, the materials of the first channel region 25 and the second channel region 26 may be different. At this time, the threshold voltages of the first transistor and the second transistor can be adjusted and controlled by adjusting the materials of the first channel region 25 and the second channel region 26, and the N-type transistor and the P-type transistor with heterogeneous channel materials in the forkheet device can be integrated.
And the second gate stack structure comprises a gate dielectric layer at least forming the periphery of the second channel region and a gate electrode formed on the gate dielectric layer. The materials of the gate dielectric layer and the gate electrode included in the second gate stack structure may refer to the materials of the gate dielectric layer and the gate electrode included in the first gate stack structure, respectively. Specifically, the material of the gate dielectric layer included in the second gate stack structure may be the same as or different from the material of the gate dielectric layer included in the first gate stack structure. The second gate stack structure may include a gate electrode of the same material as or different from the gate electrode of the first gate stack structure.
As shown in fig. 29 to 31, in the semiconductor device according to the embodiment of the present invention, the first isolation dielectric wall 181 is formed on the first dielectric layer 112 included in the semiconductor substrate 11. The first transistor and the second transistor are respectively formed on two sides of the first isolation dielectric wall 181 along the width direction, and the conductivity types of the first transistor and the second transistor are opposite, so that the semiconductor device provided by the embodiment of the invention is a forkshet device. In addition, the first transistor includes a first channel region 25 disposed spaced apart from the first insulating dielectric wall 181. And, at least two first channel portions 251 included in the first channel region 25 are spaced apart in a direction parallel to the width direction of the first partition dielectric wall 181. A gap is formed between each first channel portion 251 and the first dielectric layer 112, and at this time, the top surface, the bottom surface, and the side surfaces in the width direction of each first channel portion 251 included in the first channel region 25 are exposed outside, so that the first gate stack structure 27 included in the first transistor can surround the periphery of each first channel portion 251, which can solve the problem that the gate stack structure of the conventional forkshet device cannot cover the side wall of the channel region close to the dielectric wall due to the contact between the channel regions included in the P-type transistor and the N-type transistor, and improve the controllability of the first gate stack structure 27 included in the first transistor on each first channel portion 251. Similarly, since the second channel region 26 included in the second transistor is spaced apart from the first isolation dielectric wall 181, the second gate stack structure 28 included in the second transistor can also cover the sidewall of the second channel portion 261 close to the first isolation dielectric wall 181, so that the control capability of the second gate stack structure 28 on the second channel portion 261 can be improved, and the electrical performance of the semiconductor device can be improved.
In addition, as shown in fig. 29 to fig. 31, in the semiconductor device according to the embodiment of the present invention, the first transistor and the second transistor are both formed on the first dielectric layer 112, and the first dielectric layer 112 is a non-conductive insulating layer, so that the existence of the first dielectric layer 112 can prevent parasitic channel leakage, and further improve the gate control capability of the first gate stack structure 27 and the second gate stack structure 28.
In one example, as shown in fig. 29 and 30, the crystal orientation of the first channel region 25 may be a [110] crystal orientation. In this case, since the channel having the [110] crystal orientation is advantageous for transporting holes, it is advantageous to improve the hole mobility of the first channel region 25 when the crystal orientation of the first channel region 25 is the [110] crystal orientation.
Of course, the crystal orientation of the first channel region may be [100] crystal orientation in addition to [110] crystal orientation. Since the channel having a [100] crystal orientation is advantageous for transporting electrons, it is advantageous for improving the electron mobility of the first channel region when the crystal orientation of the first channel region is the [100] crystal orientation.
It is noted that the crystal orientation of the first channel region may be determined according to the conductivity type of the first transistor, due to the difference in mobility of the channel having the [100] crystal orientation and the [110] crystal orientation to electrons and holes, respectively. For example: in the case where the first transistor is an N-type transistor, the crystal orientation of the first channel region may be a [100] crystal orientation. Another example is: in the case where the first transistor is a P-type transistor, the first channel region may have a crystal orientation of [110 ].
In one example, as shown in fig. 29 and 30, the crystal orientation of the second channel region 26 may be a [110] crystal orientation. The beneficial effect of this case can be analyzed by referring to the aforementioned beneficial effect that the crystal orientation of the first channel region 25 is the [110] crystal orientation, and the description thereof is omitted.
In addition, the crystal orientation of the second channel region may also be a [100] crystal orientation. The specific crystal orientation of the second channel region may be determined according to the conductivity type of the second channel region, and is not particularly limited herein.
In one example, as shown in fig. 31, the semiconductor device may further include a second isolation dielectric wall 1821. The second insulating dielectric wall 1821 is formed on a side of the first transistor including the first source/drain region 22 facing away from the first insulating dielectric wall 181. In this case, as shown in fig. 13 and 16, in the case of forming the first source/drain region 22 included in the first transistor by means of source-drain epitaxy, the first isolation material 182 used for manufacturing the second isolation dielectric wall may define a formation space of the first source/drain region 22 together with the first isolation dielectric wall 181, which is beneficial to make the longitudinal cross-sectional shape of the first source/drain region 22 formed therebetween rectangular. As shown in fig. 15 and 16, the rectangular source/drain regions have a larger longitudinal cross-sectional area than the diamond-shaped source/drain regions, and thus the presence of the second isolation dielectric wall is beneficial for reducing the resistance of the first source/drain region 22, all other things being equal. The material of the second isolation dielectric wall may refer to the material of the first isolation dielectric wall 181, which is not described herein again.
In one example, as shown in fig. 31, the semiconductor device further includes a third isolation dielectric wall 1831. The third insulating dielectric wall 1831 is formed at a side of the second source/drain region 23 included in the second transistor facing away from the first insulating dielectric wall 181. Specifically, the beneficial effects in this case can be analyzed by referring to the beneficial effects of the second separating medium wall 1821, which is not described herein again. In addition, the material of the third insulating dielectric wall 1831 may also refer to the material of the first insulating dielectric wall 181 described above.
As shown in fig. 32, an embodiment of the present invention provides a method of manufacturing a semiconductor device. The manufacturing process will be described below based on the perspective or sectional views of the operations shown in fig. 2 to 31. Specifically, the manufacturing method of the semiconductor device comprises the following steps:
first, a semiconductor substrate is provided. The semiconductor base comprises a semiconductor substrate and a first dielectric layer positioned on the semiconductor substrate. For information such as the specific structure and material of the semiconductor substrate, reference may be made to the foregoing description, and further description is omitted here.
In practical applications, after providing the semiconductor substrate and before performing subsequent operations, the method for manufacturing a semiconductor device may further include:
as shown in fig. 2 and 3, a first fin structure 12 is formed on a semiconductor substrate 11.
Specifically, the first fin structure is a preformed structure for forming the first isolation dielectric wall. The first isolation dielectric wall is formed at the position where the first fin-shaped structure is removed, so that the appearance of the first fin-shaped structure and the forming position of the first fin-shaped structure on the semiconductor substrate can be determined according to the appearance and the forming position of the first isolation dielectric wall. In addition, the material of the first fin-shaped structure may be a semiconductor material such as silicon, silicon germanium, or a iii-v semiconductor material, so as to facilitate the subsequent formation of the first semiconductor layer and the second semiconductor layer by taking the first fin-shaped structure as a seed layer and by epitaxial growth or the like.
It is understood that the process of forming the first fin structure may be different according to the semiconductor substrate structure. For example: as shown in fig. 2, when the semiconductor base 11 is a silicon-on-insulator substrate, a germanium-on-insulator substrate, a silicon-on-germanium-on-insulator substrate, or the like, the semiconductor layer on the first dielectric layer 112 may be directly etched by photolithography and etching, so as to form the first fin structure 12. Alternatively, a semiconductor material with a certain thickness may be formed on the semiconductor substrate 11, and then the semiconductor layer and the semiconductor material on the first dielectric layer 112 may be etched through photolithography and etching processes, so as to form the first fin structure 12.
Another example is: as shown in fig. 3, in the case that the first dielectric layer 112 included in the semiconductor base 11 is a shallow trench isolation, the first fin structure 12 may be formed by directly etching the semiconductor substrate 111 by using photolithography and etching processes. A first dielectric layer 112 may be formed on the exposed portion of the semiconductor substrate 111 outside the first fin structure 12 by using chemical vapor deposition and etching processes. Alternatively, a semiconductor material may be formed over the semiconductor substrate 111 by a process such as epitaxial growth. The semiconductor material is then etched at least using photolithography and etching processes to form the first fin structure 12. Finally, the first dielectric layer 112 is formed in the above manner, so that the first fin structure 12 is formed on the semiconductor substrate 11.
As shown in fig. 4, a first semiconductor layer 13 is formed to cover one side of the first fin structure 12 in the width direction, and a second semiconductor layer 14 is formed to cover the other side of the first fin structure 12 in the width direction. In a direction parallel to the width of the first fin structure 12, the first semiconductor layer 13 includes at least two stacked layers 15, and the second semiconductor layer 14 includes at least one stacked layer 15. Each stack layer 15 includes a first material layer 151, and a second material layer 152 formed on a side of the first material layer 151 facing away from the first fin structure 12. The first material layer 151 and the second material layer 152 are different in material.
Specifically, each of the second material layers included in the first semiconductor layer is a film layer for forming a corresponding first channel portion included in the first channel region, so that the number of stacked layers included in the first semiconductor layer is equal to the number of first channel portions included in the first channel region. Information such as a material and specification of the second material layer included in the first semiconductor layer may be determined according to information such as a material and specification of each of the first channel portions included in the first channel region. In addition, the material of the first material layer included in the stack may be any semiconductor material different from the material of the second material layer. For example: in the case where the material of the second material layer is Si, the material of the first material layer may be Si 0.5 Ge 0.5 。
For the second semiconductor layer, in the case that the materials of the first channel region and the second channel region are the same, the second material layer included in the second semiconductor layer is a film layer for forming the corresponding second channel portion included in the second channel region, and thus the number of layers included in the second semiconductor layer is equal to the number of second channel portions included in the second channel region. Information such as a material and specification of the second material layer included in the second semiconductor layer may be determined according to information such as a material and specification of each second channel portion included in the second channel region.
In a case where the materials of the first channel region and the second channel region are different, the first material layer included in the second semiconductor layer is a film layer for forming the corresponding second channel portion included in the second channel region, and thus the number of stacked layers included in the second semiconductor layer is equal to the number of second channel portions included in the second channel region. Information such as a material and a specification of the first material layer included in the second semiconductor layer may be determined according to information such as a material and a specification of each second channel portion included in the second channel region. In this case, as shown in fig. 5, after the first fin structure 12 is formed and before the second semiconductor layer 14 is formed, the sacrificial layer 16 needs to be formed so as to cover the other side of the first fin structure 12 in the width direction. The subsequent removal of the sacrificial layer 16 may form a space between the second channel region and the first isolation dielectric wall, so that the thickness of the sacrificial layer 16 may be determined according to the specification of the second gate stack structure. In addition, the material of the sacrificial layer 16 may be any semiconductor material different from the material of the first material layer 151. The material of the sacrificial layer 16 may be the same as or different from the material of the second material layer 152.
In practical applications, the first semiconductor layer and the second semiconductor layer may be formed simultaneously. For example: the first semiconductor material layer and the second semiconductor material layer for manufacturing the first semiconductor layer and the second semiconductor layer may be formed simultaneously by using epitaxial growth or the like. The first layer of semiconductor material and the second layer of semiconductor material may then be planarized using a chemical mechanical polishing process or the like to expose tops of the first fin structures. Accordingly, the remaining portion of the first layer of semiconductor material forms a first semiconductor layer and the remaining portion of the second layer of semiconductor material forms a second semiconductor layer.
Alternatively, the first semiconductor layer and the second semiconductor layer may be formed in different operation steps under the mask action of the corresponding mask layers. For example: a first mask layer may be formed to cover one side of the first fin structure in the width direction. Then, the exposed part of the first fin-shaped structure is used as a seed layer, and one of the first semiconductor layer and the second semiconductor layer is formed by adopting the process. Then, the first mask layer is removed, and a second mask layer covering the first semiconductor layer or the second semiconductor layer is formed. And under the mask action of the second mask layer, adopting the process to form the other one of the first semiconductor layer and the second semiconductor layer, and finally removing the second mask layer.
As shown in fig. 6, the first fin structure is removed to obtain an isolation region 17 between the first semiconductor layer 13 and the second semiconductor layer 14.
In an actual application process, a dry etching process or a wet etching process may be adopted, and the first fin-shaped structure is selectively removed by an etchant having an etching effect only on the first fin-shaped structure, so as to obtain an isolation region.
As shown in fig. 8, after removing the first fin structure, a first isolation dielectric wall 181 is formed on the first dielectric layer 112. Specifically, the step of forming the first separating dielectric wall 181 on the first dielectric layer 112 includes the steps of: a first insulating dielectric wall 181 is formed in the insulating region.
In practical application, as shown in fig. 7, the insulating dielectric material 18 used for manufacturing at least the first insulating dielectric wall can be formed by a chemical vapor deposition process. Then, as shown in fig. 8 and 9, a dry etching process or a wet etching process may be used to remove the excess isolation dielectric material. Specifically, the portion of the isolation dielectric material that needs to be removed may be determined according to the specific structure of the semiconductor device to be fabricated.
For example: in the case where the semiconductor device to be manufactured includes only the first separating dielectric wall 181, and does not include the second separating dielectric wall and the third separating dielectric wall, as shown in fig. 8, it is necessary to remove the portion of the separating dielectric material located outside the separation region. At this time, as shown in fig. 8, the first semiconductor layer 13, the second semiconductor layer 14 and the first isolation dielectric wall 181 constitute the second fin structure 19. Along the width direction of the second fin structure 19, the second fin structure 19 includes a first region 191, a second region 192, and a third region 193 located between the first region 191 and the second region 192.
Another example is: in case the semiconductor device to be manufactured comprises only the first and second separating dielectric walls, it is necessary to remove the portions of the separating dielectric material covering the top of the first semiconductor layer, the second semiconductor layer and the separating region, and the portions covering the sidewalls of the second semiconductor layer facing away from the separating region.
For another example: in case the semiconductor device to be manufactured comprises only the first and third separating dielectric walls, it is necessary to remove the portions of the separating dielectric material covering the top of the first semiconductor layer, the second semiconductor layer and the separating region, and the portions covering the sidewalls of the first semiconductor layer facing away from the separating region.
For another example: as shown in fig. 9, in the case where the semiconductor device to be manufactured includes the first insulating dielectric wall 181, the second insulating dielectric wall, and the third insulating dielectric wall, only the portions of the insulating dielectric material covering the top of the first semiconductor layer 13, the second semiconductor layer 14, and the insulating region need to be removed. At this time, the portion of the isolation dielectric material remaining on the side of the first semiconductor layer 13 away from the first isolation dielectric wall 181 is the first isolation material 182. The portion of the isolation dielectric material remaining on the side of the second semiconductor layer 14 facing away from the first isolation dielectric wall 181 is the second isolation material 183.
As shown in fig. 29 to 31, after the first insulating dielectric wall 181 is formed, a first transistor and a second transistor are formed on the first dielectric layer 112. The first transistor is located on one side of the first insulating dielectric wall 181 in the width direction. The first transistor includes a first channel region 25 spaced apart from the first insulating dielectric wall 181 and having at least two first channel portions 251. At least two first channel portions 251 are spaced apart in a direction parallel to the width direction of the first separating dielectric wall 181. Each of the first channel portions 251 has a gap with the first dielectric layer 112, and the first transistor includes a first gate stack structure 27 surrounding an outer circumference of each of the first channel portions 251. The second transistor is located on a side of the first insulating dielectric wall 181 facing away from the first transistor. The second transistor comprises a second channel region 26 spaced apart from the first insulating dielectric wall 181. The second transistor is of opposite conductivity type to the first transistor.
Specifically, the information of the conductivity type, the structure, the material, and the like of the first transistor and the second transistor can be referred to in the foregoing, and the details are not repeated herein. In addition, the manufacturing sequence of the first transistor and the second transistor may be set according to actual requirements, and is not particularly limited herein. For example: one of the first transistor and the second transistor may be manufactured first under the mask action of the respective mask layer and then the other. Another example is: the first transistor and the second transistor may be formed at the same time.
In practical applications, a first gate stack structure included in the first transistor and a second gate stack structure included in the second transistor are usually formed by a replacement gate process, so as to improve the formation quality of the manufactured first gate stack structure and the manufactured second gate stack structure. In this case, after forming the first isolation dielectric wall on the first dielectric layer and before forming the first transistor and the second transistor on the first dielectric layer, as shown in fig. 10, a sacrificial gate 20 may be formed to cross over the third region included in the second fin-shaped structure 19 by using a chemical vapor deposition and etching process. The material of the sacrificial gate 20 may be polysilicon or the like to facilitate material removal.
It should be noted that, as shown in fig. 11, if the manufactured semiconductor device further includes a second isolation dielectric wall and/or a third isolation dielectric wall, the sacrificial gate 20 also spans a portion of the first isolation material and/or the second isolation material corresponding to the third region.
For example, as shown in fig. 12, after the sacrificial gate 20 is formed, processes such as chemical vapor deposition and etching may be used to form gate spacers 21 at least located at two sides of the sacrificial gate 20 along the length direction, so as to isolate the first gate stack structure and the second gate stack structure formed subsequently from other conductive structures, thereby improving electrical characteristics of the semiconductor device. The length direction of the sacrificial gate 20 is parallel to the length direction of the first isolation dielectric wall. The thickness of the gate sidewall 21 may be set according to actual requirements, and is not specifically limited herein. The gate sidewall spacers 21 may be made of an insulating material such as silicon oxide or silicon nitride.
In an actual application process, after the sacrificial gate is formed and before subsequent operations are performed, a portion of the first semiconductor layer located in the first region and the second region may be processed to form a first source/drain region included in the first transistor; and processing a portion of the second semiconductor layer located in the first region and the second region to form a second source/drain region included in the second transistor. Specifically, the formation sequence and the formation process of the first source/drain region and the second source/drain region may be set according to actual requirements, and are not specifically limited herein. For example: the first source/drain region may be formed first and then the second source/drain region may be formed under the mask action of the corresponding mask layer. Alternatively, the second source/drain region may be formed first and then the first source/drain region may be formed under the mask action of the corresponding mask layer.
The formation process of the first source/drain region and the second source/drain region is divided into at least the following two cases according to the difference of the formation processes of the first source/drain region and the second source/drain region:
the first method comprises the following steps: and forming a first source/drain region and a second source/drain region by adopting a source-drain epitaxial mode. In this case, as shown in fig. 13 and 14, at least under the mask effect of the sacrificial gate 20, a wet etching process or a dry etching process may be used to simultaneously remove the portions of the first semiconductor layer in the first region and the second region and the portions of the second semiconductor layer in the first region and the second region. Alternatively, portions of one of the first semiconductor layer and the second semiconductor layer in the first region and the second region may be removed first, and after the corresponding source/drain regions are formed, portions of the other one in the first region and the second region may be removed.
Taking an example that the portions of the first semiconductor layer located in the first region and the second region and the portions of the second semiconductor layer located in the first region and the second region are removed at the same time, and the first source/drain region is formed first, as shown in fig. 13 and 14, after the removing operation, sidewalls of the portions of the first semiconductor layer and the second semiconductor layer located in the third region 193 are exposed. At this time, a first mask layer at least covering the sidewalls of the third region 193 of the second semiconductor layer may be formed by photolithography and etching. And then, under the mask action of the first mask layer, by using the part of the first semiconductor layer, which is located in the third region 193, as a seed layer, and by adopting processes such as epitaxial growth and the like, forming first source/drain regions on two sides of the remaining part of the first semiconductor layer along the length direction. And then, removing the first mask layer, and forming a second mask layer covering the first source/drain region. And then under the mask action of the second mask layer, taking the part of the second semiconductor layer, which is positioned in the third area, as a seed layer, and forming second source/drain regions on two sides of the rest part of the second semiconductor layer along the length direction by adopting the processes of epitaxial growth and the like. Finally, as shown in fig. 15 and 16, the second mask layer is removed.
Note that, as described above, after the first semiconductor layer is formed to cover one side of the first fin structure in the width direction, as shown in fig. 9, the first isolation material 182 is formed to cover one side of the first semiconductor layer 13 away from the first fin structure. In this case, as shown in fig. 16, the first source/drain regions 22 may be formed between the first isolation material 182 and the first isolation dielectric wall 181 and on both sides of the third region of the first semiconductor layer in the above manner, and the first isolation material 182 and the first isolation dielectric wall 181 may jointly limit the formation space of the first source/drain regions 22, which is favorable for forming the first source/drain regions 22 with a rectangular longitudinal cross-section.
In addition, as for the second source-drain regions, as shown in fig. 15, the second source/drain regions 23 may be formed as described above. Alternatively, as described above, after forming the second semiconductor layer covering the other side of the first fin structure in the width direction, as shown in fig. 9, a second isolation material 183 is formed covering a side of the second semiconductor layer 14 facing away from the first fin structure. In this case, as shown in fig. 16, after removing portions of the second semiconductor layer located in the first and second regions, the second source/drain regions 23 included in the second transistor may be formed between the second isolation material 183 and the first isolation dielectric walls 181 and on both sides of the second semiconductor layer located in the third region in the above-described manner.
And the second method comprises the following steps: and forming a first source/drain region and a second source/drain region by adopting an ion implantation mode. In this case, by taking the first source/drain region as an example, after forming the sacrificial gate (or the sacrificial gate and the gate sidewall) crossing over the third region included in the second fin-shaped structure, a first mask layer covering the second semiconductor layer on the first region and the second region may be formed by using processes such as photolithography and etching. And then, under the mask action of the first mask layer, processing the parts of the first semiconductor layer, which are positioned in the first area and the second area, by adopting an ion implantation process to form a first source/drain area. And then removing the first mask layer, forming a second mask layer covering the first source/drain region, and processing the parts of the second semiconductor layer, which are positioned in the first region and the second region, by adopting an ion implantation process under the mask action of the second mask layer to form a second source/drain region. And finally removing the second mask layer.
It is to be understood that, in the above manner, after the sacrificial gate is formed to cross over the third region included in the second fin-shaped structure, an ion implantation process is performed to process the portion of the second semiconductor layer located in the first region and the second region, so as to form the second source/drain region, and then the first source/drain region is formed.
In addition, the first source/drain region and the second source/drain region may be formed by a source/drain epitaxy method or an ion implantation method. One of the first source/drain region and the second source/drain region may be formed by source/drain epitaxy, and the other may be formed by ion implantation.
As shown in fig. 17, a second dielectric layer 24 may be formed overlying the first dielectric layer 112 by chemical vapor deposition and chemical mechanical polishing. Under the condition that the first gate stack structure and the second gate stack structure are formed by adopting a gate replacement process, the first source/drain region and the second source/drain region can be protected from being affected by subsequent operations such as removing the sacrificial gate 20 by the second dielectric layer 24, and the yield of the semiconductor device is improved. Specifically, the top of the second dielectric layer 24 is flush with the top of the sacrificial gate 20. The material of the second dielectric layer may be any insulating material different from the material of the first dielectric layer 112 to prevent the second dielectric layer 24 from being affected when the etch back process is subsequently performed on at least the portion of the first dielectric layer 112 under the first transistor. For example: in the case where the material of the first dielectric layer 112 is silicon oxide, the material of the second dielectric layer 24 may be silicon nitride.
As shown in fig. 18, a wet etching process or a dry etching process may be used to remove the sacrificial gate under the mask effect of the second dielectric layer.
It is understood that after the sacrificial gate is removed, the portions of the first semiconductor layer and the second semiconductor layer located in the third region are exposed. At this time, the formation processes of the first channel region and the second channel region may be determined according to the materials of the first channel region and the second channel region, and the practical application scenario.
In one example, forming the first transistor on the first dielectric layer may include: after removing the sacrificial gate, as shown in fig. 20, 21 and 25, a portion of the first material layer 151 included in the first semiconductor layer, which is located in the third region, is selectively removed. As shown in fig. 27 and 28, the portion of the first dielectric layer 112 on the side of the first isolation dielectric wall 181 close to the first semiconductor layer is etched back, so that the second material layer included in the first semiconductor layer forms a corresponding first channel portion 251. As shown in fig. 29 to 31, a first gate stack structure 27 is formed around the outer circumference of each first channel portion 251.
In an actual application process, as shown in fig. 20, in the case that the materials of the first channel region and the second channel region are the same, a wet etching process, a dry etching process, or the like may be adopted to selectively remove the first material layer 151 included in the first semiconductor layer and the first semiconductor layer 13 included in the second semiconductor layer at the same time. Alternatively, the first material layer 151 included in the first semiconductor layer and the first material layer 151 included in the second semiconductor layer may be selectively removed in different operation steps.
Alternatively, as shown in fig. 21, in the case that the materials of the first channel region and the second channel region are different, the first material layer included in the first semiconductor layer may be selectively removed by using the above-mentioned process under the mask action of the corresponding mask layer. Then, as shown in fig. 22, the second material layer included in the sacrificial layer and the second semiconductor layer is selectively removed under the mask action of the corresponding mask layer. Finally, as shown in fig. 23, the corresponding mask layer is removed.
Alternatively, in the case where the materials of the first channel region and the second channel region are different from each other, as shown in fig. 24, the second material layer included in the sacrificial layer and the second semiconductor layer may be selectively removed first under the mask action of the corresponding mask layer. Then, as shown in fig. 25, the first material layer included in the first semiconductor layer is selectively removed under the mask action of the corresponding mask layer. And finally, removing the corresponding mask layer.
After at least the space between the adjacent first channel portions, the space between the first channel region and the first insulating dielectric wall, and the space between the second channel region and the first insulating dielectric wall are formed in the manner as described above, the formation processes of the first gate stack structure and the second gate stack structure may be determined according to the device types of the first transistor and the second transistor.
Specifically, since the first transistor is a gate-all-around transistor, after the first channel region is formed, as shown in fig. 26, under the mask action of the corresponding mask layer, wet etching or dry etching and other processes may be used to perform etching back on the portion of the first dielectric layer 112 on the side of the first isolation dielectric wall 181 close to the first semiconductor layer, so as to form a gap between the first dielectric layer 112 and the second material layer included in the first semiconductor layer, so that the second material layer included in the first semiconductor layer forms the corresponding first channel portion 251.
In addition, when the first transistor is a fin field effect transistor, as shown in fig. 20, in the case where the materials of the first channel region and the second channel region are the same, the second channel region may be formed of the second material layer included in the second semiconductor layer after the selective removal operation. As shown in fig. 22 and 24, in the case where the materials of the first channel region and the second channel region are different, the first material layer 151 included in the second semiconductor layer may be formed into the second channel region after the above selective removal operation.
And when the first transistor is a gate-all-around transistor, the step of forming the second channel region further comprises the steps of: as shown in fig. 28, the etching back process is performed on the portion of the first dielectric layer 112 on the side of the first isolation dielectric wall 181 close to the second semiconductor layer to form a gap between the first dielectric layer 112 and the second channel region 26.
It should be noted that, as described above, if the first isolation material is formed before the first source/drain region and the second source/drain region are formed, the sacrificial gate is removed and before the first channel region is formed; or after the first channel region is formed and before the first gate stack structure is formed, the method for manufacturing the semiconductor device further comprises the steps of: as shown in fig. 20 to fig. 31, a wet etching process or the like is used to remove the exposed portion of the first isolation material outside the second dielectric layer 24, so that the remaining portion of the first isolation material forms a second isolation dielectric wall 1821.
Accordingly, as previously described, if the second isolation material is formed before the first and second source/drain regions are formed, after the sacrificial gate is removed, and before the second channel region is formed; or after the second channel region is formed and before the second gate stack structure is formed, the method for manufacturing the semiconductor device further comprises the steps of: as shown in fig. 20 to fig. 31, a wet etching process or the like is used to remove the portion of the second isolation material exposed outside the second dielectric layer 24, so that the remaining portion of the second isolation material forms a third isolation dielectric wall 1831.
Finally, as shown in fig. 29 and 30, a first gate stack structure 27 may be formed around the outer periphery of each first channel portion 251 using an atomic layer deposition or the like. The first gate stack structure 27 may be formed in sequence after the first channel region 25 and the second channel region 26 are formed. Alternatively, the first channel region 25 may be formed after the first channel region is formed but before the second channel region 26 is formed under the mask action of the corresponding mask layer. The material of the first gate stack structure 27 can be referred to above.
As for the second gate stack structure, a process such as atomic layer deposition may be employed to form the second gate stack structure at least at the periphery of the second channel region. The second gate stack structure may be formed in sequence after the first channel region and the second channel region are formed. Alternatively, the second channel region may be formed after the second channel region is formed but before the first channel region is formed under the mask action of the corresponding mask layer. Materials of the second gate stack structure can be referred to above.
It should be noted that the first gate stack structure and the second gate stack structure may be formed in various ways, and how to form the first gate stack structure and the second gate stack structure is not a main feature of the present invention, so that only a brief description thereof will be provided in this specification so that a person having ordinary skill in the art can easily implement the present invention. It is fully contemplated by one of ordinary skill in the art that the above-described structures may be otherwise made.
Compared with the prior art, the beneficial effects of the manufacturing method of the semiconductor device provided by the embodiment of the invention can be analyzed by referring to the beneficial effects of the semiconductor device provided by the embodiment of the invention, and details are not repeated here.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.
Claims (18)
1. A semiconductor device, comprising:
the semiconductor substrate comprises a semiconductor substrate and a first dielectric layer positioned on the semiconductor substrate;
the first isolation dielectric wall is formed on the first dielectric layer;
the first transistor is formed on the first dielectric layer and is positioned on one side of the first isolation dielectric wall along the width direction; the first transistor comprises a first channel region and at least two first channel parts, wherein the first channel region and the first isolation dielectric wall are arranged at intervals; at least two first channel parts are distributed at intervals along the width direction parallel to the first isolation medium wall; a gap is reserved between each first channel part and the first dielectric layer, and the first transistor comprises a first gate stack structure which is surrounded on the periphery of each first channel part;
the second transistor is formed on the first dielectric layer and is positioned on one side, away from the first transistor, of the first isolation dielectric wall; the second transistor comprises a second channel region which is arranged at intervals with the first isolation medium wall; the second transistor is of opposite conductivity type to the first transistor.
2. The semiconductor device according to claim 1, wherein at least two of the first channel portions are the same in material; or the like, or a combination thereof,
at least one of the first channel portions is of a different material than the remaining first channel portions.
3. The semiconductor device of claim 1, wherein, in a case where the second transistor is a fin field effect transistor, the second channel region comprises at least one second channel portion formed on the first dielectric layer;
a second gate stack structure included in the second transistor is formed on a top of each of the second channel portions and on both sides in a width direction; the width direction of the second channel part is parallel to the width direction of the first isolation medium wall.
4. The semiconductor device according to claim 1, wherein in a case where the second transistor is a gate-all-around transistor, the second channel region includes at least one second channel portion formed over and spaced apart from the first dielectric layer;
the second transistor includes a second gate stack structure around an outer circumference of each of the second channel portions.
5. The semiconductor device according to claim 3 or 4, wherein in a case where the second channel region includes at least two second channel portions, the at least two second channel portions are spaced apart in a direction parallel to a width direction of the first dielectric isolation wall.
6. The semiconductor device according to any one of claims 1 to 4, wherein materials of the first channel region and the second channel region are different.
7. The semiconductor device according to any one of claims 1 to 4, wherein a crystal orientation of the first channel region is a [110] crystal orientation; and/or the presence of a gas in the atmosphere,
the crystal orientation of the second channel region is a [110] crystal orientation.
8. The semiconductor device according to any one of claims 1 to 4, further comprising a second insulating dielectric wall formed on a side of the first source/drain region included in the first transistor, which is away from the first insulating dielectric wall; and/or the presence of a gas in the gas,
the semiconductor device further comprises a third isolation dielectric wall formed at a side of the second source/drain region included in the second transistor facing away from the first isolation dielectric wall.
9. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate; the semiconductor base comprises a semiconductor substrate and a first dielectric layer positioned on the semiconductor substrate;
forming a first isolation dielectric wall on the first dielectric layer;
forming a first transistor and a second transistor on the first dielectric layer; the first transistor is positioned on one side of the first isolation dielectric wall along the width direction; the first transistor comprises a first channel region and at least two first channel parts, wherein the first channel region and the first isolation dielectric wall are arranged at intervals; at least two first channel parts are distributed at intervals along the width direction parallel to the first isolation medium wall; a gap is reserved between each first channel part and the first dielectric layer, and the first transistor comprises a first gate stack structure which is surrounded on the periphery of each first channel part; the second transistor is positioned on one side, away from the first transistor, of the first isolation dielectric wall; the second transistor comprises a second channel region which is arranged at intervals with the first isolation medium wall; the second transistor is of opposite conductivity type to the first transistor.
10. The method of claim 9, wherein after providing a semiconductor substrate and before forming the first isolation dielectric wall on the first dielectric layer, the method further comprises:
forming a first fin structure on the semiconductor substrate;
forming a first semiconductor layer covering one side of the first fin structure in a width direction and forming a second semiconductor layer covering the other side of the first fin structure in the width direction; in a width direction parallel to the first fin structure, the first semiconductor layer includes at least two stacked layers, and the second semiconductor layer includes at least one stacked layer; each lamination layer comprises a first material layer and a second material layer formed on one side of the first material layer, which faces away from the first fin-shaped structure; the first material layer and the second material layer are different in material;
removing the first fin structure to obtain an isolation region between the first semiconductor layer and the second semiconductor layer;
the forming a first isolation dielectric wall on the first dielectric layer comprises: and forming the first isolation dielectric wall in the isolation region.
11. The method for manufacturing a semiconductor device according to claim 10, wherein the first semiconductor layer, the second semiconductor layer, and the first insulating dielectric wall constitute a second fin structure; the second fin structure includes a first region, a second region, and a third region between the first region and the second region along a width direction of the second fin structure;
after the first isolation dielectric wall is formed on the first dielectric layer and before the first transistor and the second transistor are formed on the first dielectric layer, the method for manufacturing the semiconductor device further comprises the following steps:
forming a sacrificial gate across the third region included in the second fin structure;
forming a second dielectric layer covering the first dielectric layer; the top of the second dielectric layer is flush with the top of the sacrificial gate;
and removing the sacrificial gate.
12. The method of manufacturing the semiconductor device according to claim 11, wherein the forming the first transistor over the first dielectric layer comprises:
selectively removing a part of the first material layer included in the first semiconductor layer, wherein the part is positioned in the third area;
carrying out back-etching treatment on the part, close to the first semiconductor layer, of the first dielectric layer, of the first isolation dielectric wall, so that a second material layer included in the first semiconductor layer forms a corresponding first channel part;
forming the first gate stack structure around the outer circumference of each of the first channel parts.
13. The method according to claim 11, wherein forming the second transistor over the first dielectric layer with the same material for the first channel region and the second channel region comprises:
selectively removing a portion of the first material layer included in the second semiconductor layer, the portion being located in the third region; and the second material layer included in the second semiconductor layer forms the second channel region.
14. The method for manufacturing a semiconductor device according to claim 11, wherein in the case where materials of the first channel region and the second channel region are different,
after the forming of the first fin structure on the semiconductor substrate and before the forming of the second semiconductor layer covering the other side of the first fin structure in the width direction, the method for manufacturing the semiconductor device further comprises: forming a sacrificial layer covering the other side of the first fin-shaped structure along the width direction;
forming the second transistor on the first dielectric layer includes: selectively removing a part of the sacrificial layer corresponding to the third area and a part of a second material layer included in the second semiconductor layer and located in the third area; and such that the second semiconductor layer comprises the first material layer forming the second channel region.
15. The method for manufacturing a semiconductor device according to claim 13 or 14, wherein in the case where the second transistor is a ring-gate transistor, forming the second channel region includes:
and carrying out back etching treatment on the part of the first dielectric layer, which is positioned on one side of the first isolation dielectric wall close to the second semiconductor layer.
16. The method of manufacturing the semiconductor device according to claim 11, wherein after the forming the first semiconductor layer covering one side of the first fin structure in the width direction and before the forming the first transistor on the first dielectric layer, the method further comprises: forming a first isolation material overlying a side of the first semiconductor layer facing away from the first fin structure;
after forming the sacrificial gate across the third region included in the second fin structure and before forming the second dielectric layer overlying the first dielectric layer, the method for manufacturing a semiconductor device further includes:
removing the parts of the first semiconductor layer, which are positioned in the first area and the second area;
forming a first source/drain region included in the first transistor between the first isolation material and the first isolation dielectric wall and on two sides of the third region of the first semiconductor layer;
after removing the sacrificial gate and before forming a first gate stack structure included in the first transistor, the method for manufacturing the semiconductor device further includes: and removing the part of the first isolation material exposed out of the second dielectric layer, so that the remaining part of the first isolation material forms a second isolation dielectric wall.
17. The method of manufacturing the semiconductor device according to claim 11, wherein after the forming the second semiconductor layer covering the other side of the first fin structure in the width direction and before the forming the second transistor on the first dielectric layer, the method further comprises: forming a second isolation material overlying a side of the second semiconductor layer facing away from the first fin structure;
after forming the sacrificial gate across the third region included in the second fin structure and before forming the second dielectric layer overlying the first dielectric layer, the method of manufacturing a semiconductor device further includes:
removing the part of the second semiconductor layer, which is positioned in the first region and the second region;
forming second source/drain regions included in the second transistor between the second isolation material and the first isolation dielectric wall and on two sides of the third region of the second semiconductor layer;
after removing the sacrificial gate and before forming a second gate stack structure included in the second transistor, the method for manufacturing the semiconductor device further includes: and removing the part of the second isolation material exposed out of the second dielectric layer, so that the rest part of the second isolation material forms a third isolation dielectric wall.
18. The method of manufacturing the semiconductor device of claim 11, wherein after the forming the sacrificial gate across the third region included in the second fin structure and before the forming the second dielectric layer overlying the first dielectric layer, the method further comprises: processing the parts, located in the first area and the second area, of the first semiconductor layer by adopting an ion implantation process to form a first source/drain area included in the first transistor; and/or the presence of a gas in the gas,
after the forming a sacrificial gate crossing over the third region included in the second fin structure and before the forming a second dielectric layer covering the first dielectric layer, the method for manufacturing a semiconductor device further includes: and processing the parts of the second semiconductor layer, which are positioned in the first region and the second region, by adopting an ion implantation process so as to form a second source/drain region included by the second transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211375981.9A CN115662992A (en) | 2022-11-04 | 2022-11-04 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211375981.9A CN115662992A (en) | 2022-11-04 | 2022-11-04 | Semiconductor device and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115662992A true CN115662992A (en) | 2023-01-31 |
Family
ID=84996135
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211375981.9A Pending CN115662992A (en) | 2022-11-04 | 2022-11-04 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115662992A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116504616A (en) * | 2023-06-29 | 2023-07-28 | 北京北方华创微电子装备有限公司 | Method for manufacturing semiconductor device |
-
2022
- 2022-11-04 CN CN202211375981.9A patent/CN115662992A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116504616A (en) * | 2023-06-29 | 2023-07-28 | 北京北方华创微电子装备有限公司 | Method for manufacturing semiconductor device |
| CN116504616B (en) * | 2023-06-29 | 2023-11-14 | 北京北方华创微电子装备有限公司 | Method for manufacturing semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI679751B (en) | Semiconductor storage device, manufacturing method thereof, and electronic device including storage device | |
| CN111463287B (en) | Semiconductor device, method of manufacturing the same, and electronic apparatus including the same | |
| CN113130489A (en) | Method for manufacturing semiconductor device | |
| CN115662992A (en) | Semiconductor device and manufacturing method thereof | |
| CN111710713A (en) | Fin type field effect transistor, manufacturing method thereof and electronic equipment | |
| CN111029407B (en) | Field effect transistor and method of manufacturing the same | |
| CN113506774A (en) | Method for manufacturing semiconductor device | |
| CN113130488B (en) | Semiconductor device and manufacturing method thereof | |
| CN112992899B (en) | Semiconductor device and manufacturing method thereof | |
| CN111710717B (en) | Semiconductor device, manufacturing method thereof and electronic equipment | |
| CN113013164B (en) | Semiconductor device and manufacturing method thereof | |
| CN115548016A (en) | Semiconductor device and manufacturing method thereof | |
| CN113314423B (en) | Method for manufacturing semiconductor device | |
| CN115117147A (en) | Semiconductor device and manufacturing method thereof | |
| CN115692475A (en) | Semiconductor device and manufacturing method thereof | |
| CN113130630B (en) | Method for manufacturing semiconductor device | |
| WO2023065542A1 (en) | Semiconductor structure and fabrication method therefor | |
| CN115732560A (en) | Ring gate transistor and manufacturing method thereof | |
| CN115424933A (en) | Method for manufacturing transistor and semiconductor device | |
| CN115513142A (en) | Method for manufacturing semiconductor device | |
| CN115425080A (en) | Transistor and semiconductor device | |
| CN114975282A (en) | Method for manufacturing semiconductor device | |
| CN115116956A (en) | Method for manufacturing semiconductor device | |
| CN114823668A (en) | Semiconductor device and manufacturing method thereof | |
| CN115036357A (en) | Ring gate transistor and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |