CN111029407B - Field effect transistor and method of manufacturing the same - Google Patents
Field effect transistor and method of manufacturing the same Download PDFInfo
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- CN111029407B CN111029407B CN201911166151.3A CN201911166151A CN111029407B CN 111029407 B CN111029407 B CN 111029407B CN 201911166151 A CN201911166151 A CN 201911166151A CN 111029407 B CN111029407 B CN 111029407B
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- 230000005669 field effect Effects 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000002070 nanowire Substances 0.000 claims abstract description 88
- 239000004065 semiconductor Substances 0.000 claims abstract description 57
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000004020 conductor Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 14
- 238000005229 chemical vapour deposition Methods 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 7
- 230000009286 beneficial effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 50
- 238000005137 deposition process Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 230000008093 supporting effect Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000002633 protecting effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A field effect transistor and a method of manufacturing the same are disclosed. The field effect transistor includes: a semiconductor substrate; a fin extending along a first direction of the surface of the semiconductor substrate; the source region and the drain region are respectively positioned on the semiconductor surfaces at two sides of the fin part; and the gate stack is positioned above the fin part and extends along the second direction of the surface of the semiconductor substrate, wherein the side wall of the fin part is provided with a concave-convex pattern, and the concave-convex pattern is contacted with the gate stack. The side wall of the fin part of the field effect transistor is provided with the concave-convex pattern, and the concave-convex pattern comprises the nanowire with the circular cross section, so that the contact area between the fin part of the transistor and the gate stack is larger when the volume is the same, larger saturation current can be formed, and the transistor is smaller when the volume is the same, thereby being beneficial to reducing the area of a chip.
Description
Technical Field
The present application relates to the field of semiconductor devices, and more particularly, to a field effect transistor and a method for manufacturing the same.
Background
MOSFETs are one of the most common field effect transistors in the semiconductor industry. With the progress of the manufacture, when the distance between the source electrode and the drain electrode is about 22nm, a short channel effect occurs and leakage current is formed. In addition, the control effect of the gate on the channel is reduced due to the smaller contact area between the gate and the channel, resulting in poor switching characteristics, and thus, finFET (Fin Field-Effect Transistor, fin Field effect transistor) is presented. In the conventional transistor structure, a gate for controlling the passage of current can only control the on/off of a circuit at one side of the gate, and belongs to a planar architecture. In the FinFET architecture, the gate is a 3D fork-like structure resembling a fin that controls the switching on and off of the circuit on both sides of the circuit. The design can greatly improve circuit control and reduce leakage current, and can also greatly shorten the gate length of the transistor.
The conventional 2D structure MOSFET is developed into a 3D structure FinFET, so that after the gate length L is reduced to a certain degree, the gate still has a larger contact area with the channel, so that the channel current is better controlled, the saturation current is increased, and the leakage current and dynamic power loss are reduced. But the increase in channel width is not large enough, and a better performance FinFET can be obtained by changing the fin shape to further increase the channel width W.
Disclosure of Invention
In view of the foregoing, an object of the present application is to provide a field effect transistor and a method for manufacturing the same, in which a fin side surface of the field effect transistor is provided with a concave-convex pattern, thereby increasing a contact area between the fin and a gate stack and forming a larger saturation current.
According to an aspect of the present application, there is provided a field effect transistor comprising: a semiconductor substrate; a fin extending along a first direction of the surface of the semiconductor substrate; the source region and the drain region are respectively positioned on the semiconductor surfaces at two sides of the fin part; and the gate stack is positioned above the fin part and extends along the second direction of the surface of the semiconductor substrate, wherein the side wall of the fin part is provided with a concave-convex pattern, and the concave-convex pattern is contacted with the gate stack.
Preferably, the fin portion comprises a plurality of nanowires stacked in the vertical direction, and two adjacent stacked nanowires form a cambered surface contact.
Preferably, the cross-sectional shape of the nanowire comprises a circle.
Preferably, the fin portion includes a plurality of nanowires stacked in a vertical direction, and two adjacent stacked nanowires form a planar contact.
Preferably, the cross-sectional shape of the fin portion includes a shape formed by overlapping and intersecting a plurality of circles.
Preferably, the gate stack includes a gate dielectric layer and a gate conductor, the gate dielectric layer separating the gate conductor and the fin.
Preferably, the gate dielectric layer material is a high-K dielectric oxide.
According to another aspect of the present application, there is provided a method of manufacturing a field effect transistor, comprising: forming a fin portion on a semiconductor substrate along a first direction of the surface of the semiconductor substrate; forming a gate dielectric layer covering the surface of the fin part; forming a gate conductor on the gate dielectric layer along the second direction of the surface of the semiconductor substrate; and forming a source region and a drain region on the semiconductor surface at two sides of the fin part, wherein the side wall of the fin part is provided with a concave-convex pattern, and the concave-convex pattern is contacted with the gate stack.
Preferably, the fin portion comprises a plurality of nanowires stacked in the vertical direction, and two adjacent stacked nanowires form a cambered surface contact.
Preferably, the cross-sectional shape of the nanowire comprises a circle.
Preferably, the fin portion includes a plurality of nanowires stacked in a vertical direction, and two adjacent stacked nanowires form a planar contact.
Preferably, the cross-sectional shape of the fin portion includes a shape formed by overlapping and intersecting a plurality of circles.
Preferably, the fin forming method includes: forming a first nanowire on the semiconductor substrate along a first direction; depositing a first oxide layer on the semiconductor substrate, covering the first nanowire; forming a second nanowire on the first oxide layer along the first direction; depositing a second oxide layer over the first oxide layer, covering the second nanowires; forming a third nanowire on the second oxide layer along the first direction; and depositing a third oxide layer on the second oxide layer to cover the third nanowire, wherein the cross sections of the first nanowire, the second nanowire and the third nanowire are identical in shape and size, and the nanowire is formed by adopting a plasma chemical vapor deposition process.
Preferably, the gate dielectric layer material is a high-K dielectric oxide.
According to the field effect transistor provided by the application, the side part of the fin part is provided with the concave-convex pattern, and particularly, a plurality of cylindrical nanowires stacked in the vertical direction are adopted as the fin part, so that under the condition that the semiconductor structure has the same volume, the field effect transistor can obtain a larger effective channel area and form a larger saturation current; under the condition of obtaining the same saturation current, the application can reduce the size of the device, thereby reducing the volume of the chip.
According to the manufacturing method of the field effect transistor, the oxide layer is deposited in the process of forming the fin part, and has a certain supporting and protecting effect on the fin part, so that the probability of damage to the fin part is reduced, and the yield is improved.
Drawings
The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application with reference to the accompanying drawings, in which:
fig. 1 shows a schematic perspective view of a field effect transistor;
fig. 2 is a schematic perspective view of a field effect transistor according to a first embodiment of the present application;
fig. 3a to 3g are sectional views showing stages of a method of manufacturing a field effect transistor according to an embodiment of the present application;
fig. 4 shows a schematic cross-sectional view of a field effect transistor according to a second embodiment of the present application.
Detailed Description
Various embodiments of the present application will be described in more detail below with reference to the accompanying drawings. The same reference numbers will be used throughout the drawings to refer to the same or like parts. For clarity, the various features of the drawings are not drawn to scale.
The application will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. The semiconductor structure obtained after several steps may be depicted in one figure for simplicity.
It will be understood that when a layer, an area, or a structure of a device is described as being "on" or "over" another layer, another area, it can be referred to as being directly on the other layer, another area, or further layers or areas can be included between the other layer, another area, etc. And if the device is flipped, the one layer, one region, will be "under" or "under" the other layer, another region.
If, for the purposes of describing a situation directly overlying another layer, another region, the expression "directly overlying … …" or "overlying … … and adjoining" will be used herein.
Fig. 1 shows a schematic perspective view of a field effect transistor, which is a fin field effect transistor, and as shown, the fin field effect transistor 100 includes a semiconductor substrate 110, a source region 121, a drain region 122, a fin (channel layer) 123, and a gate conductor 130 and a gate dielectric layer (not shown). The contact surface between the gate conductor 130 and the fin 123 is the upper surface and two side surfaces of the fin 123, so that the channel current can be better controlled, the saturation current can be increased, and the leakage current and the dynamic power loss can be reduced due to the larger contact area of the gate conductor 130 to the channel. However, since the improvement in channel width is not large enough, better performance cannot be obtained.
The inventor of the present application has noted this problem and has proposed a field effect transistor with better performance and its manufacturing method, under the condition that the semiconductor structure has the same volume, a larger effective channel area can be obtained, and a larger saturation current is formed; under the condition of obtaining the same saturation current, the area of the device can be reduced, and the size of the chip is further reduced.
The following describes in further detail the embodiments of the present application with reference to the drawings and examples.
Fig. 2 is a schematic perspective view of a field effect transistor according to an embodiment of the present application, and as shown, a field effect transistor 200 includes: semiconductor substrate 210, source region 221, drain region 222, fin 223, and a gate stack comprising gate dielectric layer 224 and gate conductor 230.
The semiconductor substrate 210 is used to support fins 223, source 221 and drain 222 regions, and the like. The fin 223 extends along a first direction parallel to the surface of the semiconductor substrate 210, the sidewall has a concave-convex pattern for increasing the contact area between the fin 223 and the gate stack, the source 221 and the drain 222 are respectively located on the semiconductor substrate 210 at two sides of the fin 223, the source 221 and the drain 222 realize electric communication through the fin 223, and the gate stack is located on the fin 223 and extends along a second direction of the surface of the semiconductor substrate 210. The fin 223 includes a plurality of nanowires stacked in a vertical direction, two nanowires stacked adjacently are in arc contact, and a cross section of each nanowire is, for example, circular, so that an effective release area between the fin 223 and the gate stack is larger, and a larger saturation current can be formed.
Fig. 4 is a schematic cross-sectional view of a field effect transistor according to a second embodiment of the present application, and the difference between the field effect transistor according to the second embodiment and the field effect transistor according to the first embodiment is that the shape of the fin 323 is different, and the details of the differences are not repeated.
Referring to fig. 4, a portion of the fin 232 in contact with the gate stack has a concave-convex pattern for increasing a contact area of the fin 323 with the gate stack. Specifically, the fin 323 has a cross-sectional shape similar to a shape formed by intersecting a plurality of circles in the vertical direction, and contacts the gate stack contact portion, for example, a cambered surface. In other embodiments, the fin may have other shapes that increase the contact area with the gate stack.
Fig. 3a to 3g show sectional views of stages of a method of manufacturing a field effect transistor according to an embodiment of the present application, for example, sectional views taken along the direction indicated by the AA line and the BB line in fig. 2, of a partial structure of a 3D memory device. Not only a plurality of semiconductors and/or conductive structures but also an interlayer insulating layer that separates the plurality of semiconductors and/or conductive structures from each other are shown in the cross-sectional view.
The method begins with a semiconductor substrate 210, which semiconductor substrate 210 may be silicon oxide, silicon, or silicon-on-insulator (SOI).
In this embodiment, the fin 223 of the field effect transistor 200 is formed to include three nanowires, and in other embodiments, the number of nanowires may be set as desired.
As shown in fig. 3a, first nanowires 2231 are formed on a surface of a semiconductor substrate 210 along a first direction.
In this step, a first nanowire 2231 is deposited on the surface of the semiconductor substrate 210 in a first direction using a plasma chemical vapor deposition (PECVD) method.
In this embodiment, the cross-sectional shape of the first nanowire 2231 is, for example, a circle, and the material is, for example, silicon single crystal.
Further, a first oxide layer 201 is deposited on the surface of the semiconductor substrate 210, as shown in fig. 3 b.
In this step, an oxide is deposited on the surface of the semiconductor substrate 210 using a deposition process, such as physical vapor deposition, chemical vapor deposition, etc., to form the first oxide layer 201, and etching back is performed such that the surface of the first nanowire 2231 is exposed.
In this embodiment, the first oxide layer 201 has a certain supporting effect on the first nanowire 2231 in the subsequent step, and meanwhile, the first oxide layer 201 wraps the first nanowire 2231, so that the damage probability of the first nanowire 2231 is reduced, and the yield of the device is improved.
Further, a second nanowire 2232 and a second oxide layer are formed on the surface of the semiconductor structure, as shown in fig. 3 c.
In this step, a second nanowire 2232 is formed on the surface of the semiconductor structure by a plasma chemical vapor deposition (PECVD) method along a first direction, and the second nanowire 2232 and the first nanowire 2231 are located at the same axis in a vertical direction and have the same radius. Then, a deposition process, such as physical vapor deposition, chemical vapor deposition, etc., is used to deposit an oxide on the surface of the semiconductor structure to form a second oxide layer, and etching back is performed to expose the surface of the second nanowire 2232.
The two deposited oxides are shown overall as oxide layer 201 in fig. 3 c. However, the present application is not limited thereto, and an oxide deposited using a plurality of independent deposition steps may be illustrated as a plurality of oxide layers. In this embodiment, the oxide layer 201 has a certain supporting effect on the first nanowire 2231 and the second nanowire 2232 in the subsequent steps, and meanwhile, the oxide layer 201 wraps the first nanowire 2231 and the second nanowire 2232, so that the damage probability of the first nanowire 2231 and the second nanowire 2232 is reduced, and the yield of the device is improved.
Further, a third nanowire 2233 and a third oxide layer are formed on the surface of the semiconductor structure, as shown in fig. 3 d.
In this step, a third nanowire 2233 is formed on the surface of the semiconductor structure by a plasma chemical vapor deposition (PECVD) method along a first direction, and the third nanowire 2233 and the first nanowire 2231 and the second nanowire 2232 are located at the same axis in a vertical direction and have the same radius. And then depositing oxide on the surface of the semiconductor structure by adopting a deposition process, such as physical vapor deposition, chemical vapor deposition and the like, so as to form a third oxide layer.
In this embodiment, the three deposited oxide is shown in its entirety as oxide layer 201 in fig. 3 d. The oxide layer 201 has a certain supporting effect on the first nanowire 2231, the second nanowire 2232 and the third nanowire 2233 in the subsequent steps, and meanwhile, the oxide layer 201 wraps the first nanowire 2231, the second nanowire 2232 and the third nanowire 2233, so that damage probability of the first nanowire 2231, the second nanowire 2232 and the third nanowire 2233 is reduced, and the yield of devices is improved. In this embodiment, the first nanowire 2231, the second nanowire 2232, and the third nanowire 2233 constitute the fin 223 of the field effect transistor 200.
Further, the oxide layer 201 is removed, and a gate dielectric layer 224 is formed on the surface of the semiconductor structure, as shown in fig. 3 e.
In this step, the oxide layer 201 in the semiconductor structure is removed using an etching process, such as a dry etching process, including an ion milling etching, a plasma etching, a reactive ion etching, a laser ablation, or a wet etching or a gas phase etching, or the like. A layer of high K material is then deposited on the surface of the semiconductor structure by chemical vapor deposition to form gate dielectric layer 224.
In this embodiment, the material of the gate dielectric layer 224 is, for example, an oxide of a high-K dielectric, and the gate dielectric layer 224 covers the surface of the fin for separating the fin from a gate conductor to be formed later.
Further, a gate conductor 230 is deposited in a second direction over the surface of the semiconductor structure, as shown in fig. 3 f.
At this step, polysilicon (Poly Si) is deposited on the surface of the semiconductor structure in a second direction using a deposition process, such as physical vapor deposition, chemical vapor deposition, etc., to form gate conductor 230.
In this embodiment, the gate conductor 230 and the gate dielectric layer 224 are gate stack structures for controlling the channel current in the nanowires, and since the fin portion is formed by a plurality of stacked nanowires, the gate stack structures and the fin portion have a larger contact area, so that the channel current is better controlled, and a larger saturation current can be formed.
Further, source regions 221 and drain regions 222 are formed on both sides of the fin along the second direction of the semiconductor structure, respectively, as shown in fig. 3 g.
In this step, a deposition process, such as physical vapor deposition, chemical vapor deposition, or the like, is used to deposit a conductive material on both sides of the fin along the second direction of the semiconductor structure, forming source region 221 and drain region 222, respectively.
In this embodiment, the source 221 and drain 222 regions are in electrical communication through the fin.
According to the manufacturing method of the field effect transistor, the oxide layer is deposited in the process of forming the fin part, and has a certain supporting and protecting effect on the fin part, so that the probability of damage to the fin part is reduced, and the yield is improved.
According to the field effect transistor provided by the application, the plurality of nanowires stacked in the vertical direction are adopted as the fin parts, and under the condition that the semiconductor structure has the same volume, the field effect transistor can obtain a larger effective channel area to form a larger saturation current; under the condition of obtaining the same saturation current, the application can reduce the size of the device, thereby reducing the volume of the chip.
Embodiments in accordance with the present application, as described above, are not intended to be exhaustive or to limit the application to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and the practical application, to thereby enable others skilled in the art to best utilize the application and various modifications as are suited to the particular use contemplated. The application is limited only by the claims and the full scope and equivalents thereof.
Claims (13)
1. A method of manufacturing a field effect transistor, comprising:
forming a fin portion on a semiconductor substrate along a first direction of the surface of the semiconductor substrate;
forming a gate dielectric layer covering the surface of the fin part;
forming a gate conductor on the gate dielectric layer along the second direction of the surface of the semiconductor substrate;
forming a source region and a drain region on the semiconductor surface at two sides of the fin portion,
wherein the side wall of the fin part is provided with a concave-convex pattern, the concave-convex pattern is contacted with the grid dielectric layer,
the fin forming method comprises the following steps:
forming a first nanowire on the semiconductor substrate along a first direction;
depositing a first oxide layer on the semiconductor substrate, covering the first nanowire;
forming a second nanowire on the first oxide layer along the first direction;
depositing a second oxide layer over the first oxide layer, covering the second nanowires;
forming a third nanowire on the second oxide layer along the first direction;
depositing a third oxide layer over the second oxide layer, covering the third nanowires,
the cross section shapes and the sizes of the first nanowire, the second nanowire and the third nanowire are the same, and the nanowires are formed by adopting a plasma chemical vapor deposition process;
the first nanowire, the second nanowire and the third nanowire are located at the same axis in the vertical direction.
2. The method of manufacturing of claim 1, wherein the fin comprises a plurality of nanowires stacked in a vertical direction, two of the nanowires stacked adjacently forming a cambered surface contact.
3. The manufacturing method of claim 2, wherein the cross-sectional shape of the nanowire comprises a circle.
4. The method of manufacturing of claim 1, wherein the fin comprises a plurality of nanowires stacked in a vertical direction, two of the nanowires stacked adjacently forming a planar contact.
5. The method of manufacturing of claim 4, wherein a cross-sectional shape of the fin comprises a plurality of shapes formed by overlapping and intersecting circles.
6. The method of manufacturing of claim 1, wherein the gate dielectric layer material is a high-K dielectric oxide.
7. A field effect transistor formed using the method of manufacturing of any of claims 1-6, the field effect transistor comprising:
a semiconductor substrate;
a fin extending along a first direction of the surface of the semiconductor substrate;
the source region and the drain region are respectively positioned on the semiconductor surfaces at two sides of the fin part;
a gate stack located over the fin extending in a second direction along the surface of the semiconductor substrate,
the side wall of the fin portion is provided with a concave-convex pattern, and the concave-convex pattern is in contact with the gate stack.
8. The field effect transistor of claim 7, wherein the fin comprises a plurality of nanowires stacked in a vertical direction, two of the nanowires stacked adjacently forming a cambered surface contact.
9. The field effect transistor of claim 8, wherein the cross-sectional shape of the nanowire comprises a circle.
10. The field effect transistor of claim 7, wherein the fin comprises a plurality of nanowires stacked in a vertical direction, two of the nanowires stacked adjacently forming a planar contact.
11. The field effect transistor of claim 10, wherein a cross-sectional shape of the fin comprises a plurality of shapes formed by overlapping and intersecting circles.
12. The field effect transistor of claim 7, wherein the gate stack comprises a gate dielectric layer and a gate conductor, the gate dielectric layer to separate the gate conductor and the fin.
13. The field effect transistor of claim 7, wherein the gate dielectric layer material is a high K dielectric oxide.
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