CN113130488B - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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CN113130488B
CN113130488B CN202110269373.9A CN202110269373A CN113130488B CN 113130488 B CN113130488 B CN 113130488B CN 202110269373 A CN202110269373 A CN 202110269373A CN 113130488 B CN113130488 B CN 113130488B
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layer
transistor
channel
buffer
region
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CN113130488A (en
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李永亮
赵飞
程晓红
马雪丽
王文武
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductors, and aims to simplify the manufacturing process of the semiconductor device and improve the yield and the performance of the semiconductor device under the condition of ensuring that the threshold voltages of a first transistor and a second transistor are different. The semiconductor device includes: the transistor includes a substrate, a buffer layer, a first transistor, and a second transistor. The buffer layer is formed on the substrate. The first transistor is formed on the buffer layer. The second transistor is formed over the first transistor. The second transistor and the first transistor are of different conductivity types. The second transistor and the first transistor are all ring-gate transistors. The second channel region of the second transistor and the first channel region of the first transistor are both made of germanium-silicon, and the content of germanium in the second channel region is different from that in the first channel region. The manufacturing method of the semiconductor device is used for manufacturing the semiconductor device.

Description

Semiconductor device and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.
Background
In a manufacturing process of a practical Complementary Field Effect Transistor (CFET), gate stack structures with different thicknesses or different materials are usually formed on the periphery of a channel region included in an NMOS (N-Metal-Oxide-Semiconductor) Transistor and a PMOS (P-Metal-Oxide-Semiconductor) Transistor included in the CFET device, so that the NMOS Transistor and the PMOS Transistor have different threshold voltages.
However, the method of forming gate stack structures of different thicknesses or different materials at the peripheries of channel regions included in the NMOS transistor and the PMOS transistor to make the NMOS transistor and the PMOS transistor have different threshold voltages causes a reduction in yield of semiconductor devices.
Disclosure of Invention
The invention aims to provide a semiconductor device and a manufacturing method thereof, which are used for simplifying the manufacturing process of the semiconductor device and improving the yield and the performance of the semiconductor device under the condition of ensuring that the threshold voltages of a first transistor and a second transistor are different.
In order to achieve the above object, the present invention provides a semiconductor device comprising: a substrate, a first electrode and a second electrode,
a buffer layer formed on the substrate;
a first transistor formed on the buffer layer;
and a second transistor formed over the first transistor; the second transistor and the first transistor are different in conductivity type; the second transistor and the first transistor are all ring-grid transistors; the second channel region of the second transistor and the first channel region of the first transistor are both made of germanium-silicon, and the content of germanium in the second channel region is different from that in the first channel region.
Compared with the prior art, the semiconductor device provided by the invention has the advantages that the first transistor and the second transistor formed on the first transistor are different in conductivity type. And the first channel region included by the first transistor and the second channel region included by the second transistor are both made of germanium-silicon, and the content of germanium in the second channel region is different from that in the first channel region. Therefore, the channel regions which are made of the germanium-silicon material and have different germanium contents have different carrier mobility and conductivity, so that the first transistor and the second transistor can obtain different threshold voltages under the condition that the first channel region and the second channel region are made of the germanium-silicon material and have different germanium contents. Therefore, in the process of manufacturing the semiconductor device provided by the invention, the first transistor and the second transistor can have different threshold voltages only by forming the first channel region on the buffer layer and forming the second channel region above the first channel region, and gate stack structures with different thicknesses or materials do not need to be formed on the peripheries of the channel regions included in different transistors by means of back etching and multiple depositions, so that the manufacturing process of the semiconductor device can be simplified.
Further, a buffer layer is formed on the substrate. And, a first transistor is formed on the buffer layer. Meanwhile, a second transistor is formed on the first transistor. Based on this, in the process of manufacturing the semiconductor device provided by the present invention, a first channel layer for forming a first channel region, a first sacrificial layer and a second isolation layer for isolation, and a second channel layer for forming a second channel region may be sequentially epitaxially grown on the above buffer layer. Alternatively, a second sacrificial layer for isolation may be formed in addition to the above-described film layer. At this time, the presence of the buffer layer may provide stress to the first channel layer and/or the second channel layer, thereby causing strain to be generated in the first channel region and/or the second channel region formed based on the first channel layer and/or the second channel layer, thereby improving mobility of carriers in the first transistor and/or the second transistor and improving driving performance of the semiconductor device. In addition, in the process of releasing the first channel region and the second channel region in the gate forming region, the buffer layer can isolate the film layers to be etched, namely the first sacrificial layer and the second isolation layer (or the first sacrificial layer, the second isolation layer and the second sacrificial layer), from the substrate, and even if the etching selection between the film layer to be etched and the substrate is low, an etchant for etching the film layer to be etched cannot contact and react with the substrate, so that the appearance of the substrate can meet the requirement of a preset scheme, and the yield and the performance of a semiconductor device can be improved.
The present invention also provides a method of manufacturing a semiconductor device, the method of manufacturing the semiconductor device including:
providing a substrate;
forming a buffer layer on a substrate;
forming a first transistor on the buffer layer and a second transistor on the first transistor; the second transistor and the first transistor are different in conductivity type; the second transistor and the first transistor are all ring-gate transistors; the second channel region of the second transistor and the first channel region of the first transistor are both made of germanium-silicon, and the content of germanium in the second channel region is different from that in the first channel region.
Compared with the prior art, the manufacturing method of the semiconductor device provided by the invention has the same beneficial effects as those of the semiconductor device provided by the technical scheme, and the details are not repeated here.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic structural diagram of a substrate with a buffer material layer, a first stacked layer, a second isolation layer, a semiconductor layer and a silicon protection layer formed thereon according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a fin structure formed in an embodiment of the invention.
Fig. 3 is a schematic structural diagram after forming shallow trench isolation in the embodiment of the present invention.
Fig. 4 isbase:Sub>A sectional view of the structure of fig. 3 taken along the linebase:Sub>A-base:Sub>A.
Fig. 5 is a schematic structural diagram after forming a sacrificial gate and a sidewall spacer in the embodiment of the present invention.
Fig. 6 is a schematic structural diagram of the embodiment of the present invention after removing portions of the silicon protection layer, the second channel layer, the second sacrificial layer, and the second isolation layer located in the first semiconductor region and the second semiconductor region.
FIG. 7 is a schematic structural diagram illustrating formation of a first source/drain region in an embodiment of the present invention;
FIG. 8 is a schematic diagram illustrating a structure after forming a first isolation layer according to an embodiment of the present invention;
FIG. 9 is a schematic structural diagram illustrating a second source/drain region formed in accordance with an embodiment of the present invention;
FIG. 10 isbase:Sub>A cross-sectional view ofbase:Sub>A dielectric layer formed along A-A in an embodiment of the present invention;
FIG. 11 isbase:Sub>A cross-sectional view of the structure along the direction A-A after removing the sacrificial gate and removing the silicon protection layer, the second sacrificial layer, the second isolation layer and the first sacrificial layer from the inner portion of the gate forming region according to the embodiment of the present invention;
fig. 12 isbase:Sub>A structural cross-sectional view along the directionbase:Sub>A-base:Sub>A after formingbase:Sub>A first gate stack structure andbase:Sub>A second gate stack structure in an embodiment of the invention.
Reference numerals: 11 is a substrate, 12 is a buffer material layer, 121 is a buffer layer, 1211 is a first buffer portion, 1212 is a second buffer portion, 13 is a first stacked layer, 131 is a first sacrificial layer, 132 is a first channel layer, 1321 is a first channel region, 14 is a second isolation layer, 15 is a semiconductor layer, 16 is a second stacked layer, 161 is a second channel layer, 1611 is a second channel region, 162 is a second sacrificial layer, 17 is a silicon protection layer, 18 is a fin structure, 181 is a fin portion, 1811 is a first semiconductor region, 1812 is a second semiconductor region, 1813 is a gate forming region, 19 is a shallow trench isolation, 20 is a sacrificial gate, 21 is a sidewall, 22 is a first source/drain region, 23 is a first isolation layer, 24 is a second source/drain region, 25 is a dielectric layer, 26 is a first gate stacked structure, 27 is a second gate stacked structure, 28 is a first transistor, and 29 is a second transistor.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and some details may be omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed. In order to make the technical problems, technical solutions and advantageous effects of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise. The meaning of "a number" is one or more unless specifically limited otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In a manufacturing process of a practical Complementary Field Effect Transistor (CFET), gate stack structures with different thicknesses or different materials are usually formed on the periphery of a channel region included in an NMOS (N-Metal-Oxide-Semiconductor) Transistor and a PMOS (P-Metal-Oxide-Semiconductor) Transistor included in the CFET device, so that the NMOS Transistor and the PMOS Transistor have different threshold voltages.
The following briefly describes the manufacturing process of NMOS transistors and PMOS transistors having different threshold voltages, taking as an example that the PMOS transistor is formed on an NMOS transistor, and each of the NMOS transistor and the PMOS transistor includes a nanowire or a chip: first, a first laminated layer, an isolation layer and a second channel layer are sequentially formed on a substrate along a thickness direction of the substrate. The first stack is located on a substrate. The isolation layer is located between the first stack and the second channel layer. Each of the first stacks includes a first sacrificial layer, and a first channel layer on the first sacrificial layer. The first stack, the isolation layer, the second channel layer, and a portion of the substrate are then etched to form at least one fin structure extending in a first direction on the substrate. And shallow trench isolations are formed between adjacent fin structures. And forming a fin part on the part of each fin structure exposed outside the shallow trench isolation. And then, forming a sacrificial gate extending along the second direction on the periphery of the at least two fin parts, and removing the second channel layer and the isolation layer at the two sides of the sacrificial gate. Wherein the second direction is different from the first direction. Then, a first source/drain region included in the NMOS transistor is formed on the substrate, and a second source/drain region included in the PMOS transistor is formed above the first source/drain region. The first source/drain region and the second source/drain region are electrically insulated. And then removing the sacrificial gate, and removing the isolation layer and the part of the first sacrificial layer positioned in the gate forming region, so that the parts of the first channel layer and the second channel layer positioned in the gate forming region form a nanowire or a sheet. And forming a gate stack structure corresponding to the NMOS transistor on the periphery of the nanowire or chip included in the NMOS transistor and the PMOS transistor. The gate stack structure typically includes a gate dielectric layer, a work function layer, and other metal gate stacks (e.g., a stack of titanium nitride and tungsten). And removing the gate stack structure corresponding to the NMOS transistor formed on the periphery of the nanowire or chip included in the PMOS transistor. And finally, forming a gate stack structure corresponding to the PMOS transistor on the periphery of the nanowire or the chip included by the PMOS transistor, thereby obtaining the NMOS transistor and the PMOS transistor with different threshold voltages by means of back etching and multiple depositions.
As can be seen from the above, the manufacturing process of the semiconductor device is complicated by forming the gate stack structures with different thicknesses or different materials on the peripheries of the channel regions included in the NMOS transistor and the PMOS transistor to make the NMOS transistor and the PMOS transistor have different threshold voltages. In addition, the materials of the substrate, the first sacrificial layer and the isolation layer are all silicon. After the sacrificial gate is removed, in the process of removing the part, located in the gate forming area, of the isolation layer and the first sacrificial layer, the etchant not only has an etching effect on the isolation layer and the first sacrificial layer, but also can etch the part, corresponding to the gate forming area, of the substrate, so that the subsequent operation is not facilitated, and meanwhile, the appearance and performance of the semiconductor device cannot meet the requirements of a preset scheme. Furthermore, NMOS transistors and PMOS transistors often have different threshold voltages by forming gate dielectric layers and/or work function layers of different thicknesses or different materials on the peripheries of their channel regions, which have the same material as the other metal gate stacks. In the manufacturing process, not only the gate dielectric layer and the work function layer corresponding to the NMOS transistor, but also other metal gate stacks are formed on the peripheries of the nanowires or sheets included in the NMOS transistor and the PMOS transistor. And the other metal gate stacks are respectively etched and re-formed in the back etching and subsequent multi-deposition processes, so that the waste of other metal gate stack materials is caused, and the production cost of the semiconductor device is not favorably saved.
Further, as semiconductor technology advances, integrated circuits with higher performance and higher functionality require greater element density, and the size, and space of individual components, between elements, or of individual elements themselves also need to be further reduced. The difficulty of forming gate stack structures of different thicknesses or different materials in a smaller space is large, which results in the reduction of yield and performance of semiconductor devices.
In order to solve the above technical problem, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same. Embodiments of the present invention provide a semiconductor device in which a first transistor is of a different conductivity type than a second transistor formed thereon. And the first channel region included by the first transistor and the second channel region included by the second transistor are both made of germanium-silicon, and the content of germanium in the second channel region is different from that in the first channel region. Therefore, in the process of manufacturing the semiconductor device provided by the invention, the first transistor and the second transistor can have different threshold voltages only by forming the first channel region on the buffer layer and forming the second channel region above the first channel region, and gate stack structures with different thicknesses or materials do not need to be formed on the peripheries of the channel regions included in different transistors by means of back etching and multiple depositions, so that the manufacturing process of the semiconductor device can be simplified. In addition, the first transistor is formed on the buffer layer. Meanwhile, a second transistor is formed on the first transistor. The existence of the buffer layer can generate strain in the first channel region and the second channel region, so that the mobility of carriers in the first transistor and the second transistor is improved, and the driving performance of the semiconductor device is improved.
The embodiment of the invention provides a semiconductor device. As shown in fig. 12, the semiconductor device includes: a substrate 11, a buffer layer 121 formed on the substrate 11, a first transistor 28 formed on the buffer layer 121, and a second transistor 29 formed on the first transistor 28. The second transistor 29 and the first transistor 28 are of different conductivity types. The second transistor 29 and the first transistor 28 are both ring-gate transistors. The second channel region 1611 included in the second transistor 29 and the first channel region 1321 included in the first transistor 28 are both made of silicon germanium, and the content of germanium (the content of germanium appearing here and below is the concentration of germanium) in the second channel region 1611 and the first channel region 1321 is different.
Specifically, the above substrate is any semiconductor substrate that can be applied to the embodiments of the present invention. For example: the substrate may be a silicon substrate or a silicon-on-insulator substrate.
For the buffer layer, the specific structure, thickness and material of the buffer layer may be set according to actual requirements, and are not limited specifically here. Illustratively, the buffer layer may have a thickness of 100nm to 1.5 μm. The buffer layer may be made of Si 1-x Ge x Wherein x is more than or equal to 0.25 and less than or equal to 0.7. In this case, si as described above 1-x Ge x Buffer of materialThe buffer layer can provide corresponding stress for a first channel layer used for forming a first channel region and a second channel layer used for forming a second channel region, and the mobility of carriers in the first channel region and the second channel region is improved, so that the driving performance of the semiconductor device is improved. Specifically, the content of germanium in the buffer layer may be set according to the conductivity types of the first transistor and the second transistor, and the content of germanium in the first channel region and the second channel region. In addition, in some cases, shallow trench isolations for defining active regions are formed on the buffer layer. As for the material contained in the shallow trench isolation, siN and Si can be used 3 N 4 、SiO 2 Or an insulating material such as SiCO.
For the first transistor and the second transistor, the first transistor may be an NMOS transistor or a PMOS transistor in terms of conductivity type. Because the second transistor and the first transistor have different conduction types, when the first transistor is a PMOS transistor, the second transistor is an NMOS transistor. At this time, the NMOS transistor is formed on the PMOS transistor. In another example, when the first transistor is an NMOS transistor, the second transistor is a PMOS transistor. At this time, the PMOS transistor is formed on the NMOS transistor. In terms of structure, as shown in fig. 12, the first transistor 28 may include a first source/drain region 22 and a first gate stack structure 26 in addition to the first channel region 1321. Wherein the first source/drain regions 22 are formed at both sides of the first channel region 1321 in the length direction. The first gate stack structure 26 surrounds the outer circumference of the first channel region 1321. The second transistor 29 may include a second source/drain region 24 and a second gate stack structure 27 in addition to the second channel region 1611. Wherein second source/drain regions 24 are formed at both sides of the second channel region 1611 in the length direction. The second gate stack 27 surrounds the second channel region 1611. The first gate stack structure 26 and the second gate stack structure 27 may have the same material. At this time, after the first channel region 1321 and the second channel region 1611 are obtained, the first gate stack structure 26 may be formed at the outer circumference of the first channel region 1321 while the second gate stack structure 27 is formed at the outer circumference of the second channel region 1611, so as to simplify the manufacturing process of the semiconductor device.
Specifically, the content of germanium in the first channel region and the second channel region may be set according to an actual application scenario, and is not limited specifically here. For example, the channel region of the NMOS transistor may be made of Si 1-y Ge y Wherein y is more than or equal to 0.1 and less than or equal to 0.5. The channel region of the PMOS transistor may be made of Si 1-z Ge z Wherein z is more than or equal to 0.4 and less than 1, and z-y is more than or equal to 0.3. Wherein, when the first transistor is NMOS transistor and the second transistor is PMOS transistor, the first channel region is made of Si 1-y Ge y . The second channel region is made of Si 1-z Ge z . In another example, when the first transistor is a PMOS transistor and the second transistor is an NMOS transistor, the first channel region is made of Si 1-z Ge z . The second channel region is made of Si 1- y Ge y 。
It is worth noting that when the channel region of the PMOS transistor is made of the sige high mobility material, the carrier mobility of the channel region can be improved, thereby improving the performance of the PMOS transistor. However, when a channel region in an NMOS transistor is fabricated using a sige high mobility material, there are problems of poor interface state, high source-drain contact resistance, low solid concentration of N-type impurities, and rapid diffusion. Based on this, in the case where the first transistor is a PMOS transistor and the second transistor is an NMOS transistor, the content of germanium in the first channel region is greater than the content of germanium in the second channel region. Or, in the case that the first transistor is an NMOS transistor and the second transistor is a PMOS transistor, the content of germanium in the first channel region is less than the content of germanium in the second channel region, which may improve the performance of the semiconductor device.
In addition, the minimum vertical distance between the first channel region and the second channel region may be set according to an actual application scenario, and is not specifically limited herein. Illustratively, the minimum vertical distance between the first channel region and the second channel region may be 50nm to 100nm.
For the first source/drain region and the second source/drain region, the material of the first source/drain region and the second source/drain region is a semiconductor material (for example:silicon germanium or germanium, etc.). The first source/drain region and the second source/drain region may be made of the same material or different materials. Specifically, the material of the first source/drain region and the second source/drain region may be set according to an application scenario, and is not specifically limited herein. The first gate stack structure may include a first gate dielectric layer surrounding an outer circumference of the first channel region, and a first metal gate formed on the first gate dielectric layer. The second gate stack structure may include a second gate dielectric layer surrounding an outer circumference of the second channel region, and a second metal gate formed on the second gate dielectric layer. When the first gate stack structure and the second gate stack structure are made of the same material, the first gate dielectric layer is made of the same material as the second gate dielectric layer. The first metal grid and the second metal grid are made of the same material. Specifically, the materials contained in the first gate dielectric layer and the second gate dielectric layer may be both HfO 2 、ZrO 2 、TiO 2 Or Al 2 O 3 And materials with higher dielectric constants. The first metal gate and the second metal gate may be made of conductive materials such as TiN, taN, tiSiN, or the like.
As can be seen from the above, embodiments of the present invention provide a semiconductor device in which a first transistor and a second transistor formed thereon have different conductivity types. And the first channel region included by the first transistor and the second channel region included by the second transistor are both made of germanium-silicon, and the content of germanium in the second channel region is different from that in the first channel region. Therefore, the channel regions which are made of the germanium-silicon material and have different germanium contents have different carrier mobility and conductivity, so that the first transistor and the second transistor can obtain different threshold voltages under the condition that the first channel region and the second channel region are made of the germanium-silicon material and have different germanium contents. Therefore, in the process of manufacturing the semiconductor device provided by the embodiment of the invention, the first transistor and the second transistor can have different threshold voltages only by forming the first channel region on the buffer layer and forming the second channel region above the first channel region, and gate stack structures with different thicknesses or materials do not need to be formed on the peripheries of the channel regions included in different transistors by means of back etching and multiple depositions, so that the manufacturing process of the semiconductor device can be simplified.
Further, a buffer layer is formed on the substrate. Also, a first transistor is formed on the buffer layer, and a second transistor is formed on the first transistor. Based on this, in the process of manufacturing the semiconductor device provided by the embodiment of the present invention, a first channel layer for forming a first channel region, a first sacrificial layer and a second isolation layer for isolation, and a second channel layer for forming a second channel region may be sequentially epitaxially grown on the buffer layer. Alternatively, a second sacrificial layer for isolation may be formed in addition to the above-described film layer. At this time, the presence of the buffer layer may provide stress to the first channel layer and/or the second channel layer, thereby causing strain to be generated in the first channel region and/or the second channel region formed based on the first channel layer and/or the second channel layer, thereby improving mobility of carriers in the first transistor and/or the second transistor and improving driving performance of the semiconductor device. In addition, in the process of releasing the first channel region and the second channel region in the gate forming region, the buffer layer can isolate the film layers to be etched, namely the first sacrificial layer and the second isolation layer (or the first sacrificial layer, the second isolation layer and the second sacrificial layer), from the substrate, and even if the etching selection ratio between the film layer to be etched and the substrate is low, the film layer to be etched and an etching agent for etching cannot contact and react with the substrate, so that the appearance of the substrate can meet the requirement of a preset scheme, and the yield and the performance of a semiconductor device can be improved.
In one example, as shown in fig. 2 and 12, the buffer layer 121 may include a first buffer portion 1211 and a second buffer portion 1212. The first buffer 1211 is covered on the substrate 11. The second buffer portion 1212 is a fin-shaped structure formed on the first buffer portion 1211. The first source/drain region 22 and the first channel region 1321 included in the first transistor 28 are formed on the second buffer portion 1212. It is to be understood that the first transistor 28 and the second transistor 29 are both ring-gate transistors. Based on this, as shown in fig. 11, in the process of manufacturing the first transistor 28 and the second transistor 29 on the buffer layer 121, the presence of the second buffer portion 1212 facilitates removal of the portions of the first sacrificial layer and the second isolation layer (or the first sacrificial layer, the second isolation layer, and the second sacrificial layer) located in the gate formation region in the process of forming the first channel region 1321 and the second channel region 1611, which reduces the difficulty in manufacturing the semiconductor device.
In one example, as shown in fig. 2 and 12, the first channel region 1321 and the second channel region 1611 described above are self-aligned. It is to be understood that, as shown in fig. 1, in the process of manufacturing the semiconductor device provided by the embodiment of the present invention, a first channel layer 132 for forming a first channel region, a first sacrificial layer 131 and a second isolation layer 14 for isolation, and a second channel layer 161 for forming a second channel region may be sequentially epitaxially grown on the buffer material layer 12 (a film layer for forming the buffer layer 121). Alternatively, a second sacrificial layer 162 for isolation may be formed in addition to the above-described film layer. As shown in fig. 2, at least the second channel layer, the second isolation layer, the first channel layer, and the first sacrificial layer (when the second sacrificial layer is formed, the second sacrificial layer is also etched) may be etched from top to bottom through photolithography and etching processes to form the fin-shaped structure 18, thereby achieving self-alignment of the first channel region and the second channel region, making the first channel region and the second channel region have a relatively consistent morphology and specification, and facilitating improvement of the performance of the semiconductor device.
In one example, as shown in fig. 9 and 12, the semiconductor device may further include a first isolation layer 23. A first isolation layer 23 is located between the first source/drain region 22 comprised by the first transistor 28 and the second source/drain region 24 comprised by the second transistor 29 for isolating the first source/drain region 22 from the second source/drain region 24. It should be understood that the presence of the first isolation layer 23 can separate the first source/drain region 22 from the second source/drain region 24 after the second source/drain region 24 is formed above the first source/drain region 22, so as to prevent the first source/drain region 22 from being electrically connected to the second source/drain region 24, which is beneficial to improving the stability of the semiconductor device.
Specifically, the material of the first isolation layer may be an insulating material such as silicon oxide or silicon nitride. The thickness of the first isolation layer may be set according to an actual application scenario, and is not specifically limited herein.
In some cases, the semiconductor device may further include a dielectric layer 25, as shown in fig. 10 to 12. The dielectric layer 25 overlies the first source/drain region 22 and the second source/drain region 24. It should be understood that the presence of the dielectric layer 25 can ensure that the exposing of the sacrificial gate 20 is obtained by using a planarization process and the first source/drain region 22 and the second source/drain region 24 are protected from the removal, cleaning and other processes of the sacrificial gate 20, thereby improving the yield and performance of the semiconductor device. The dielectric layer 25 is made of an insulating material. For example: silicon oxide. The thickness of the dielectric layer 25 may be set according to practical application scenarios, and is not particularly limited herein.
The embodiment of the invention also provides a manufacturing method of the semiconductor device. The manufacturing process will be described below with reference to the perspective or cross-sectional views of the operation shown in fig. 1 to 12. Specifically, the manufacturing method of the semiconductor device comprises the following steps:
first, a substrate is provided. The material of the substrate can be referred to above.
In one example, as shown in FIG. 1, a layer of buffer material 12 is formed overlying a surface of a substrate 11.
Illustratively, a layer of buffer material may be formed on the surface of the substrate by an epitaxial process. The buffer material layer may then be planarized by chemical mechanical polishing, etc. to make the top of the buffer material layer more planar. Therefore, the film layers such as the first laminated layer and the second isolation layer formed on the relatively flat buffer material layer are relatively flat, so that a structure with relatively regular appearance is formed on the basis of the film layers, and the yield of the semiconductor device can be improved. The buffer material layer is a film layer forming the buffer layer, and the material and thickness of the buffer material layer can be set by referring to the material and thickness of the buffer layer. For example: the buffer material layer may be made of Si 1-x Ge x Wherein x is more than or equal to 0.25 and less than or equal to 0.7. The thickness of the buffer material layer may be 100nm to 1.5 μm.
As shown in fig. 1, at least one first stacked layer 13 covering the buffer material layer 12 and a second spacer layer 14 on the at least one first stacked layer 13 are sequentially formed. The first stack 13 includes a first sacrificial layer 131, and a first channel layer 132 on the first sacrificial layer 131. The material of the first channel layer 132 is silicon germanium.
Illustratively, the first stack layer and the second isolation layer may be sequentially formed through an epitaxial process. The first channel layer included in the first stack is a film layer forming the first channel region, so that the content of germanium in the first channel layer and the thickness of the first channel layer may be set with reference to the content of germanium in the first channel region and the thickness of the first channel region described above. The materials of the first sacrificial layer and the second isolation layer need to have a certain etching selection ratio with the materials of the first channel layer respectively, so that the first channel layer is prevented from being influenced by processes such as etching when the parts, located in the grid forming region, of the first sacrificial layer and the second isolation layer are removed in the follow-up process. For example: the first sacrificial layer and the second isolation layer may be made of silicon. In addition, the second spacer determines a minimum vertical distance between the first channel region and the second channel region to be formed subsequently, so that the thickness of the second spacer may be set according to the minimum vertical distance. For example: the thickness of the second isolation layer may be 50nm to 100nm.
In addition, the number of the first stacked layers may be set according to the requirement of the number of the nanowires or the sheets included in the first transistor in the practical application scenario. For example: when the first transistor includes two layers of nanowires or sheets, the number of layers of the first stack is two.
As shown in fig. 1, a semiconductor layer 15 is formed overlying the second isolation layer 14. The semiconductor layer 15 is a second channel layer 161 or at least one second stack 16. The second stack 16 includes a second sacrificial layer 162 and a second channel layer 161 which are stacked on the second isolation layer 14 along the thickness direction of the substrate 11. The material of the second channel layer 161 is silicon germanium, and the content of germanium in the second channel layer 161 is different from that in the first channel layer 132.
Illustratively, in the case where the semiconductor layer is a layer of the second channel layer formed on the second isolation layer, the second channel layer may be formed through an epitaxial process. The second channel layer is a film layer forming the second channel region, so the content of germanium in the second channel layer and the thickness of the second channel layer can be set by referring to the content of germanium in the second channel region and the thickness of the second channel region as described above.
In the case where the semiconductor layer is at least one second stacked layer formed on the second isolation layer, the second stacked layer may be formed by an epitaxial process. As for the number of layers of the second stacked layer, the number of layers of the nanowire or the sheet included in the second transistor may be set according to the requirement of the practical application scenario. For example: when the second transistor comprises only one layer of nanowires or pads, a second layer stack may be formed on the second isolation layer. Another example is: when the second transistor includes a plurality of layers of nanowires or sheets, it is necessary to form a second stacked layer on the second isolation layer in the same number of layers as the number of layers of nanowires or sheets included in the second transistor. Specifically, reference may be made to the foregoing materials of the second channel layer included in the second stacked layer. In addition, the second sacrificial layer included in the second stack may be formed on the second channel layer with a certain etch selectivity between the material of the second isolation layer and the material of the second channel layer. Of course, the second channel layer may also be formed on the second sacrificial layer. The position relationship between the second channel layer and the second sacrificial layer may be set according to an actual application scenario, and is not specifically limited herein. In addition, the existence of the second sacrificial layer can enable a space to be formed between the adjacent second channel regions after the second channel regions are released, and a second gate stack structure surrounding the periphery of the second channel regions can be formed through the space. The material of the second sacrificial layer and the material of the second channel layer need to have a certain etching selection ratio. For example: the second sacrificial layer may be made of silicon.
It is noted that a first channel layer for forming a first channel region, a first sacrificial layer and a second isolation layer for isolation, and a second channel layer for forming a second channel region are sequentially epitaxially grown on a buffer material layer for forming a buffer layer. Alternatively, a second sacrificial layer for isolation may be formed in addition to the above-described film layer. At this time, the presence of the buffer material layer may provide stress to the first and second channel layers, thereby causing strain to be generated in the first and second channel regions formed based on the first and second channel layers, thereby improving mobility of carriers in the first and second transistors and improving driving performance of the semiconductor device.
As shown in fig. 1, in one example, as described previously, when the semiconductor layer 15 is the second channel layer 161, or when the semiconductor layer 15 is at least one second stack 16 and the second channel layer 161 included in the second stack 16 is located on the second sacrificial layer 162, the silicon protection layer 17 may be formed on the semiconductor layer 15.
Illustratively, the silicon protective layer may be formed by an epitaxial process. The silicon protection layer is formed on the uppermost second channel layer. Based on the silicon protective layer, the second channel layer made of the germanium-silicon material can be protected from the influence of subsequent processes such as sacrificial gate etching and the like, the quality of the second channel region formed based on the second channel layer is improved, and the performance of the semiconductor device is further improved. Of course, if the quality of the second channel region is not sufficiently affected in the subsequent processes such as the sacrificial gate etching, the silicon protection layer may not be formed.
As shown in fig. 2, in the case where the silicon protection layer is formed on the semiconductor layer, a portion of the buffer material layer is etched from the top of the silicon protection layer to form the fin structure 18 extending along the first direction. The remaining buffer material layer forms the buffer layer 121.
Illustratively, a photoresist layer may be formed on the silicon protective layer. And exposing and developing the photoresist layer to form a photoresist pattern. And then, etching to part of the buffer material layer from the top of the silicon protection layer through advanced processes such as side wall transfer and the like to form a fin-shaped structure extending along the first direction. At this time, the fin structure includes a silicon protection layer, a second channel layer (or a second channel layer and a second sacrificial layer), a second isolation layer, a first channel layer, a first sacrificial layer, and a portion remaining after a portion of the buffer material layer is etched.
The etched depth of the buffer material layer may be set according to the thickness of the shallow trench isolation. For example: the buffer material layer may be etched to a depth greater than or equal to the thickness of the shallow trench isolation. And the remaining buffer material layer forms a buffer layer. Specifically, the part of the buffer material layer which is not etched forms a first buffer part. And the part of the top of the buffer material layer which is left after etching forms a second buffer part. In addition, the first direction may be any direction parallel to the surface of the substrate.
If the silicon protection layer is not formed on the semiconductor layer, it is necessary to etch a portion of the buffer material layer from the top of the semiconductor layer to form the fin structure. At this time, the fin structure includes a portion remaining after the second channel layer (or the second channel layer and the second sacrificial layer), the second isolation layer, the first channel layer, the first sacrificial layer, and a portion of the buffer material layer are etched.
As shown in fig. 3 to 12, a first transistor 28 is formed over the buffer layer 121, and a second transistor 29 is formed over the first transistor 28. The second transistor 29 and the first transistor 28 are of different conductivity types. The second transistor 29 and the first transistor 28 are both ring-gate transistors. The second channel region 1611 included in the second transistor 29 and the first channel region 1321 included in the first transistor 28 are both made of silicon germanium, and the content of germanium in the second channel region 1611 is different from that in the first channel region 1321.
Specifically, for information such as the conductivity types corresponding to the first transistor and the second transistor, and the content of germanium in the first channel region and the second channel region, reference may be made to the foregoing, and details are not repeated here.
In one example, the forming the first transistor on the buffer layer and the forming the second transistor on the first transistor may include:
as shown in fig. 3 and 4, shallow trench isolations 19 are formed on portions of the buffer layer 121 between adjacent two fin structures. The exposed portion of the fin structure outside the shallow trench isolation 19 is a fin 181. The fin 181 includes a first semiconductor region 1811, a second semiconductor region 1812, and a gate formation region 1813 located between the first semiconductor region 1811 and the second semiconductor region 1812.
Illustratively, the shallow trench isolation may be formed by depositing an isolation material between adjacent fin structures by a physical vapor deposition or chemical vapor deposition process, and etching back the isolation material. The top of the shallow trench isolation may be flush with or lower than the top of the second buffer. The material of the shallow trench isolation can be referred to above.
As shown in fig. 5, a sacrificial gate 20 extending in the second direction is formed at the outer periphery of the gate forming region. The second direction is different from the first direction.
Illustratively, as shown in fig. 5, a gate material for forming the sacrificial gate 20 may be deposited on the fin structure and the shallow trench isolation 19 by a chemical vapor deposition process or the like. Then, the gate material may be etched by a dry etching method, and only a portion of the gate material located at the periphery of the gate formation region is remained, so as to obtain the sacrificial gate 20 extending along the second direction. The second direction may be any direction parallel to the surface of the substrate 11 and different from the first direction. Preferably, the second direction is orthogonal to the first direction. The gate material may be amorphous silicon, polysilicon, or other material that is easily removed. In addition, after the sacrificial gate 20 is formed, the spacers 21 may be formed at the two sidewalls of the sacrificial gate 20 in the width direction in the above manner. The material of the sidewall spacers 21 may be an insulating material such as silicon nitride.
As shown in fig. 6 and 7, the first source/drain region 22 included in the first transistor is formed at least on a portion of the buffer layer 121 located in the first semiconductor region and the second semiconductor region.
Illustratively, in the case where the silicon protective layer is formed on the semiconductor layer, portions of the silicon protective layer, the second channel layer (or the second channel layer and the second sacrificial layer), and the second isolation layer located within the first semiconductor region and the second semiconductor region may be removed by an anisotropic etching process. A layer of epitaxial isolation material may then be formed overlying the formed structure using a process such as chemical vapor deposition. And the epitaxial isolation material may be etched by a dry etching process to form an epitaxial isolation layer (not shown). The epitaxial isolation layer is not only formed on two side walls of the side wall along the width direction, but also covers the periphery of the silicon protection layer, the second channel layer (or the second channel layer and the second sacrificial layer) and the rest part of the second isolation layer after being etched. The material of the epitaxial isolation layer can be set according to the actual application scene, and is not specifically limited here. As shown in fig. 7, an epitaxial process may be used to form the first source/drain regions 22 at least on the portions of the buffer layer 121 located in the first semiconductor region and the second semiconductor region. The existence of the epitaxial isolation layer can prevent epitaxial materials from being simultaneously formed on the silicon protection layer, the second channel layer (or the second channel layer and the second sacrificial layer) and the periphery of the part of the second isolation layer left after being etched in the process of epitaxially forming the first source/drain region 22, so that the yield of the semiconductor device is improved.
The first source/drain region may be formed on the shallow trench isolation, in addition to the buffer layer. Further, as described earlier, when the silicon protective layer is not formed, only portions of the second channel layer (or the second channel layer and the second sacrificial layer) and the second isolation layer located within the first semiconductor region and the second semiconductor region may be removed by an anisotropic etching process. The epitaxial isolation layer formed subsequently is formed on two side walls of the side walls along the width direction and covers the second channel layer (or the second channel layer and the second sacrificial layer) and the periphery of the etched residual part of the second isolation layer.
Further, the first source/drain region may be formed in other desirable forms other than the above-described forms.
In one example, as shown in fig. 8, in a case where the manufactured semiconductor device further includes the first isolation layer 23, after forming the first source/drain region 22 included in the first transistor at least on a portion of the buffer layer 121 located in the first semiconductor region and the second semiconductor region, and before forming the second source/drain region included in the second transistor above the first source/drain region 22, the manufacturing method of the semiconductor device further includes: a first isolation layer 23 is formed on the first source/drain region 22. The first isolation layer 23 is located between the first source/drain region 22 included in the first transistor and the second source/drain region included in the second transistor, and is used for isolating the first source/drain region 22 from the second source/drain region.
Illustratively, the isolation material covering the first source/drain region and the sacrificial gate may be formed by chemical vapor deposition or the like. The isolation material may then be sequentially subjected to a planarization process and an etching-back process, leaving only a portion of the isolation material overlying the first source/drain region, and a top height of the remaining isolation material being less than a bottom height of the lowermost second channel layer, thereby obtaining a first isolation layer. The material of the first isolation layer can be referred to above.
Illustratively, after the first isolation layer is formed. Or after the first source/drain region is formed and before the first isolation layer is formed, the epitaxial isolation layer may be etched by using a dry etching process or the like until the height of the top of the remaining epitaxial isolation layer is less than the height of the bottom of the second channel layer located at the lowest position.
As shown in fig. 9, a second source/drain region 24 included in the second transistor is formed above the first source/drain region 22.
Illustratively, the second source/drain region may be formed over the first source/drain region using an epitaxial process. Of course, the second source/drain region may be formed in other satisfactory manners besides the above-described formation manner.
As shown in fig. 10, in an example, as described above, in the case that the manufactured semiconductor device further includes the dielectric layer 25, after forming the second source/drain region 24 included in the second transistor above the first source/drain region 22, before removing the sacrificial gate 20, the manufacturing method of the semiconductor device may further include: a dielectric layer 25 is formed overlying the first source/drain regions 22 and the second source/drain regions 24.
Illustratively, the dielectric material covering the first source/drain region, the second source/drain region and the sacrificial gate may be formed by chemical vapor deposition or the like. The dielectric material may then be thinned by chemical mechanical polishing or the like until the top of the sacrificial gate is exposed. Correspondingly, the residual dielectric material only covers the first source/drain region and the second source/drain region, so that a dielectric layer is obtained. The material and thickness of the dielectric layer can be referred to above.
As shown in fig. 11, the sacrificial gate is removed. And with the buffer layer 121 as an etching stop layer, a portion of the second isolation layer and the first sacrificial layer located in the gate formation region is removed, or a portion of the second sacrificial layer, the second isolation layer and the first sacrificial layer located in the gate formation region is removed, so that a portion of the second channel layer located in the gate formation region forms a second channel region 1611, and a portion of the first channel layer located in the gate formation region forms a first channel region 1321.
For example, the sacrificial gate located at the periphery of the gate formation region may be selectively removed by wet etching or the like. At this time, the portion of the fin portion located in the gate formation region is exposed. And then, under the condition that the semiconductor layer is the second channel layer and a silicon protection layer is not formed on the semiconductor layer, wet etching and other modes can be adopted to remove the second isolation layer and the part of the first sacrificial layer, which is positioned in the grid electrode forming area. And under the condition that the semiconductor layer is at least one second lamination layer and a silicon protection layer is not formed on the semiconductor layer, wet etching and other manners can be adopted to remove the second sacrificial layer, the second isolation layer and the part of the first sacrificial layer, which is positioned in the grid electrode forming area. Accordingly, a portion of the second channel layer located within the gate forming region forms a second channel region. A portion of the first channel layer located within the gate forming region forms a first channel region.
As described above, in the case where the silicon protective layer is formed on the semiconductor layer, after the sacrificial gate is removed, the portion of the silicon protective layer located in the gate electrode formation region needs to be removed before the first gate stack structure and the second gate stack structure are formed.
It should be noted that, as shown in fig. 11, in the process of releasing the first channel region 1321 and the second channel region 1611 located in the gate forming region, the buffer layer 121 may isolate the film to be etched, including the first sacrificial layer and the second isolation layer (or the first sacrificial layer, the second isolation layer, and the second sacrificial layer), from the substrate 11, and even if the etching selection between the film to be etched and the substrate 11 is relatively low, an etchant for etching the film to be etched cannot contact and react with the substrate 11, so as to ensure that the topography of the substrate 11 meets the requirement of a preset scheme, and improve the yield and performance of the semiconductor device.
As shown in fig. 12, a first gate stack structure 26 is formed around the outer periphery of the first channel region 1321, and at the same time, a second gate stack structure 27 is formed around the outer periphery of the second channel region 1611, so that a first transistor 28 and a second transistor 29 are obtained. The first gate stack structure 26 and the second gate stack structure 27 are made of the same material.
For example, the first gate stack structure and the second gate stack structure may be formed simultaneously by atomic layer deposition or the like. Specifically, the specific structures and materials of the first gate stack structure and the second gate stack structure may refer to the foregoing, and are not described herein again.
As can be seen from the above, the semiconductor manufacturing method provided by the present invention only needs to form the first channel region on the buffer layer and form the second channel region above the first channel region, so that the first transistor and the second transistor have different threshold voltages, and it is not necessary to form gate stack structures with different thicknesses or materials on the peripheries of the channel regions included in different transistors by means of etching back and multiple depositions, thereby simplifying the manufacturing process of the semiconductor device.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims (11)

1. A semiconductor device, comprising: a substrate, a first electrode and a second electrode,
a buffer layer formed on the substrate;
a first transistor formed on the buffer layer;
and a second transistor formed over the first transistor; the second transistor and the first transistor are different in conductivity type; the second transistor and the first transistor are all ring-gate transistors; the second channel region included by the second transistor and the first channel region included by the first transistor are both made of germanium-silicon, and the content of germanium in the second channel region is different from that in the first channel region; the first transistor is an NMOS transistor, and the second transistor is a PMOS transistor; or, the first transistor is a PMOS transistor, and the second transistor is an NMOS transistor; the channel region of the NMOS transistor is made of Si 1-y Ge y Wherein y is more than or equal to 0.1 and less than or equal to 0.5; the PMOS transistor comprises a channel region made of Si 1-z Ge z Wherein z is more than or equal to 0.4 and less than 1, and z-y is more than or equal to 0.3.
2. The semiconductor device according to claim 1, wherein a material of a first gate stack structure included in the first transistor is the same as a material of a second gate stack structure included in the second transistor; and/or the presence of a gas in the gas,
the buffer layer is made of Si 1-x Ge x Wherein x is more than or equal to 0.25 and less than or equal to 0.7; and/or the presence of a gas in the atmosphere,
the buffer layer comprises a first buffer part and a second buffer part; the first buffer part covers the substrate; the second buffer part is a fin-shaped structure formed on the first buffer part; the first source/drain region and the first channel region included in the first transistor are formed on the second buffer.
3. The semiconductor device of claim 1, wherein the first channel region and the second channel region are self-aligned.
4. The semiconductor device according to any one of claims 1 to 3, wherein a minimum vertical distance between the first channel region and the second channel region is 50nm to 100nm; and/or the presence of a gas in the gas,
the semiconductor device further includes a first isolation layer; the first isolation layer is located between a first source/drain region included in the first transistor and a second source/drain region included in the second transistor, and is used for isolating the first source/drain region from the second source/drain region.
5. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a buffer layer on the substrate;
forming a first transistor on the buffer layer and a second transistor on the first transistor; the second transistor and the first transistor are different in conductivity type; the second transistor and the first transistor are all ring-gate transistors; the second channel region included by the second transistor and the first channel region included by the first transistor are both made of germanium-silicon, and the content of germanium in the second channel region is different from that in the first channel region; the first transistor is an NMOS transistor, and the second transistor is a PMOS transistor; or, the first transistor is a PMOS transistor, and the second transistor is an NMOS transistor; the channel region of the NMOS transistor is made of Si 1-y Ge y Wherein y is more than or equal to 0.1 and less than or equal to 0.5; the PMOS transistor comprises a channel region made of Si 1-z Ge z Wherein z is more than or equal to 0.4 and less than 1, and z-y is more than or equal to 0.3.
6. The method for manufacturing a semiconductor device according to claim 5, wherein the forming of the buffer layer over the substrate includes:
forming a buffer material layer covering the surface of the substrate;
sequentially forming at least one first laminated layer covering the buffer material layer and a second isolating layer positioned on the at least one first laminated layer; the first laminate includes a first sacrificial layer, and a first channel layer on the first sacrificial layer; the first channel layer is made of germanium-silicon;
forming a semiconductor layer overlying the second isolation layer; the semiconductor layer is a second channel layer or at least one second laminated layer; the second laminated layer includes a second sacrificial layer and a second channel layer which are laminated on the second isolation layer along a thickness direction of the substrate; the second channel layer is made of germanium-silicon, and the content of germanium in the second channel layer is different from that in the first channel layer;
etching to a part of the buffer material layer from the top of the semiconductor layer to form a fin-shaped structure extending along a first direction; the remaining buffer material layer forms the buffer layer.
7. The method according to claim 6, wherein when the semiconductor layer is the second channel layer, or when the semiconductor layer is at least one second stacked layer and the second channel layer included in the second stacked layer is on the second sacrificial layer, after the semiconductor layer is formed so as to cover the second isolation layer, before the first transistor is formed on the buffer layer and the second transistor is formed on the first transistor, the method comprises:
forming a silicon protective layer on the semiconductor layer;
etching to a part of the buffer material layer from the top of the silicon protection layer to form the fin-shaped structure; and/or the presence of a gas in the gas,
after forming the buffer material layer covering the surface of the substrate and before forming the at least one first stacked layer covering the buffer material layer, the method for manufacturing the semiconductor device further comprises:
and carrying out planarization treatment on the buffer material layer.
8. The method for manufacturing a semiconductor device according to claim 6, wherein a thickness of the buffer material layer is 100nm to 1.5 μm; and/or the presence of a gas in the gas,
the first sacrificial layer, the second sacrificial layer and the second isolation layer are all made of silicon; and/or the presence of a gas in the gas,
the thickness of the second isolation layer is 50 nm-100 nm.
9. The method for manufacturing the semiconductor device according to claim 6, wherein the forming of a first transistor over the buffer layer and a second transistor over the first transistor comprises:
removing the second isolation layer and the part of the first sacrificial layer, which is positioned in a grid electrode forming area, or removing the second sacrificial layer, the second isolation layer and the part of the first sacrificial layer, which is positioned in the grid electrode forming area, by taking the buffer layer as an etching stop layer, so that the part of the second channel layer, which is positioned in the grid electrode forming area, forms the second channel area, and the part of the first channel layer, which is positioned in the grid electrode forming area, forms the first channel area;
forming a first gate stack structure around the periphery of the first channel region and simultaneously forming a second gate stack structure around the periphery of the second channel region to obtain the first transistor and the second transistor; the first gate stack structure and the second gate stack structure are made of the same material.
10. The method according to claim 9, wherein after the buffer layer is formed over the substrate, the buffer layer is used as an etching stop layer to remove the second isolation layer and the first sacrificial layer at a portion in the gate formation region, or before the second sacrificial layer, the second isolation layer, and the first sacrificial layer are removed at a portion in the gate formation region, and the method further comprises:
forming shallow trench isolation on a part of the buffer layer between two adjacent fin structures; the part of the fin-shaped structure exposed outside the shallow trench isolation is a fin part; the fin portion includes a first semiconductor region, a second semiconductor region, and a gate formation region located between the first semiconductor region and the second semiconductor region;
forming a sacrificial gate extending in a second direction at the periphery of the gate forming region; the second direction is different from the first direction;
forming a first source/drain region included in the first transistor at least on a portion of the buffer layer located in the first semiconductor region and the second semiconductor region;
forming a second source/drain region included in the second transistor over the first source/drain region;
and removing the sacrificial gate.
11. The method according to claim 10, wherein after the first source/drain region included in the first transistor is formed at least on the portion of the buffer layer located in the first semiconductor region and the second semiconductor region, and before the second source/drain region included in the second transistor is formed over the first source/drain region, the method further comprises:
forming a first isolation layer on the first source/drain region; the first isolation layer is located between a first source/drain region included in the first transistor and a second source/drain region included in the second transistor, and is used for isolating the first source/drain region from the second source/drain region.
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