CN114678329A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
CN114678329A
CN114678329A CN202210167255.1A CN202210167255A CN114678329A CN 114678329 A CN114678329 A CN 114678329A CN 202210167255 A CN202210167255 A CN 202210167255A CN 114678329 A CN114678329 A CN 114678329A
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China
Prior art keywords
dielectric layer
fin
gate dielectric
region
gate
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CN202210167255.1A
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Chinese (zh)
Inventor
李永亮
陈安澜
程晓红
罗军
王文武
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to CN202210167255.1A priority Critical patent/CN114678329A/en
Publication of CN114678329A publication Critical patent/CN114678329A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

Abstract

The invention discloses a manufacturing method of a semiconductor device, relates to the technical field of semiconductors, and is used for solving the problem of poor compatibility between a core device with a gate-all-around transistor and an input/output device. The manufacturing method comprises the following steps: a first fin portion and a second fin portion which are identical in structure are formed on a substrate. And forming a first gate dielectric layer at least covering the peripheries of the channel forming regions of the first fin part and the second fin part, wherein the part of the first fin part, which is positioned in the channel forming region, forms a channel of the fin field effect transistor. And removing the part of the first gate dielectric layer, which is positioned at the periphery of the channel forming region of the second fin part. And processing the channel forming region of the second fin portion to obtain the channel of the gate-all-around transistor. And forming a second gate dielectric layer on the rest part of the first gate dielectric layer and a third gate dielectric layer around the periphery of the channel of the gate-all-around transistor. The thickness of the third gate dielectric layer is smaller than the total thickness of the first gate dielectric layer and the second gate dielectric layer.

Description

Method for manufacturing semiconductor device
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor device.
Background
The gate-all-around transistor has the advantages of higher gate control capability and the like compared with a planar transistor and a fin field effect transistor, so that the working performance of an integrated circuit comprising the core device can be improved when the device structure of the core device is the gate-all-around transistor.
However, the compatibility between the core device with the gate-all-around transistor and the input/output device of the integrated circuit is poor, and it is difficult to integrate the core device and the input/output device by using the existing manufacturing method.
Disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor device, which is used for solving the problem of poor compatibility between a core device with a gate-all-around transistor and an input/output device of an integrated circuit and reducing the integration difficulty of the core device and the input/output device.
In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device, the method comprising:
a substrate is provided. The substrate has a first element region and a second element region.
A first fin portion and a second fin portion which are identical in structure are formed on a substrate. The first fin portion is located on the first element region. The second fin portion is located on the second element region. The first fin portion and the second fin portion are provided with channel forming regions.
And forming a first gate dielectric layer at least covering the peripheries of the channel forming regions of the first fin part and the second fin part, wherein the part of the first fin part in the channel forming region forms a channel of the fin field effect transistor.
And removing the part of the first gate dielectric layer, which is positioned at the periphery of the channel forming region of the second fin part. And processing the channel forming region of the second fin portion to obtain the channel of the gate-all-around transistor.
And forming a second gate dielectric layer on the rest part of the first gate dielectric layer and a third gate dielectric layer surrounding the periphery of the channel of the gate-all-around transistor. The thickness of the third gate dielectric layer is smaller than the total thickness of the first gate dielectric layer and the second gate dielectric layer.
Compared with the prior art, in the manufacturing method of the semiconductor device, the first gate dielectric layer is formed to at least cover the periphery of the channel forming region of the first fin part and the periphery of the channel forming region of the second fin part, after the channel forming region of the first fin part forms the channel of the fin field effect transistor, the part, located on the periphery of the channel forming region of the second fin part, of the first gate dielectric layer is removed, and the channel forming region of the second fin part is processed to obtain the channel of the ring gate transistor. At the moment, a first gate dielectric layer is formed on the periphery of a channel of the fin field effect transistor. And the gate-all-around transistor has a channel exposed to the outside. And then forming a second gate dielectric layer on the rest part of the first gate dielectric layer and a third gate dielectric layer around the periphery of the channel of the gate-all-around transistor. After the operation is carried out, a first gate dielectric layer and a second gate dielectric layer are sequentially formed on the periphery of a channel of the fin field effect transistor. And the gate-all-around transistor is provided with a channel which is only surrounded by a third gate dielectric layer. And the thickness of the third gate dielectric layer is smaller than the total thickness of the first gate dielectric layer and the second gate dielectric layer. Based on this, when the manufacturing method of the semiconductor device provided by the invention is used for manufacturing an input/output device and a core device, the input/output device with the fin field effect transistor as the device structure and the core device with the gate all around transistor as the device structure can be formed, so that the problem that when the input/output device also adopts the gate all around transistor structure due to the fact that the thickness of the gate dielectric layer of the input/output device is large, the subsequent metal gate material cannot be filled or only can be partially filled due to the fact that the space between channels is small, the problem of poor compatibility with the core device is solved, and the integration difficulty of the core device and the input/output device is reduced.
In addition, the first fin portion on the first element region and the second fin portion on the second element region have the same structure, so that the first fin portion and the second fin portion can be formed on the substrate at the same time, the manufacturing process of the semiconductor device can be simplified, and the manufacturing cost of the semiconductor device can be reduced.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic structural diagram of a core device and an input/output device integrated with a gate-all-around transistor;
fig. 2 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a structure after at least one stacked material layer is formed on a substrate according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram illustrating a first fin structure and a second fin structure formed on a substrate according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a structure after shallow trench isolation is formed on a substrate in an embodiment of the present invention;
FIG. 6 is a cross-sectional view of the structure of FIG. 5 taken along line B-B';
FIG. 7 is a schematic diagram of a first structure after a first gate dielectric layer is formed on a substrate according to an embodiment of the present invention;
FIG. 8 is a cross-sectional view of the structure shown in FIG. 7, taken along line A-A';
FIG. 9 is a cross-sectional view of the structure shown in FIG. 7, taken along line B-B';
FIG. 10 is a diagram illustrating a second structure after a first gate dielectric layer is formed on a substrate according to an embodiment of the present invention;
FIG. 11 is a cross-sectional view of the structure shown in FIG. 10, taken along line B-B';
FIG. 12 is a cross-sectional view of a first structure along the direction B-B' after forming a sacrificial gate and a sidewall spacer in an embodiment of the present invention;
FIG. 13 is a cross-sectional view of a second structure along the direction B-B' after forming a sacrificial gate and a sidewall spacer in an embodiment of the present invention;
FIG. 14 is a cross-sectional view of a structure along B-B' after forming source and drain regions in an embodiment of the present invention;
FIG. 15 is a schematic structural diagram illustrating a dielectric layer formed in an embodiment of the present invention;
FIG. 16 is a cross-sectional view of the structure taken along line A-A' after removal of the sacrificial gate in an embodiment of the present invention;
FIG. 17 is a cross-sectional view of a structure taken along the direction A-A' after a mask layer is formed in an embodiment of the present invention;
FIG. 18 is a cross-sectional view of a structure along the direction A-A' after forming a channel in a gate-all-around transistor according to an embodiment of the present invention;
FIG. 19 is a cross-sectional view of the structure taken along the line A-A' after the mask layer has been removed in accordance with an embodiment of the present invention;
FIG. 20 is a structural cross-sectional view taken along the direction A-A' after forming a second gate dielectric layer and a third gate dielectric layer in an embodiment of the present invention;
FIG. 21 is a cross-sectional view of a fin field effect transistor and a gate-all-around transistor formed in accordance with an embodiment of the present invention.
Reference numerals are as follows: 11 is a substrate, 111 is a first element region, 112 is a second element region, 12 is a stacked material layer, 121 is a sacrificial material layer, 1211 is a sacrificial layer, 122 is a channel material layer, 1221 is a channel layer, 123 is a stack layer, 13 is a first fin structure, 131 is a first fin portion, 14 is a second fin structure, 141 is a second fin portion, 15 is a channel formation region, 16 is a source region formation region, 17 is a drain region formation region, 18 is a shallow trench isolation, 19 is a first gate dielectric layer, 20 is a sacrificial gate, 21 is a sidewall, 22 is a source region, 23 is a drain region, 24 is a dielectric layer, 25 is a mask layer, 26 is a channel, 27 is a second gate dielectric layer, 28 is a third gate dielectric layer, 29 is a first gate, 30 is a second gate, 31 is a fin field effect transistor, 32 is a ring gate transistor, 33 is a gate dielectric layer, 34 is a gate, 35 is an input/output device, and 36 is a core device.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that these descriptions are illustrative only and are not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and some details may be omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed. In order to make the technical problems, technical solutions and advantageous effects of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise. The meaning of "a number" is one or more unless specifically limited otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
An integrated circuit has input/output (IO) devices and Core (Core) devices. The input/output device is mainly used for realizing input and output functions between a chip and a peripheral circuit in an integrated circuit. Because the input/output device needs to bear higher working voltage (usually 1.8V, 2.5V, 3.3V or 5V, etc.), the input/output device has a thicker gate dielectric layer. The core device is a device used in the chip and is mainly used for realizing logic operation in the chip. Because the number of core devices in the chip is large, the core devices usually use a lower operating voltage (usually 1.0V or 1.2V, etc.) to achieve the purpose of saving power consumption and increasing the operation speed. Correspondingly, the thickness of the gate dielectric layer of the core device is smaller.
In addition, the gate-all-around transistor has the advantages of higher gate control capability and the like compared with a planar transistor and a fin field effect transistor, so that the working performance of the integrated circuit can be improved when the core device is the gate-all-around transistor. In the process of manufacturing the Core device and the input/output device of the gate-all-around transistor on the same substrate, as shown in fig. 1, after forming a gate dielectric layer 33 (the thickness of the gate dielectric layer 33 is smaller) around the periphery of the channel 26 of the Core device 36 on the Core device region of the substrate 11 and a gate dielectric layer 33 (the thickness of the gate dielectric layer 33 is larger) around the periphery of the channel 26 of the input/output device 35 on the IO device region, because the distance between adjacent nanowires or sheets only meets the structural requirement of the Core device 36, compared with the input/output device 35, after forming the thicker gate dielectric layer 33, the gate dielectric layer 33 fills the gap between the smaller nanowires or sheets or only leaves a smaller gate forming space between the nanowires or sheets, and then the input meeting the working requirement cannot be formed in the gap or the smaller gate space The gate 34 of the output device 35 causes a "pinch-off" phenomenon between adjacent nanowires or chips in the IO device region, thereby affecting the electrical performance of the input/output device 35 formed in the IO device region, i.e., it is difficult to integrate the core device 36 of which the device structure is a gate-all-around transistor with the input/output device 35, and reduce the working performance of the input/output device 35.
In order to solve the above technical problem, embodiments of the present invention provide a method for manufacturing a semiconductor device. In the method for manufacturing the semiconductor device, the remaining first gate dielectric layer is only located at the periphery of the channel of the fin field effect transistor through the processes of deposition, selective removal and the like. And after forming the channel of the gate all around transistor, forming a second gate dielectric layer positioned on the rest part of the first gate dielectric layer and a third gate dielectric layer formed around the periphery of the channel of the gate all around transistor, so as to realize that the fin field effect transistor and the gate all around transistor have gate dielectric layers with different thicknesses.
As shown in fig. 2, an embodiment of the present invention provides a method for manufacturing a semiconductor device. The manufacturing process will be described below with reference to the perspective and cross-sectional views of the operation shown in fig. 3 to 21. Specifically, the manufacturing method of the semiconductor device comprises the following steps:
first, a substrate is provided. The substrate has a first element region and a second element region.
The substrate may be any semiconductor substrate such as a silicon substrate, a silicon-on-insulator substrate, a silicon-germanium substrate, or a germanium substrate. The substrate is provided with a first element region which is a region corresponding to a subsequently formed fin field effect transistor, so that the position and the number of the first element region on the substrate can be set according to the forming position and the number of the fin field effect transistor on the substrate respectively. The substrate has a second element region corresponding to a subsequently formed gate-all-around transistor, so that the positions and the number of the second element regions on the substrate can be set according to the forming positions and the number of the gate-all-around transistors on the substrate respectively.
Illustratively, when the semiconductor device manufacturing method provided by the embodiment of the invention is used for manufacturing an input/output device with a device structure of a fin field effect transistor and a core device with a device structure of a gate-all-around transistor, the first device region is located at the periphery of the second device region.
As shown in fig. 3 to 6, the first fin 131 and the second fin 141 having the same structure are formed on the substrate 11. The first fin 131 is located on the first device region 111. The second fin 141 is located on the second device region 112. The first fin 131 and the second fin 141 each have a channel formation region 15.
Specifically, the first fin portion and the second fin portion have the same structure, which means that the specifications, components, and materials contained in the first fin portion and the second fin portion are the same. The specific structures of the first fin portion and the second fin portion can be set according to actual requirements. Illustratively, as shown in fig. 5, the first fin 131 and the second fin 141 may each include at least one stacked layer 123 along a thickness direction of the substrate 11. Each of the stacked layers 123 includes a sacrificial layer 1211, and a channel layer 1221 on the sacrificial layer 1211. Specifically, as shown in fig. 7 to 11, a channel of the finfet is formed based on the channel formation region 15 of the first fin 131, and thus the sacrificial layer and the channel layer are made of semiconductor materials. As shown in fig. 17 and 18, the channel formation region 15 of the second fin is processed to form the channel 26 of the gate-all-around transistor, so that the sacrificial layer and the channel layer have a certain etching selectivity. Illustratively, the channel layer may include Si as a material 1-xGex. X is more than or equal to 0 and less than or equal to 1. The material contained in the sacrificial layer may be Si1-yGey. Y is more than or equal to 0 and less than or equal to 1, and | x-y | is more than or equal to 0.2. For example: the channel layer contains Si as a material. The sacrificial layer may contain Si0.5Ge0.5Or Ge. Another example is: the channel layer contains Si as a material0.5Ge0.5. The sacrificial layer may contain a material of Si or Ge.
The number of stacked layers included in the first fin portion and the second fin portion is equal to the number of layers of nanowires or sheets included in a channel of the gate-all-around transistor, so that the number of stacked layers can be set according to the number of layers of nanowires or sheets included in the gate-all-around transistor to be manufactured. In addition, the extending directions of the lengths of the first fin portion and the second fin portion may be the same or different.
In the practical application process, shallow trench isolation is also formed on the substrate. The first fin portion and the second fin portion are exposed outside the shallow trench isolation. The material contained in the shallow trench isolation may be an insulating material such as silicon oxide, silicon oxycarbide, or silicon nitride. The thickness of the shallow trench isolation can be set according to actual requirements. Further, as shown in fig. 6, the first fin portion and the second fin portion formed on the substrate 11 may each have not only the channel formation region 15 but also the source region formation region 16 and the drain region formation region 17. The channel formation region 15 is located between the source region formation region 16 and the drain region formation region 17. Therefore, after the sacrificial gate and the side wall are formed on the periphery of the channel forming region at least covering the channel of the fin field effect transistor and the channel forming region of the second fin part, the source region contacting with the channel forming region can be conveniently formed at least in the source region forming region, and the drain region contacting with the channel forming region can be conveniently formed at least in the drain region forming region.
In an example, in a case where the first fin portion and the second fin portion each include the at least one stacked layer, the forming the first fin portion and the second fin portion having the same structure on the substrate may include:
as shown in fig. 3, at least one laminated material layer 12 is formed on the substrate 11 along the thickness direction of the substrate 11.
In practical applications, the at least one stacked material layer may be formed by using a process such as epitaxial growth. As shown in fig. 3 to 5, the at least one laminated material layer 12 is a film layer for forming the at least one laminated layer 123 included in the first fin portion 131 and the second fin portion 141, so that the number of layers and the thickness of the laminated material layer 12 formed on the substrate 11 may be set with reference to the number of layers and the thickness of the laminated layer 123. The materials contained in the sacrificial material layer 121 and the channel material layer 122 included in the stacked-layer material layer 12 may be respectively provided with reference to the materials contained in the sacrificial layer 1211 and the channel layer 1221 included in the stacked layer 123.
As shown in fig. 4, at least one of the stacked material layers and the substrate 11 are etched to form a first fin structure 13 on the first element region 111 and a second fin structure 14 on the second element region 112.
In practical applications, a photoresist mask may be formed on the top stacked material layer. The photoresist mask covers a region where the first fin structure and the second fin structure are formed later. And under the mask action of the photoresist mask, etching from the top of the at least one laminated material layer to the substrate downwards by adopting a dry etching process to form the first fin-shaped structure and the second fin-shaped structure. Wherein the depth of the substrate etched is greater than or equal to the thickness of the shallow trench isolation.
As shown in fig. 5, shallow trench isolations 18 are formed on portions of the substrate 11 exposed outside the first and second fin structures. The exposed portion of the first fin structure outside the shallow trench isolation 18 is a first fin 131. The exposed portion of the second fin structure outside the shallow trench isolation 18 is a second fin 141.
In an actual application process, the isolation material covering the substrate and the first fin-shaped structure and the second fin-shaped structure can be formed by adopting processes such as chemical vapor deposition or physical vapor deposition, and the isolation material is subjected to planarization treatment by adopting a chemical mechanical polishing process, so that the top of the remaining isolation material is respectively flush with the top of the first fin-shaped structure and the top of the second fin-shaped structure, and therefore after the remaining isolation material is etched back to form shallow trench isolation, all regions of the shallow trench isolation are in the same plane, the situation that the part of the channel layer adjacent to the shallow trench isolation, which is located in the channel forming region of the second fin portion, cannot be released due to the fact that the part of the shallow trench isolation, which is located in the second element region, surrounds the periphery of the sacrificial layer at the bottommost layer is avoided, and the yield of the semiconductor device is improved.
It should be noted that, under the condition that the etched depth of the substrate is greater than the thickness of the shallow trench isolation, the first fin portion and the second fin portion processing both include at least one stacked layer, and also include a portion of the substrate that is etched and exposed outside the shallow trench isolation. And under the condition that the etched depth of the substrate is equal to the thickness of the shallow trench isolation, the first fin part and the second fin part only comprise at least one layer of lamination.
It should be noted that the first fin portion and the second fin portion have the same structure, so that the first fin portion and the second fin portion can be formed on the substrate at the same time, and the manufacturing process of the semiconductor device can be simplified. In addition, in the case where the first fin and the second fin each include the at least one stacked layer, after the first fin is formed, a portion of the first fin located in the channel formation region may be a channel of the finfet. And the channel of the gate-all-around transistor can be released by removing the sacrificial layer in the channel forming region of the second fin part after the second fin part is formed. That is to say, the channels of the two different device structures can be obtained based on the first fin portion and the second fin portion formed on the substrate at the same time, and no additional operations such as material deposition or etching are needed, so that the manufacturing process of the semiconductor device can be simplified, and the manufacturing cost of the semiconductor device can be reduced.
As shown in fig. 7 to 11, the first gate dielectric layer 19 is formed to cover at least the outer periphery of the channel formation region 15 of the first fin 131 and the outer periphery of the channel formation region 15 of the second fin 141, and the channel 26 of the finfet is formed in the portion of the first fin 131 in the channel formation region 15.
In an actual application process, as shown in fig. 7 to 9, in a case that the first gate dielectric layer 19 covers the substrate 11, the first fin portion 131, and the second fin portion 141, the first gate dielectric layer 19 covering the first element region 111 and the second element region 112 may be formed by using an atomic layer deposition process or a plasma enhanced chemical vapor deposition process. As shown in fig. 10 and 11, in the case where the first gate dielectric layer 19 covers the periphery of the channel formation region 15 of the first fin 131 and the channel formation region 15 of the second fin 141, the first dielectric material layer covering the first element region 111 and the second element region 112 may be formed by the above-mentioned process. Then, portions of the substrate 111, the source region formation region 16 and the drain region formation region 17 of the first fin 131, and the source region formation region 16 and the drain region formation region 17 of the second fin 141 may be removed by photolithography and etching processes, so that the remaining first dielectric material layer forms the first gate dielectric layer 19. In this case, the first gate dielectric layer 19 may have portions formed on the channel formation region 15 of the first fin 131 and the channel formation region 15 of the second fin 141, and also have portions formed on the shallow trench isolation for connection. That is, the first gate dielectric layer 19 has a strip structure covering the periphery of the channel formation region 15 of the first fin 131 and the channel formation region 15 of the second fin 141.
As shown in fig. 10 and 11, the fact that the first gate dielectric layer 19 is located on the periphery of the channel formation region 15 of the first fin 131 means that the first gate dielectric layer 19 includes a portion formed on the channel formation region 15 of the first fin 131 and a portion of the first gate dielectric layer 19 located on the first element region 111 for connection. Correspondingly, the fact that the first gate dielectric layer 19 is located on the periphery of the channel formation region 15 of the second fin 141 means that the first gate dielectric layer 19 is formed on the channel formation region 15 of the second fin 141, and the first gate dielectric layer 19 is located on the second element region 112 for connection.
It should be understood that the portion of the first gate dielectric layer located at the periphery of the channel formation region of the first fin portion is a portion constituting the gate dielectric layer of the finfet transistor, and therefore the thickness of the first gate dielectric layer may be set according to the operating voltage of the finfet transistor in an actual application scenario. For example: in the case that the finfet is an input/output device, the thickness of the first gate dielectric layer may be 3nm when the operating voltage of the input/output device is 1.5V or 1.8V. And when the operating voltage of the input/output device is 2.5V or 2.8V, the thickness of the first gate dielectric layer can be 5 nm.
In addition, the material contained in the first gate dielectric layer is an insulating material. The insulating material comprises an oxide insulating material. Correspondingly, when the material contained in the first gate dielectric layer is the oxidation insulating material, the first gate dielectric layer is the gate oxide layer. For example: the first gate dielectric layer contains silicon oxide.
Furthermore, the part of the first gate dielectric layer, which is located at the periphery of the channel formation region of the first fin portion, is a part of the gate dielectric layer which forms the fin field effect transistor, so that under the condition that the formed first gate dielectric layer is only located at the periphery of the channel formation regions of the first fin portion and the second fin portion, the length extension direction of the first gate dielectric layer is any direction which is different from the length extension direction of the first fin portion and is parallel to the surface of the substrate. Preferably, the length extension direction of the first gate dielectric layer is orthogonal to the length extension direction of the first fin portion and the length extension direction of the second fin portion.
In an example, in a case that the first gate dielectric layer is a gate oxide layer, after forming the first gate dielectric layer covering at least the outer peripheries of the channel formation regions of the first fin portion and the channel formation regions of the second fin portion, before performing subsequent operations, the method for manufacturing a semiconductor device may further include: and performing nitridation treatment and/or annealing treatment on the first gate dielectric layer.
In an actual application process, the sacrificial layer or the channel layer included by the first fin portion and the second fin portion contains Ge. Therefore, if the forming temperature is too high during the formation of the first gate dielectric layer, Ge contained in the sacrificial layer or the channel layer is easily oxidized, thereby reducing the yield of the manufactured semiconductor device. And if the forming temperature is too low, the quality of the formed first gate dielectric layer is poor (for example, the compactness of the first gate dielectric layer is low, so that the insulating property of the first gate dielectric layer is poor). After the first gate dielectric layer is formed, the first gate dielectric layer is subjected to nitridation treatment, annealing treatment, nitridation treatment and annealing treatment, and any one of the three operations can improve the compactness of the first gate dielectric layer and the quality of the first gate dielectric layer, so that the working performance of the manufactured semiconductor device is enhanced.
Specifically, the processing conditions of the nitriding treatment and the annealing treatment may be set according to actual requirements, and are not specifically limited herein. Exemplary processing conditions for the nitridation process are: under the nitrogen environment, the processing power is 500W-2000W.
For example, the processing conditions of the annealing treatment may be: nitrogen was used as the shielding gas. The annealing temperature is 400-850 ℃. The treatment time is 10 s-1 min.
In addition, nitridation treatment and annealing treatment need to be performed on the first gate dielectric layer, and in the case of the nitridation treatment and the annealing treatment, the execution sequence of the nitridation treatment and the annealing treatment may also be set according to actual requirements, which is not specifically limited herein.
In an example, in a case where the first fin and the second fin further each have a source region formation region and a drain region formation region, and the channel formation region is located between the source region formation region and the drain region formation region, after forming a first gate dielectric layer that covers at least an outer periphery of the channel formation region of the first fin and an outer periphery of the channel formation region of the second fin, and before removing a portion of the first gate dielectric layer located at an outer periphery of the channel formation region of the second fin, the method for manufacturing a semiconductor device may further include:
as shown in fig. 12 and 13, a sacrificial gate 20 and a sidewall 21 are formed on the portion of the first gate dielectric layer 19 located in the channel formation region 15 of the finfet and the channel of the second fin. The length extension direction of the sacrificial gate 20 is different from the length extension direction of the first fin portion and the second fin portion. The side walls 21 are at least located at two sides of the sacrificial gate 20 along the width direction. Specifically, the spacers 21 may be formed only on two sides of the sacrificial gate 20 in the width direction. Alternatively, the sidewall may surround the sidewall of the sacrificial gate.
In practical applications, a gate material for forming a sacrificial gate may be deposited over the first device region and the second device region by a chemical vapor deposition process. And then, etching the gate material by adopting a dry etching mode, and reserving a part of the gate material on a part of the first gate dielectric layer corresponding to the channel of the fin field effect transistor and the channel forming region of the second fin part to obtain the sacrificial gate. The gate material may be amorphous silicon, polysilicon, or other materials that are easily removed. As shown in fig. 12 and 13, after the sacrificial gate 20 is formed, the sidewall spacers 21 may be formed at least on the sidewalls of the sacrificial gate 20 in the above manner. The material of the sidewall spacers 21 may be an insulating material such as silicon nitride. The thickness of the side wall 21 can be set according to actual requirements.
It is noted that, as described above, the channel layer is located in the channel formation region of the second fin portion and then forms the channel of the gate-all-around transistor, so that in the process of forming the sacrificial gate and the sidewall, a portion of the first gate dielectric layer is located at the periphery of the channel formation region of the second fin portion, and under the action of the mask, the channel of the gate-all-around transistor formed subsequently can be protected from the etching, cleaning and other operations, thereby improving the yield of the gate-all-around transistor.
As described above, in the case where the first gate dielectric layer 19 is formed to cover the substrate 11, the first fin portion 131, and the second fin portion 141, and the first gate dielectric layer 19 is formed to cover at least the outer periphery of the channel formation region 15 of the first fin portion 131 and the outer periphery of the channel formation region 15 of the second fin portion 141, as shown in fig. 7 to 9, the method for manufacturing a semiconductor device further includes the steps of: the first gate dielectric layer 19 is removed from the source region formation region 16 and the drain region formation region 17 of the first fin 131 and the source region formation region 16 and the drain region formation region 17 of the second fin 141.
Specifically, the portions of the first gate dielectric layer on the source region forming region and the drain region forming region of the first fin portion and the source region forming region and the drain region forming region of the second fin portion may be removed by using a dry etching process or the like. The first gate dielectric layer can be etched in the process of respectively forming the sacrifice gate and the side wall by taking the sacrifice gate and the side wall as masks and etching the gate material for forming the sacrifice gate and the dielectric material for forming the side wall, so that the manufacturing process of the semiconductor device can be simplified.
Of course, the first gate dielectric layer may also be etched after the first gate dielectric layer is formed and before the sacrificial gate and the sidewall are formed. Or, after the first gate dielectric layer, the sacrificial gate and the side wall are formed, and before the source region and the drain region are formed, the first gate dielectric layer may be etched.
As shown in fig. 14, the source region formation region and the drain region formation region of the first fin portion are processed to form a source region 22 and a drain region 23 of the fin field effect transistor; and processing a source region forming region and a drain region forming region of the second fin portion to form a source region 22 and a drain region 23 of the gate-all-around transistor.
In an actual application process, a dry etching process or a wet etching process may be used to remove portions of the first fin portion located in the source region formation region and the drain region formation region, and to remove portions of the second fin portion located in the source region formation region and the drain region formation region. As shown in fig. 14, a source region 22 is epitaxially formed in the source region formation region and a drain region 23 is epitaxially formed in the drain region formation region by using epitaxial growth or the like, so that the source region 22 and the drain region 23 of the finfet and the gate-all-around transistor can be obtained at the same time. Or, ion implantation processing may be directly performed on the portion of the first fin portion located in the source region formation region and the drain region formation region, and on the portion of the second fin portion located in the source region formation region and the drain region formation region, so that the source region formation region forms a source region correspondingly, and the drain region formation region forms a drain region correspondingly.
As shown in fig. 15, a dielectric layer 24 is formed overlying the first element region 111 and the second element region 112. The top of the dielectric layer 24 is flush with the top of the sacrificial gate 20.
In practical applications, a physical vapor deposition or chemical vapor deposition process may be used to form a dielectric material covering the first device region and the second device region, and a chemical mechanical polishing process may be used to planarize the dielectric material to expose the top of the sacrificial gate. Wherein the portion of the dielectric material remaining over the first element region and the second element region forms a dielectric layer. The dielectric layer may be made of an insulating material such as silicon oxide.
As shown in fig. 16, the sacrificial gate is removed, so that the portion of the first gate dielectric layer 19 located at the periphery of the channel 26 of the finfet and the channel formation region 15 of the second fin is exposed, which facilitates the subsequent removal of the portion of the first gate dielectric layer 19 located at the periphery of the channel formation region 15 of the second fin 141. Specifically, the sacrificial gate may be selectively removed by photolithography and etching processes.
As shown in fig. 17 to 19, a portion of the first gate dielectric layer 19 located at the periphery of the channel formation region 15 of the second fin is removed. And the channel formation region 15 of the second fin portion is processed to obtain the channel 26 of the gate-all-around transistor.
It should be understood that the method for manufacturing the semiconductor device provided by the embodiment of the invention realizes that the formed fin field effect transistor has the gate dielectric layer with a thickness greater than that of the gate dielectric layer of the gate all around the transistor by depositing, selectively removing and the like to enable the remaining first gate dielectric layer to be only located at the periphery of the channel of the fin field effect transistor, and after the channel of the gate all around the transistor is formed, forming the second gate dielectric layer located on the remaining part of the first gate dielectric layer and forming the third gate dielectric layer around the periphery of the channel of the gate all around the transistor. Based on this, after the first gate dielectric layer is formed and the sacrificial gate is removed, the portion of the first gate dielectric layer located at the periphery of the channel formation region of the second fin portion needs to be removed. And the channel forming region of the second fin part is exposed so as to form a channel of the ring gate transistor based on the channel forming region of the second fin part.
Illustratively, the removing of the portion, located at the periphery of the channel formation region of the second fin portion, of the first gate dielectric layer may be implemented by: as shown in fig. 17, under the mask action of the mask layer 25, the portion of the first gate dielectric layer 19 located at the periphery of the channel formation region 15 of the second fin portion is etched, and the portion of the first gate dielectric layer 19 located at the periphery of the channel 26 of the finfet device is retained. The mask layer 25 covers the first device region 111.
Specifically, the material contained in the mask layer may be set according to actual requirements, as long as the material can be applied to the method for manufacturing a semiconductor device provided by the embodiment of the present invention. For example: the mask layer may be a photoresist mask layer, an amorphous silicon mask layer, a Spin On Carbon (SOC) mask layer, or an Advanced Patterning (APF) layer.
In an actual application process, the process adopted in the forming process of the mask layer can be selected according to the material of the mask layer. For example: in the case where the mask layer is a photoresist mask layer, a spin-on process may be used to form a photoresist layer over the first device region and the second device region. And then, exposing and developing the photoresist layer under the action of the mask plate, and removing the part of the photoresist layer on the second element area so that the part of the photoresist layer remained on the first element area forms a photoresist mask layer. Another example is: in the case where the mask layer is an amorphous silicon mask layer, an amorphous silicon layer may be formed over the first element region and the second element region by using a chemical vapor deposition process or the like. Followed by a photolithography process, and the use of NH 4And selectively removing the part of the amorphous silicon layer on the second element area by using the OH solution, so that the part of the amorphous silicon layer, which is remained on the first element area, forms an amorphous silicon mask layer. After the mask layer is formed, under the mask effect of the mask layer, the part, located at the periphery of the channel forming region of the second fin portion, of the first gate dielectric layer can be removed by adopting dry etching and other processes, and the remaining first gate dielectric layer is only located at the periphery of the channel of the fin field effect transistor.
For example, in a case where the first fin portion and the second fin portion each include the at least one stacked layer, the processing the channel formation region of the second fin portion to obtain the channel of the gate-all-around transistor may include: as shown in fig. 18, the portion of the sacrificial layer located in the channel formation region of the second fin is removed, so that the portion of the channel layer located in the channel formation region of the second fin forms a channel 26 of the gate-all-around transistor.
In an actual application process, under the mask action of the mask layer, after the part of the first gate dielectric layer, which is positioned at the periphery of the channel forming region of the second fin portion, is removed, the channel forming region of the second fin portion is exposed. Based on this, a wet etching process or a dry etching process may be used to remove the portion of the sacrificial layer located in the channel formation region of the second fin portion, so as to release the portion of the channel layer located in the channel formation region of the second fin portion, so that the channel of the gate-all-around transistor is formed. In the operation process, the channel of the fin field effect transistor is surrounded by the mask layer and the residual first gate dielectric layer, so that the sacrificial layer is not influenced when being positioned in the channel of the fin field effect transistor.
It is to be understood that, as shown in fig. 18, after the trench 26 of the gate-all-around transistor is obtained, the mask layer 25 is further formed on the remaining first gate dielectric layer 19, so that the channel formation region of the second fin portion is processed to obtain the trench 26 of the gate-all-around transistor, and before the subsequent operation, the manufacturing method of the semiconductor device further includes the steps of: as shown in fig. 19, the mask layer is removed.
Specifically, the process for removing the mask layer and the etchant used may be selected according to the material of the mask layer. For example: in the case where the mask layer is an advanced patterning layer or a spin-on carbon mask layer, the mask layer may be formed by a dry etching process, such as O2And removing the mask layer by using plasma. Another example is: in the case that the mask layer is an amorphous silicon mask layer, the wet etching process may be performed, for example, with NH4And removing the mask layer by using OH solution.
As shown in fig. 20, a second gate dielectric layer 27 is formed overlying the remaining portion of the first gate dielectric layer 19, and a third gate dielectric layer 28 is formed around the periphery of the trench 26 provided in the gate-all-around transistor. The thickness of the third gate dielectric layer 28 is less than the total thickness of the first gate dielectric layer 19 and the second gate dielectric layer 27.
Specifically, the materials contained in the second gate dielectric layer and the third gate dielectric layer, and the thicknesses of the two layers, may be set according to practical application scenarios. The second gate dielectric layer and the third gate dielectric layer may be made of the same material or different materials. The thicknesses of the second gate dielectric layer and the third gate dielectric layer may be equal or different, as long as the methods can be applied to the method for manufacturing the semiconductor device provided by the embodiment of the present invention.
In an actual application process, an appropriate manufacturing scheme and process can be selected according to the relationship between the materials contained in the second gate dielectric layer and the third gate dielectric layer and the layer thicknesses of the two layers.
For example: as shown in fig. 20, when the second gate dielectric layer 27 and the third gate dielectric layer 28 are made of the same material and have the same thickness, the second gate dielectric layer 27 and the third gate dielectric layer 28 are formed at the same time by using a process such as atomic layer deposition, so that the manufacturing process of the semiconductor device can be simplified.
Another example is: under the condition that the second gate dielectric layer and the third gate dielectric layer contain different materials, chemical vapor deposition and other processes can be adopted to form the second dielectric material layer which is positioned on the rest first gate dielectric layer and surrounds the periphery of the channel of the gate-all-around transistor. And then selectively removing the part of the second dielectric material layer surrounding the periphery of the channel of the gate-all-around transistor. And finally, forming a third dielectric material layer on the rest second dielectric material layer and on the periphery of the channel of the gate-all-around transistor, so that the third dielectric material layer can form a third gate dielectric layer around the part of the periphery of the channel of the gate-all-around transistor, and the rest second dielectric material layer and the part of the third dielectric material layer above the second dielectric material layer form a second gate dielectric layer. Of course, in the case where a part of the material contained in the third gate dielectric layer is the same as the material contained in the second gate dielectric layer, the third dielectric material layer may be selectively formed around the outer periphery of the channel of the gate-all-around transistor. And forming a second dielectric material layer on the third dielectric material layer and the rest of the first gate dielectric layer so as to obtain a second gate dielectric layer and a third gate dielectric layer.
The second gate dielectric layer and the third gate dielectric layer may be made of HfO2、ZrO2、TiO2Or Al2O3And materials with higher dielectric constants.
In addition, when the thicknesses of the second gate dielectric layer and the third gate dielectric layer are different, the manufacturing process may be performed by referring to the above-mentioned forming scheme, and details are not described here.
In one example, after forming the second gate dielectric layer on the remaining portion of the first gate dielectric layer and forming the third gate dielectric layer around the periphery of the channel of the gate-all-around transistor, the method for manufacturing the semiconductor device further comprises the steps of: as shown in fig. 21, a first gate electrode 29 is formed on the second gate dielectric layer 27 to obtain a finfet 31; and a second gate 30 is formed on the third gate dielectric layer 28 to obtain a gate-all-around transistor 32.
The first gate and the second gate may be made of the same material or different materials. Specifically, the materials contained in the first gate and the second gate may be set according to practical application scenarios, and are not specifically limited herein.
In practical applications, in the case that the first gate electrode and the second gate electrode contain the same material, the first gate electrode and the second gate electrode may be formed simultaneously by using a chemical vapor deposition process or the like. Under the condition that the materials of the first gate and the second gate are different, the manufacturing can be performed by referring to the forming schemes of the second gate dielectric layer and the third gate dielectric layer, and details are not repeated here.
In addition, a first gate dielectric layer and a second gate dielectric layer are formed on the periphery of a channel of the fin field effect transistor. And a third gate dielectric layer is formed on the periphery of a channel of the gate-all-around transistor. And the thickness of the third gate dielectric layer is smaller than the total thickness of the first gate dielectric layer and the second gate dielectric layer. Therefore, the input/output device in the integrated circuit is provided with the thicker gate dielectric layer, and the core device is provided with the thinner gate dielectric layer, so that the integration of the input/output device and the core device can be realized by adopting the manufacturing method of the semiconductor device provided by the embodiment of the invention. The fin field effect transistor is an input/output device. The gate transistor is a core device.
As can be seen from the above, when the method for manufacturing a semiconductor device is used for manufacturing an input/output device and a core device, the input/output device having the device structure of the fin field effect transistor and the core device having the device structure of the gate-all-around transistor can be formed, so that the problem that the subsequent metal gate material cannot be filled or can only be partially filled due to the filling of the thick oxide layer caused by the smaller distance between channels when the input/output device also adopts the gate-all-around transistor structure due to the larger thickness of the gate dielectric layer of the input/output device can be solved, the problem of poor compatibility with the core device can be solved, and the integration difficulty of the core device and the input/output device can be reduced.
In the above description, details of the techniques such as patterning and etching of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims (11)

1. A method of manufacturing a semiconductor device, comprising:
providing a substrate; the substrate has a first element region and a second element region;
forming a first fin part and a second fin part which have the same structure on the substrate; the first fin portion is located on the first element region; the second fin portion is located on the second element region; the first fin portion and the second fin portion are provided with channel forming regions;
Forming a first gate dielectric layer at least covering the periphery of a channel forming region of the first fin part and the periphery of a channel forming region of the second fin part, wherein the part of the first fin part, which is positioned in the channel forming region, forms a channel of the fin field effect transistor;
removing the part, located on the periphery of the channel forming region, of the second fin part, of the first gate dielectric layer; processing the channel forming region of the second fin part to obtain a channel of the gate-all-around transistor;
forming a second gate dielectric layer on the rest part of the first gate dielectric layer and a third gate dielectric layer which is formed to surround the periphery of a channel of the gate-all-around transistor; the thickness of the third gate dielectric layer is smaller than the total thickness of the first gate dielectric layer and the second gate dielectric layer.
2. The method of manufacturing the semiconductor device according to claim 1, wherein the fin field effect transistor is an input/output device; the gate all around transistor is a core device.
3. The method for manufacturing the semiconductor device according to claim 1, wherein the second gate dielectric layer and the third gate dielectric layer comprise the same material; and/or the presence of a gas in the gas,
The second gate dielectric layer and the third gate dielectric layer are equal in layer thickness.
4. The method for manufacturing the semiconductor device according to claim 1, wherein the removing of the portion of the first gate dielectric layer on the periphery of the channel formation region of the second fin portion is:
under the mask action of a mask layer, etching the part, located on the periphery of a channel forming region, of the first gate dielectric layer, located on the periphery of a channel formed by the second fin part, and reserving the part, located on the periphery of a channel, of the fin field effect transistor, of the first gate dielectric layer; the mask layer covers the first element area;
after the channel forming region of the second fin portion is processed to obtain a channel of the gate-all-around transistor, before forming a second gate dielectric layer located on the remaining portion of the first gate dielectric layer and forming a third gate dielectric layer surrounding the periphery of the channel of the gate-all-around transistor, the method for manufacturing the semiconductor device further includes:
and removing the mask layer.
5. The method of claim 4, wherein the mask layer is a photoresist mask layer, an amorphous silicon mask layer, a spin-on carbon mask layer, or an advanced patterning layer.
6. The method of manufacturing a semiconductor device according to claim 1, wherein the first fin portion and the second fin portion each further have a source region formation region and a drain region formation region; the channel forming region is positioned between the source region forming region and the drain region forming region;
after the first gate dielectric layer at least covering the peripheries of the channel forming regions of the first fin portion and the second fin portion is formed, and before the first gate dielectric layer is removed from the periphery of the channel forming region of the second fin portion, the method for manufacturing the semiconductor device further comprises:
forming a sacrificial gate and a side wall on the part of the first gate dielectric layer, which is positioned in a channel forming region of the fin field effect transistor and the channel forming region of the second fin part; the length extension direction of the sacrificial gate is different from the length extension direction of the first fin part and the length extension direction of the second fin part; the side walls are at least positioned at two sides of the sacrificial gate along the width direction;
processing a source region forming region and a drain region forming region of the first fin portion to form a source region and a drain region of the fin field effect transistor; processing a source region forming region and a drain region forming region of the second fin portion to form a source region and a drain region of the gate-all-around transistor;
Forming a dielectric layer overlying the first element region and the second element region; the top of the dielectric layer is flush with the top of the sacrificial gate;
and removing the sacrificial gate.
7. The manufacturing method of a semiconductor device according to claim 6, wherein the first gate dielectric layer is a gate oxide layer;
after forming the first gate dielectric layer at least covering the periphery of the channel forming region of the first fin and the periphery of the channel forming region of the second fin, before forming the sacrificial gate and the sidewall on the portion, located on the channel forming region of the fin field effect transistor and the channel forming region of the second fin, of the first gate dielectric layer, the manufacturing method of the semiconductor device further includes:
and performing nitridation treatment and/or annealing treatment on the first gate dielectric layer.
8. The method for manufacturing a semiconductor device according to claim 7, wherein the nitriding treatment is performed under the following conditions: under the nitrogen environment, the processing power is 500W-2000W; and/or the presence of a gas in the gas,
the treatment conditions of the annealing treatment are as follows: adopting nitrogen as protective gas; the annealing temperature is 400-850 ℃; the treatment time is 10 s-1 min.
9. The method for manufacturing the semiconductor device according to claim 6, wherein the first gate dielectric layer covers the substrate, the first fin portion and the second fin portion;
after the first gate dielectric layers are formed at least covering the peripheries of the channel forming regions of the first fin parts and the peripheries of the channel forming regions of the second fin parts, processing a source region forming region and a drain region forming region of the first fin part to form a source region and a drain region of the fin field effect transistor; and processing a source region forming region and a drain region forming region of the second fin portion, wherein before the source region and the drain region of the gate-all-around transistor are formed, the manufacturing method of the semiconductor device further comprises the following steps:
and removing the first gate dielectric layer on the source region forming region and the drain region forming region of the first fin part and on the source region forming region and the drain region forming region of the second fin part.
10. The method of manufacturing a semiconductor device according to claim 1, wherein the first fin portion and the second fin portion each include at least one stacked layer along a thickness direction of the substrate; each of the stacked layers includes a sacrificial layer and a channel layer on the sacrificial layer;
Processing the channel forming region of the second fin portion to obtain a channel of the gate-all-around transistor, including:
and removing the part of the sacrificial layer, which is positioned in the channel forming region of the second fin part, so that the part of the channel layer, which is positioned in the channel forming region of the second fin part, forms a channel of the gate-all-around transistor.
11. A method for manufacturing a semiconductor device according to any one of claims 1 to 10, wherein shallow trench isolation is formed over the substrate; the first fin portion and the second fin portion are exposed outside the shallow trench isolation; and/or the presence of a gas in the atmosphere,
after the second gate dielectric layer located on the remaining part of the first gate dielectric layer and the third gate dielectric layer formed around the periphery of the channel of the gate-all-around transistor are formed, the manufacturing method of the semiconductor device further comprises the following steps:
forming a first grid electrode on the second grid dielectric layer to obtain a fin field effect transistor; and forming a second grid electrode on the third grid dielectric layer to obtain the gate-all-around transistor.
CN202210167255.1A 2022-02-23 2022-02-23 Method for manufacturing semiconductor device Pending CN114678329A (en)

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