CN115036357A - Ring gate transistor and manufacturing method thereof - Google Patents
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- CN115036357A CN115036357A CN202210508772.0A CN202210508772A CN115036357A CN 115036357 A CN115036357 A CN 115036357A CN 202210508772 A CN202210508772 A CN 202210508772A CN 115036357 A CN115036357 A CN 115036357A
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H01L29/0843—Source or drain regions of field-effect devices
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract
The invention discloses a gate-all-around transistor and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for improving the working performance of the gate-all-around transistor under the condition of inhibiting the parasitic channel electric leakage of the gate-all-around transistor. The gate-all-around transistor and the manufacturing method thereof comprise the following steps: the semiconductor device comprises a substrate, a stacking structure, a gate stack, an isolation side wall and a leakage suppression structure. The stacked structure is formed on a substrate. The stacked structure includes a source region, a drain region, and at least one layer of nanowires or sheets located between the source region and the drain region. The gate stack surrounds the periphery of the at least one layer of nanowires or sheets. The isolation side walls are at least formed on two sides of the gate stack along the length direction. The leakage current suppressing structure is formed on the substrate. The leakage suppression structure is positioned below the at least one layer of nano-wire or sheet and below the part of the isolation side wall corresponding to the at least one layer of nano-wire or sheet. The leakage current suppressing structure is doped with impurities having a conductivity type opposite to that of the gate-all-around transistor. The bottom of each of the source region and the drain region is at least flush with the bottom of the leakage suppression structure.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a gate-all-around transistor and a manufacturing method thereof.
Background
With the development of semiconductor technology, gate-all-around transistors are produced in time. Because the gate stack of the gate-all-around transistor is formed on the top and the side wall of the channel and the bottom of the channel, the gate-all-around transistor has stronger gate control capability and is beneficial to inhibiting short channel effect compared with a planar transistor and a fin field effect transistor.
However, the conventional manufacturing method suppresses the parasitic channel leakage of the gate-all-around transistor and also causes the degradation of the operating performance of the gate-all-around transistor.
Disclosure of Invention
The invention aims to provide a gate all-around transistor and a manufacturing method thereof, which are used for improving the working performance of the gate all-around transistor under the condition of inhibiting the parasitic channel leakage of the gate all-around transistor.
In order to achieve the above object, the present invention provides a gate-all-around transistor comprising: a substrate, a first electrode and a second electrode,
and a stacked structure formed on the substrate. The stacked structure comprises a source region, a drain region and at least one layer of nanowire or sheet positioned between the source region and the drain region, wherein the at least one layer of nanowire or sheet is respectively contacted with the source region and the drain region, and a gap is formed between the at least one layer of nanowire or sheet and the substrate.
And the grid stack surrounds the periphery of the at least one layer of nanowire or chip.
And the isolation side walls are at least formed on two sides of the gate stack along the length direction.
And a leakage suppression structure formed on the substrate. The leakage suppression structure is positioned below the at least one layer of nano-wire or sheet and below the part of the isolation side wall corresponding to the at least one layer of nano-wire or sheet. The leakage suppression structure is doped with impurities having a conductivity type opposite to that of the gate-all-around transistor. The bottoms of the source region and the drain region are at least flush with the bottom of the leakage suppression structure.
Compared with the prior art, the gate-all-around transistor provided by the invention has the advantage that the leakage current suppression structure is formed on the substrate. And the leakage suppression structure is positioned below the at least one layer of nanowire or sheet and below the part of the isolation side wall corresponding to the at least one layer of nanowire or sheet. In other words, the leakage current suppressing structure is located between the at least one layer of the nanowire or the sheet and the substrate, and between the portions of the isolation side walls corresponding to the nanowire or the sheet and the substrate. In this case, the above-described leakage suppressing structure may separate the gate stack from the substrate even if there is a gap between the substrate and the nanowire or chip, and the gate stack surrounds the periphery of at least one layer of the nanowire or chip through the gap. In addition, the leakage current of a parasitic channel in the gate-all-around transistor can be inhibited by utilizing a reverse biased PN junction because the leakage current inhibiting structure is doped with impurities with the conductivity type opposite to that of the gate-all-around transistor.
In addition, the leakage current suppressing structure is formed on the substrate, that is, the leakage current suppressing structure is a structure additionally formed on the substrate. And, the leakage current suppressing structure is located below the nanowire or the sheet. Based on this, in the process of actually manufacturing the gate-all-around transistor provided by the present invention, before forming the channel layer for manufacturing the nanowire or the sheet on the substrate, the leakage current suppressing structure may be obtained by forming the leakage current suppressing layer for manufacturing the leakage current suppressing structure on the substrate in advance and etching the leakage current suppressing layer. In this case, since the channel layer is formed after the leakage current suppressing layer, when impurities are doped into the leakage current suppressing layer, the impurities do not enter the channel layer, so that the impurities do not exist in the channel layer, and a nanowire or a chip formed on the basis of the channel layer is ensured to have high carrier mobility. Meanwhile, the quality of the channel layer cannot be influenced due to impurity doping, and high-quality nanowires or sheets can be obtained, so that the working performance of the gate-all-around transistor can be improved.
Furthermore, the bottom of the source region and the bottom of the drain region of the gate-all-around transistor are at least flush with the bottom of the leakage suppression structure. That is, the bottom heights of the source region and the drain region are equal to or less than the bottom height of the leakage suppressing structure. At the moment, the source region and the drain region are only adjacent to the leakage suppression structure in a plane parallel to the surface of the substrate and are not adjacent to each other along the thickness direction of the substrate, so that the source region and the drain region can be prevented from forming highly doped PN junctions distributed along the thickness direction of the substrate with the leakage suppression structure, the leakage of the source region and the drain region is prevented from increasing, and the gate-all-around transistor is ensured to have good conductivity.
The invention also provides a manufacturing method of the gate all-around transistor, which comprises the following steps:
a substrate is provided.
And forming a stacked structure, an isolation side wall, a leakage suppression structure and a gate stack on the substrate. The stacked structure comprises a source region, a drain region and at least one layer of nanowire or sheet positioned between the source region and the drain region, wherein the at least one layer of nanowire or sheet is respectively contacted with the source region and the drain region, and a gap is formed between the at least one layer of nanowire or sheet and the substrate. The gate stack surrounds the periphery of the at least one layer of nanowires or sheets. The isolation side walls are at least formed on two sides of the gate stack along the length direction. The leakage suppression structure is positioned below the at least one layer of nano-wire or sheet and below the part of the isolation side wall corresponding to the at least one layer of nano-wire or sheet. The leakage current suppressing structure is doped with impurities having a conductivity type opposite to that of the gate-all-around transistor. The bottom of each of the source region and the drain region is at least flush with the bottom of the leakage suppression structure.
Compared with the prior art, the manufacturing method of the gate-all-around transistor provided by the invention has the same beneficial effects as those of the gate-all-around transistor provided by the invention, and the details are not repeated here.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 (1) is a cross-sectional view of a structure obtained after a punch-through preventing implantation process is performed on a fin-shaped structure; fig. 1 (2) is a cross-sectional view of a structure after a gate-all-around transistor is formed based on a fin structure;
fig. 2 is a schematic structural diagram of a leakage current suppressing layer and at least one stacked layer formed on a substrate according to an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating a first structure after forming a fin portion according to an embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating a second structure after forming a fin portion according to an embodiment of the present invention;
FIG. 5 is a cross-sectional view of a structure along direction B-B' after forming a fin portion according to an embodiment of the present invention;
FIGS. 5 are sectional views of two structures along the direction A-A' after forming fin portions at portions (2) and (3) in the embodiment of the present invention;
parts (1), (2) and (3) in fig. 6 are schematic diagrams of three structures after the shallow trench isolation structure in the embodiment of the invention;
fig. 7 is a schematic structural diagram after a sacrificial gate and an isolation sidewall are formed in the embodiment of the present invention;
FIG. 8 is a cross-sectional view of the structure of FIG. 7 taken along line B-B';
fig. 9 shows three schematic structural diagrams after (1), (2), and (3) are the portions of the fin portion located in the source formation region and the drain formation region in the embodiment of the present invention, and the fin portion is etched at least down to the leakage suppressing layer after the patterning process to obtain a leakage suppressing structure;
FIG. 10 is a schematic view of a structure after forming a notch according to an embodiment of the present invention;
FIG. 11 is a schematic structural diagram of an embodiment of the present invention after forming an inner sidewall;
FIGS. 12 (1) and (2) are sectional views of two structures along the direction B-B' after forming source and drain regions according to an embodiment of the present invention;
FIG. 13 is a cross-sectional view of a structure along the direction B-B' after forming a dielectric layer according to an embodiment of the present invention;
FIG. 14 is a schematic structural diagram illustrating the structure after the sacrificial gate is removed according to an embodiment of the present invention;
FIG. 15 is a cross-sectional view of the structure along the direction B-B' after removing the portion of the sacrificial layer located in the release region according to the embodiment of the present invention;
parts (1) and (2) in fig. 16 are cross-sectional views of two structures of a gate-all-around transistor along the direction B-B' according to an embodiment of the present invention;
FIG. 17 is a cross-sectional view of a third gate-all-around transistor along the direction B-B' according to an embodiment of the present invention;
fig. 18 is a flowchart of a method for manufacturing a gate all around transistor according to an embodiment of the present invention.
Reference numerals: 11 is a substrate, 12 is a leakage inhibiting layer, 121 is a doping layer, 122 is an intrinsic layer, 13 is a lamination layer, 131 is a sacrificial layer, 132 is a channel layer, 14 is a fin portion, 15 is a shallow trench isolation structure, 16 is a source forming region, 17 is a drain forming region, 18 is a transition region, 19 is a sacrificial gate, 20 is an isolation side wall, 21 is a leakage inhibiting structure, 211 is a doping portion, 212 is an intrinsic portion, 22 is a notch, 23 is an inner side wall, 24 is a source region, 25 is a drain region, 26 is a dielectric layer, 27 is a release region, 28 is a nanowire or a chip, 29 is a fin-shaped gate stack, 291 is a gate dielectric layer, 292 is a gate electrode, 30 is a structure, 31 is a barrier layer, and 32 is a central region.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed. In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise. The meaning of "a number" is one or more unless specifically limited otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood according to specific situations by those of ordinary skill in the art.
With the development of semiconductor technology, gate-all-around transistors are produced in time. Because the gate stack structure of the gate-all-around transistor is not only formed on the top and the side wall of the channel, but also formed at the bottom of the channel, compared with a planar transistor and a fin field effect transistor, the gate-all-around transistor has stronger gate control capability, is beneficial to inhibiting short channel effect, and has higher working performance.
In the actual process of manufacturing the gate-all-around transistor, at least one layer stack needs to be formed on the substrate. Each stack layer includes a sacrificial layer, and a channel layer on the sacrificial layer. And etching down to a portion of the substrate from the top of the stack to form a fin structure. As shown in fig. 1, after forming the shallow trench isolation structure 15 on the exposed portion of the substrate 11 outside the fin structure 30, impurity ions having a conductivity type opposite to that of the pass-through prevention implantation are implanted at least into the fin structure 30 to form a blocking layer 31 in a middle-lower portion of the fin structure 30 (i.e., a portion of the substrate 11 included in the fin structure 30 that is etched), so as to suppress leakage of a parasitic channel by using the highly doped blocking layer 31.
However, before forming the barrier layer, an etched channel layer is formed on the substrate, and the etched channel layer is a film for manufacturing a nanowire or a sheet of a gate-all-around transistor. In this case, in the process of forming the barrier layer by implanting impurity ions into the middle and lower portions of the fin structure through the punch-through prevention implantation process, the implanted impurity ions may exist in the etched channel layer, resulting in a decrease in carrier mobility in the nanowire or the chip included in the gate-all-around transistor. Further, since it is necessary to form a barrier layer in the middle-lower portion of the fin structure, the implantation energy of impurity ions is large. Therefore, when the punch-through prevention injection process is executed, the etched channel layer may be damaged, so that the quality of the nanowire or the sheet is influenced, and the conductivity of the gate-all-around transistor is reduced.
In addition, in the case where the gate all around transistor has a wide channel width, it is difficult to solve the problem of parasitic channel leakage in the gate all around transistor through the above-described punch-through prevention implantation process. Specifically, as shown in fig. 1, in the process of manufacturing the gate-all-around transistor, since the gate-all-around transistor has a wider channel width, the fin structure 30 formed on the substrate 11 also has a wider width. Based on this, when impurity ions are implanted into the fin structure 30 by the punch-through prevention implantation process, it is difficult for the impurity ions to enter the central region 32 of the fin structure 30 in the width direction thereof (the direction parallel to the a-a' direction), that is, the central region 32 of the fin structure 30 in the width direction thereof does not completely form the barrier layer 31. In this case, after a suitable voltage is applied to the gate stack 29 of the gate-all-around transistor, the source region and the drain region can be conducted through the channel, and the central region 32 has a problem of parasitic channel leakage, thereby reducing the operating performance of the gate-all-around transistor.
In order to solve the above technical problem, embodiments of the present invention provide a gate all around transistor and a method for manufacturing the same. In the gate-all-around transistor provided by the embodiment of the invention, the leakage suppression structure is positioned between at least one layer of nanowire or sheet and the substrate, and between the part of the isolation side wall corresponding to the nanowire or sheet and the substrate, so as to suppress leakage of a parasitic channel by using a reverse-biased PN junction. And the leakage current inhibiting structure is a structure additionally formed on the substrate, and is positioned below the nanowire or the chip, so that impurities are prevented from entering the nanowire or the chip when the impurities are doped in a leakage current inhibiting layer for manufacturing the leakage current inhibiting structure, and the nanowire or the chip is ensured to have high carrier mobility.
As shown in fig. 16 and 17, an embodiment of the present invention provides a gate-all-around transistor. The gate-all-around transistor comprises a substrate 11, a stacked structure, a gate stack 29, an isolation side wall 20 and a leakage suppression structure 21.
As shown in fig. 16 and 17, the above-described stacked structure is formed on the substrate 11. The stacked structure comprises a source region 24, a drain region 25, and at least one layer of nanowires or flakes 28 located between the source region 24 and the drain region 25, the at least one layer of nanowires or flakes 28 being in contact with the source region 24 and the drain region 25, respectively, with a gap between the at least one layer of nanowires or flakes 28 and the substrate 11. The gate stack 29 surrounds the periphery of the at least one layer of nanowires or flakes 28. The isolation spacers 20 are formed at least at both sides of the gate stack 29 in the length direction. The leakage current suppressing structure 21 is formed on the substrate 11. The leakage suppressing structure 21 is located under the at least one layer of nanowires or sheets 28 and under the portions of the isolation sidewall 20 corresponding to the at least one layer of nanowires or sheets 28. The leakage suppressing structure 21 is doped with impurities having a conductivity type opposite to that of the gate-all-around transistor. The bottom of each of the source region 24 and the drain region 25 is at least flush with the bottom of the leakage-suppressing structure 21.
Specifically, the substrate may be any semiconductor substrate such as a silicon substrate, a silicon germanium substrate, or a germanium substrate. Also, the substrate may have an active region and an isolation region. Wherein, the active region is doped with impurities with the conductivity type opposite to that of the gate-all-around transistor. For example: in the case where the gate-all-around transistor is an NMOS transistor, the active region is doped with a P-type impurity (e.g., boron). Another example is: in the case where the gate-all-around transistor is a PMOS transistor, the active region is doped with an N-type impurity (e.g., phosphorus). The leakage current suppressing structure and the stacking structure are formed on the active region.
In some cases, as shown in fig. 11, the gate-all-around transistor may further include a shallow trench isolation structure 15 formed on the isolation region. The top height of the shallow trench isolation structure 15 is less than or equal to the top height of the leakage suppression structure 21. In this case, the shallow trench isolation structure 15 may isolate the source and drain regions of the gate-all-around transistor provided by the embodiment of the present invention from the source and drain regions of other transistors formed on the substrate 11, preventing electrical connection with each other. Specifically, the thickness of the shallow trench isolation structure may be set according to actual requirements. The shallow trench isolation structure can be made of SiN or Si 3 N 4 、SiO 2 Or an insulating material such as SiCO.
For the stacked structure, the material of the source region, the drain region, and the nanowire or sheet included in the stacked structure may be silicon, silicon germanium, or other semiconductor materials. The number of layers of the nanowires or the sheets included in the stacked structure may be set according to actual requirements, and is not specifically limited herein.
As shown in fig. 16, the gate-all-around transistor includes a source region 24 and a drain region 25, both of which have bottoms at least flush with the bottom of the leakage suppression structure 21. That is, the bottom heights of the source region 24 and the drain region 25 may be equal to the bottom height of the leakage suppressing structure 21, and may be smaller than the bottom height of the leakage suppressing structure 21. In both cases, the source region 24 and the drain region 25 are only adjacent to the leakage inhibiting structure 21 in a plane parallel to the surface of the substrate 11, but not adjacent to each other along the thickness direction of the substrate 11, i.e., the source region 24 and the drain region 25 can be prevented from forming highly doped PN junctions distributed along the thickness direction of the substrate 11 with the leakage inhibiting structure 21, thereby avoiding increasing the leakage of the source region 24 and the drain region 25 and improving the conductivity of the gate-all-around transistor.
For the gate stack, as shown in fig. 16 and 17, the gate stack 29 may include a gate dielectric layer 291, and a gate electrode 292 formed on the gate dielectric layer 291. The gate dielectric layer 291 surrounds the periphery of the nanowire or chip 28. Alternatively, the gate dielectric layer may be additionally formed on the substrate (or the shallow trench isolation structure) and the portion of the leakage current suppressing structure corresponding to the gate forming region. The thicknesses of the gate dielectric layer and the gate electrode may be set according to actual requirements, and are not specifically limited herein. The gate dielectric layer may be made of insulating material with low dielectric constant such as silicon oxide or silicon nitride, or may be made of HfO 2 、ZrO 2 、TiO 2 Or Al 2 O 3 And insulating materials with higher dielectric constants. The grid can be made of polycrystalline silicon, TiN, TaN or TiSiN and other conductive materials.
For the above-mentioned isolation spacers, as shown in fig. 14, 16 and 17, the isolation spacers 20 may be formed only on both sides of the gate stack 29 in the length direction (the direction is parallel to the B-B' direction). Alternatively, the isolation sidewall may surround the circumference of the gate stack. Wherein, the thickness and the material of isolation side wall can set up according to actual demand. For example: the isolation side wall may be made of an insulating material such as silicon nitride. Specifically, as shown in fig. 14, 16 and 17, the portion of the isolation sidewall 20 corresponding to the nanowire or chip 28 is the portion of the isolation sidewall 20 formed on the top nanowire or chip 28. In addition, as shown in fig. 10 and 11, the isolation sidewall spacers 20 may also have portions formed on the substrate 11 (or the shallow trench isolation structure 15).
For the leakage current suppressing structure, the distribution of the impurity doped in the leakage current suppressing structure can be set according to actual requirements. In one example, as shown in fig. 16, all regions of the leakage current suppressing structure 21 may be doped with the above-described impurity along the thickness direction of the substrate 11. In another example, along the thickness direction of the substrate 11, there may be a portion of the leakage current suppressing structure 21 that is doped with the above-mentioned impurity, and another portion that is not doped with the above-mentioned impurity. In this case, the number and arrangement of the regions doped with the impurities and the regions not doped with the impurities may also be set according to actual requirements. For example: as shown in fig. 17, along the thickness direction of the substrate 11, the leakage suppressing structure 21 may include a doped portion 211, and an intrinsic portion 212 located on the doped portion 211. The doped portion 211 is doped with the above-mentioned impurities. Another example is: the leakage suppression structure may include a first intrinsic portion, a second intrinsic portion, and a doped portion between the first intrinsic portion and the second intrinsic portion along a thickness direction of the substrate. The doped portion is doped with the impurity. In both cases, the portion of the leakage suppression structure that is not doped with impurities is closer to the nanowire or the sheet. Based on this, as shown in fig. 2 to 17, in the process of manufacturing the gate-all-around transistor provided by the embodiment of the present invention, since the leakage current suppressing structure 21 is located below at least one layer of the nanowire or the sheet 28, the sacrificial layer 131 and the channel layer 132 for manufacturing the nanowire or the sheet 28 are formed on the leakage current suppressing layer 12 for manufacturing the leakage current suppressing structure 21. At this time, after the formation of the leakage current suppression layer 12, and the at least one sacrificial layer 131 and the at least one channel layer 132 which are alternately distributed, the presence of the intrinsic layer 122 in the leakage current suppression layer 12 can prevent the impurity in the impurity-doped layer 121 doped with the impurity in the leakage current suppression layer 12 from being out-diffused into the sacrificial layer 131 and the channel layer 132 when a subsequent high temperature process such as annealing is performed, thereby further ensuring that the carrier mobility of the nanowire or chip 28 formed by the channel layer 132 is not affected by the impurity, and improving the conductivity of the ring gate transistor.
As for the impurity type doped in the leakage suppressing structure, it can be set with reference to the conductivity type of the gate-all-around transistor. For example: in the case where the gate all around transistor is a PMOS transistor, the leakage suppressing structure is doped with N-type impurities. Another example is: in the case that the gate all around transistor is an NMOS transistor, the leakage current suppressing structure is doped with P-type impurities. In addition, the doping concentration of the doping in the leakage suppression structure can be set according to practical application scenes. For example: the doping concentration of impurities in the leakage inhibiting structure is 1E18cm -3 To 2E19cm -3 . Specifically, the doping concentration is a doping concentration in a region doped with an impurity in the leakage current suppressing structure. For example: in the case where the leakage suppressing structure includes the above-described doped portion and intrinsic portion, the doped portionThe doping concentration of the internal impurity is 1E18cm -3 To 2E19cm -3 。
As for the thickness and the material of the leakage current suppression structure, they may be set according to actual requirements, as long as they can suppress the parasitic channel leakage in the gate-all-around transistor and can be applied to the gate-all-around transistor provided in the embodiments of the present invention. For example: the thickness of the leakage suppressing structure may be 10nm to 40 nm. For example: the leakage current suppressing structure may be made of Si 1-x Ge x And a semiconductor material; wherein x is more than or equal to 0 and less than or equal to 1 (such as Si and Si) 0.3 Ge 0.7 Or Ge, etc.).
As can be seen from the above, as shown in fig. 16 and 17, in the gate-all-around transistor provided in the embodiment of the present invention, the leakage current suppressing structure 21 is formed on the substrate 11. The leakage suppression structure 21 is located below the at least one layer of nanowires or sheets 28 and below the portions of the isolation sidewall 20 corresponding to the at least one layer of nanowires or sheets 28. In other words, the leakage suppressing structure 21 is located between the at least one layer of nanowires or sheets 28 and the substrate 11, and between the portions of the isolation sidewalls 20 corresponding to the nanowires or sheets 28 and the substrate 11. In this case, even if there is a gap between the substrate 11 and the nanowire or chip 28, and the gate stack 29 surrounds the periphery of at least one layer of the nanowire or chip 28 through the gap, the above-described leakage current suppressing structure 21 may separate the gate stack 29 from the substrate 11. In addition, since the leakage suppressing structure 21 is doped with an impurity having a conductivity type opposite to that of the gate-all-around transistor, leakage of a parasitic channel can be suppressed by a reverse-biased PN junction.
In addition, as shown in fig. 2 to 17, the leakage current suppressing structure 21 is formed on the substrate 11, that is, the leakage current suppressing structure 21 is a structure additionally formed on the substrate 11. Also, the leakage suppressing structure 21 is located below the nanowire or the sheet 28. Based on this, in the process of actually manufacturing the gate-all-around transistor provided by the embodiment of the present invention, before the channel layer 132 for manufacturing the nanowire or the sheet 28 is formed on the substrate 11, the leakage inhibiting structure 21 may be obtained by forming the leakage inhibiting layer 12 for manufacturing the leakage inhibiting structure 21 on the substrate 11 in advance and etching the leakage inhibiting layer 12. In this case, since the channel layer 132 is formed after the leakage suppression layer 12, impurities do not enter the channel layer 132 when the leakage suppression layer 12 is doped with the impurities, which is advantageous in that the channel layer 132 does not have the above-mentioned impurities therein, and a high carrier mobility is ensured in the nanowire or chip 28 formed based on the channel layer 132. Meanwhile, the quality of the channel layer 132 is not affected by doping impurities, which is beneficial to obtaining high-quality nanowires or chips 28 and further beneficial to improving the working performance of the gate-all-around transistor.
In one example, as shown in fig. 16 and 17, the gate-all-around transistor may further include inner sidewalls 23. Along the length direction of the gate stack 29, the inner sidewall 23 is located between the gate stack 29 and the source region 24, and between the gate stack 29 and the drain region 25. In this case, as shown in fig. 11 to 17, the presence of the inner sidewall 23 is advantageous to prevent the gate stack 29, which is subsequently surrounded on the periphery of the nanowire or chip 28, from being formed on the portion of the nanowire or chip 28 covered by the sidewall, so as to control the length of the gate stack 29.
The inner side wall may be made of an insulating material such as silicon oxide or silicon nitride. The specific thickness of the inner side wall can be set according to actual requirements.
As shown in fig. 18, an embodiment of the invention provides a method for manufacturing a gate-all-around transistor. The manufacturing process will be described below based on the perspective and sectional views of the operation shown in fig. 2 to 17. Specifically, the method for manufacturing the gate-all-around transistor comprises the following steps:
first, a substrate is provided. The substrate may be a semiconductor substrate such as a silicon substrate or a silicon germanium substrate.
As shown in fig. 2 to 17, a stacked structure, isolation spacers 20, a leakage suppression structure 21, and a gate stack 29 are formed on the substrate 11. The stacked structure includes a source region 24, a drain region 25, and at least one layer of nanowires or sheets 28 located between the source region 24 and the drain region 25, the at least one layer of nanowires or sheets 28 being in contact with the source region 24 and the drain region 25, respectively, with a gap between the at least one layer of nanowires or sheets 28 and the substrate 11. The gate stack 29 surrounds the periphery of at least one layer of nanowires or sheets 28. The isolation spacers 20 are formed at least at both sides of the gate stack 29 in the length direction. The leakage suppression structure 21 is located under the at least one layer of nanowires or sheets 28 and under the portion of the isolation sidewall 20 corresponding to the at least one layer of nanowires or sheets 28. The leakage suppressing structure 21 is doped with impurities having a conductivity type opposite to that of the gate-all-around transistor. The bottom of each of the source region 24 and the drain region 25 is at least flush with the bottom of the leakage suppressing structure 21.
Specifically, the information such as the specific materials and specifications of the stack structure, the isolation sidewall, the leakage suppression structure, and the gate stack may refer to the foregoing, and is not described herein again.
In one example, the substrate has an active region and an isolation region. In this case, the above-described forming of the leakage suppressing structure on the substrate may include the steps of:
as shown in fig. 2, a leakage current suppressing layer 12 and at least one stacked layer 13 are formed so as to cover a substrate 11. Each of the laminated layers 13 includes a sacrificial layer 131, and a channel layer 132 on the sacrificial layer 131.
Specifically, the leakage current suppressing layer is a film layer used for manufacturing the leakage current suppressing structure, so that information such as the thickness, material, and doping condition of the leakage current suppressing layer can be determined by referring to the information about the leakage current suppressing structure described above. For example: as shown in fig. 2, in the case where the leakage suppressing structure includes the above-described doped portion and the above-described intrinsic portion, the leakage suppressing layer 12 may include a doped layer 121, and an intrinsic layer 122 located on the doped layer 121. The thickness of the intrinsic layer 122 may be set according to actual requirements, as long as impurities in the doped layer 121 are prevented from diffusing into the channel layer 132. For example: the thickness of the intrinsic layer 122 may be 0 to 10 nm.
For at least one layer of the stack, the channel layer included in the stack is a film layer for manufacturing the nanowire or the chip included in the gate-all-around transistor, so the number of layers of the stack formed on the leakage current suppressing layer is equal to the number of layers of the nanowire or the chip included in the gate-all-around transistor. The material and thickness of the channel layer are the same as those of the nanowire or the sheet, respectively. As for the thickness of the sacrificial layer, the thickness may be set with reference to the specification of the gate stack, and the material of the sacrificial layer may be set according to the material of the channel layer and the leakage current suppressing structure, so as to prevent the nanowire or the sheet from being released by removing a portion of the sacrificial layerAnd the leakage suppression structure, and the yield of the gate-all-around transistor is improved. For example, the material of the leakage suppressing structure may be Si 1-x Ge x The material of the channel layer may be Si 1-y Ge y The sacrificial layer may be made of Si 1-z Ge z . Wherein x is more than or equal to 0 and less than or equal to 1, y is more than or equal to 0 and less than or equal to 1, z is more than or equal to 0 and less than or equal to 1, | x-z | is more than or equal to 0.2, and | y-z | is more than or equal to 0.2. Specifically, the materials of the leakage current suppressing structure and the channel layer may be the same or different. For example: the leakage suppressing structure is made of Si 0.2 Ge 0.8 The channel layer is made of Si, and the sacrificial layer is made of Si 0.6 Ge 0.4 . Another example is: the leakage suppressing structure is made of Si 0.5 Ge 0.5 The channel layer is made of Si 0.5 Ge 0.5 The sacrificial layer is made of Si.
It should be noted that, when the material of the leakage suppression structure is a sige material, the material of the leakage suppression layer is also a sige material. At this time, the leakage current suppressing layer formed on the substrate may also serve as a strain buffer layer to provide stress to a film layer formed thereon for fabricating at least one stack, so that strain is generated in a nanowire or sheet formed based on a channel layer included in the stack, carrier mobility of the gate-all-around transistor is improved, and driving performance of the gate-all-around transistor is improved.
In an actual application process, the leakage current suppressing layer and the stacked layer may be formed on the substrate by using a process such as epitaxial growth. Because at least part of the region in the electric leakage inhibition layer is doped with impurities, the electric leakage inhibition layer can be doped with impurities with corresponding concentration by adopting an in-situ doping process in the epitaxial growth process, and the manufacturing efficiency of the gate-all-around transistor is improved. Of course, other processes may be used to form the above-described leakage current suppressing layer and the stack.
As shown in fig. 3 to 5, at least the leakage current suppressing layer 12 and the at least one stacked layer are patterned to form a fin 14 on the active region.
In practical application, a self-aligned double exposure (SADP) technique or the like may be used to etch from the top of the stack to at least the bottom of the leakage current suppressing layer, so as to obtain a fin portion on the active region. As shown in fig. 4 and 5 (3), only the leakage current suppressing layer 12 and the stacked layer may be subjected to patterning. As shown in fig. 3 and (1) and (2) of fig. 5, the stacked layer, the leakage current suppressing layer 12, and a part of the substrate 11 may be subjected to patterning processing. The specific object of the patterning process in the process of forming the fin portion 14 may be set according to an actual application scenario, and is not limited specifically here.
As shown in fig. 6, a shallow trench isolation structure 15 is formed on a portion of the substrate 11 located in the isolation region. The top height of the shallow trench isolation structure 15 is less than or equal to the top height of the leakage suppression layer 12. The portion of the fin 14 exposed outside the shallow trench isolation structure 15 has a source formation region 16, a drain formation region 17, and a transition region 18 between the source formation region 16 and the drain formation region 17.
In an actual application process, the isolation material covering the isolation region and the fin portion may be formed by using a chemical vapor deposition process or the like, and the isolation material may be planarized. And then, carrying out back etching treatment on the planarized isolation material until the top height of the rest part of the isolation material is less than or equal to the top height of the electric leakage restraining layer after the patterning treatment, and obtaining the shallow trench isolation structure. The material of the shallow trench isolation structure can be referred to above. According to the difference of the thickness of the shallow trench isolation structure, the part of the fin part exposed outside the shallow trench isolation structure has the following conditions:
first, as shown in fig. 6 (1), if the top height of the shallow trench isolation structure 15 is equal to the top height of the patterned leakage prevention layer 12, the exposed portion of the fin 14 includes only the patterned at least one stacked layer.
Secondly, as shown in part (2) of fig. 6, if the height of the top of the shallow trench isolation structure 15 is smaller than the height of the top of the leakage current prevention layer 12 after patterning and smaller than the height of the bottom of the leakage current prevention layer 12 after patterning, the exposed portion of the fin 14 includes at least one stacked layer after patterning and a portion of the leakage current prevention layer 12 which is exposed outside the shallow trench isolation structure 15 after patterning.
Third, as shown in part (3) of fig. 6, if the height of the top of the shallow trench isolation structure 15 is greater than 0 and less than or equal to the height of the bottom of the leakage prevention layer 12 after the patterning process, the exposed part includes at least one stacked layer after the patterning process and the leakage prevention layer 12.
As shown in parts (1), (2), and (3) of fig. 9, the top of the portion of the fin located in the source formation region and the drain formation region is etched down to at least the bottom of the patterned leakage suppression layer to expose the portion of the active region located below the source formation region and the drain formation region, and the remaining portion of the leakage suppression layer is made to form the leakage suppression structure 21.
In practical applications, the process of forming the leakage current suppressing structure is different according to the forming process of the gate stack. In an exemplary case where the gate stack is formed by using a gate-last process, after forming the shallow trench isolation structure and before performing subsequent operations, the method for manufacturing the gate-all-around transistor further includes: as shown in fig. 7 and 8, a sacrificial gate 19 and an isolation sidewall 20 are formed to cover the periphery of the transition region 18. The isolation side walls 20 are at least located on two sides of the sacrificial gate 19 along the length direction. Specifically, a gate material for forming the sacrificial gate may be deposited on the formed structure by a chemical vapor deposition process or the like. And then, dry etching and other processes can be adopted to etch the grid electrode material, and the part of the grid electrode material covering the periphery of the transition region is reserved to obtain the sacrificial grid. The gate material may be amorphous silicon, polysilicon, or other material that is easy to remove. As shown in fig. 7 and 8, after the sacrificial gate 19 is formed, the isolation spacers 20 may be formed at least on the sidewalls of the sacrificial gate 19 in the above manner. The material and thickness of the isolation sidewall spacers 20 can be referred to above.
As shown in fig. 9, after obtaining the sacrificial gate 19 and the isolation sidewall 20, the top of the portion of the fin located in the source formation region and the drain formation region may be etched at least down to the bottom of the patterned leakage current suppressing layer under the mask effect of the sacrificial gate 19 and the isolation sidewall 20. At this time, the remaining portion of the leakage current suppressing layer is located in and/or below the transition region.
Note that, in order to ensure that the portions of the patterned leakage current suppressing layer located below the source formation region and the drain formation region are completely removed, after etching to the bottom of the patterned leakage current suppressing layer, the portions of the substrate located below the source formation region and the drain formation region may be continuously etched downward.
According to the forming process of the leakage current inhibiting structure, the channel layer is formed after the leakage current inhibiting layer, so that impurities cannot enter the channel layer when the impurities are doped in the leakage current inhibiting layer, the impurities cannot exist in the channel layer, and the nanowires or sheets formed on the basis of the channel layer are ensured to have high carrier mobility. Meanwhile, the quality of the channel layer cannot be influenced due to impurity doping, high-quality nanowires or chips can be obtained, and the working performance of the gate-all-around transistor can be improved.
In one example, as described above, in the case of forming the gate stack by using the gate-last process, after forming the leakage inhibiting structure in the remaining portion of the leakage inhibiting layer, before forming the source region in the source forming region and the drain region in the drain forming region, the method for manufacturing the gate-all-around transistor may further include the steps of: as shown in fig. 10, the portion of the sacrificial layer located in the transition region is selectively etched along the length of the gate stack to recess the sidewalls of the remaining portion of the sacrificial layer inwardly with respect to the sidewalls of the remaining portion of the channel layer, resulting in a notch 22. As shown in fig. 11, an inner sidewall 23 is formed in the recess.
In the practical application process, because the sacrificial layer, the leakage inhibiting structure and the channel layer have certain etching selection ratios, selective etching can be carried out on the part of the sacrificial layer, which is positioned in the transition region, by adopting a selective etchant. Since the leakage suppressing structure and the portion of the channel layer located in the transition region are not affected by the etchant, the sidewalls of the remaining portion of the sacrificial layer are recessed inward with respect to the sidewalls of the remaining portion of the channel layer, thereby obtaining a notch. Then, a chemical vapor deposition process or the like can be used to form the inner sidewall in the recess.
It should be noted that, in the subsequent process of releasing the nanowire or the chip, only the portion of the sacrificial layer located in the release region may be removed without affecting the portion of the sacrificial layer covered by the isolation sidewall, or the inner sidewall may not be formed under the condition that the requirement on the length of the gate stack is not strict.
In one example, as described above, in the case of forming the gate stack using a back gate, after forming the leakage suppression structure in the remaining portion of the leakage suppression layer, the method for manufacturing the gate-all-around transistor further includes the following steps:
as shown in fig. 12, a source region 24 is formed at least in the source formation region, and a drain region 25 is formed at least in the drain formation region. Specifically, a source region 24 may be formed at least in the source formation region and a drain region 25 may be formed in the drain formation region by epitaxial growth or the like. The source region 24 and the drain region 25 may be formed simultaneously or in steps.
In some cases, as shown in fig. 13, after forming the source region 24 and the drain region 25, a dielectric layer 26 may be formed overlying the substrate 11 by using physical vapor deposition and chemical mechanical polishing. The top of the dielectric layer 26 is flush with the top of the sacrificial gate 19, so as to prevent the source region 24 and the drain region 25 from being affected by etching, cleaning and the like in the subsequent process of removing the sacrificial gate 19 and the remaining part of the sacrificial layer, and improve the yield of the gate-all-around transistor.
As shown in fig. 14 and 15, the sacrificial gate is removed, and the portion of the sacrificial layer covered by the release region 27 is removed, so that the portion of each channel layer located within the transition region forms a respective layer nanowire or patch 28. The release region 27 is a region released after the sacrificial gate is removed.
In an actual application process, a dry etching process or a wet etching process may be adopted to sequentially remove the sacrificial gate and the portion of the sacrificial layer covered by the release region.
As shown in fig. 16 and 17, a gate stack 29 is formed around the periphery of at least one layer of nanowires or sheets 28.
Illustratively, the gate stack may be formed using a process such as atomic layer deposition. The specific structure and material of the gate stack can be found in the above paragraphs.
It should be noted that, in addition to the leakage suppression structure, the stacked structure, the isolation sidewall, the gate stack, and the like may be formed in various ways. How to form the above-described structure is not essential features of the present invention, and thus, in the present specification, only brief descriptions thereof will be made so that those skilled in the art can easily carry out the present invention. It is fully contemplated by one of ordinary skill in the art that the above-described structures may be otherwise made.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the disclosure, and these alternatives and modifications are intended to fall within the scope of the disclosure.
Claims (11)
1. A gate all around transistor, comprising: a substrate, a first electrode and a second electrode,
a stacked structure formed on the substrate; the stacked structure comprises a source region, a drain region and at least one layer of nanowires or sheets positioned between the source region and the drain region, the at least one layer of nanowires or sheets is respectively contacted with the source region and the drain region, and a gap is formed between the at least one layer of nanowires or sheets and the substrate;
a gate stack surrounding a periphery of the at least one layer of nanowires or sheets;
the isolation side walls are at least formed on two sides of the gate stack along the length direction;
and a leakage suppression structure formed on the substrate; the electric leakage suppression structure is positioned below the at least one layer of nano wire or sheet and below the part of the isolation side wall corresponding to the at least one layer of nano wire or sheet; impurities with the conductivity type opposite to that of the gate-all-around transistor are doped in the leakage suppression structure; the bottoms of the source region and the drain region are at least flush with the bottom of the leakage suppression structure.
2. The gate-all-around transistor of claim 1, wherein along a thickness direction of the substrate, the leakage-suppressing structure comprises a doped portion and an intrinsic portion located on the doped portion; the doped portion is doped with the impurity.
3. The gate-all-around transistor of claim 1, wherein the thickness of the leakage suppression structure is 10nm to 40 nm; and/or the presence of a gas in the gas,
the doping concentration of the impurity in the leakage current inhibiting structure is 1E18cm -3 To 2E19cm -3 (ii) a And/or the presence of a gas in the gas,
the leakage suppression structure is made of Si 1-x Ge x ，0≤x≤1。
4. The gate-all-around transistor of claim 1, further comprising inner sidewalls; along the length direction of the gate stack, the inner side wall is located between the gate stack and the source region and between the gate stack and the drain region.
5. The gate-all-around transistor according to any one of claims 1 to 4, wherein the substrate has an isolation region and an active region; the leakage suppression structure and the stack structure are formed on the active region;
the gate all around transistor also comprises a shallow groove isolation structure formed on the isolation region; the top height of the shallow trench isolation structure is smaller than or equal to the top height of the leakage suppression structure.
6. A method for manufacturing a gate all around transistor, comprising:
providing a substrate;
forming a stacked structure, an isolation side wall, a leakage suppression structure and a gate stack on the substrate; the stacked structure comprises a source region, a drain region and at least one layer of nanowires or sheets positioned between the source region and the drain region, the at least one layer of nanowires or sheets is respectively contacted with the source region and the drain region, and a gap is formed between the at least one layer of nanowires or sheets and the substrate; the gate stack surrounds the periphery of the at least one layer of nanowires or sheets; the isolation side walls are at least formed on two sides of the gate stack along the length direction; the electric leakage suppression structure is positioned below the at least one layer of nano wire or sheet and below the part of the isolation side wall corresponding to the at least one layer of nano wire or sheet; impurities with the conductivity type opposite to that of the gate-all-around transistor are doped in the leakage suppression structure; the bottom of the source region and the bottom of the drain region are at least flush with the bottom of the leakage suppression structure.
7. The method of manufacturing a gate-all-around transistor according to claim 6, wherein the substrate has an active region and an isolation region;
forming the leakage suppression structure on the substrate includes:
forming a leakage current suppressing layer and at least one stacked layer covering the substrate; each of the stacked layers includes a sacrificial layer and a channel layer on the sacrificial layer;
patterning at least the leakage current suppression layer and the at least one laminated layer to form a fin portion on the active region;
forming a shallow trench isolation structure on the part of the substrate, which is positioned in the isolation region; the top height of the shallow trench isolation structure is less than or equal to the top height of the leakage suppression layer; the part of the fin part exposed out of the shallow trench isolation structure is provided with a source forming area, a drain forming area and a transition area positioned between the source forming area and the drain forming area;
and etching at least the top of the part of the fin part, which is positioned in the source forming area and the drain forming area, to the bottom of the electric leakage restraining layer after the patterning treatment so as to expose the part of the active area, which is positioned below the source forming area and the drain forming area, and enabling the rest part of the electric leakage restraining layer to form the electric leakage restraining structure.
8. The method of claim 7, wherein after forming the shallow trench isolation structure on the portion of the substrate in the isolation region, the top of the portion of the fin portion in the source formation region and the drain formation region is etched at least down to the bottom of the patterned leakage current suppressing layer, and the method further comprises:
forming a sacrificial gate and the isolation side wall which cover the periphery of the transition region; the isolation side walls are at least positioned at two sides of the sacrificial gate along the length direction;
after the residual part of the leakage current inhibiting layer forms the leakage current inhibiting structure, the method for manufacturing the gate-all-around transistor further comprises the following steps:
forming the source region at least in the source formation region and forming the drain region at least in the drain formation region;
removing the sacrificial gate and the part of the sacrificial layer covered by the release region, so that the part of each channel layer, which is positioned in the transition region, forms a corresponding layer of the nanowire or the chip; the release region is a region released after the sacrificial gate is removed;
forming the gate stack around the periphery of at least one layer of nanowires or sheets.
9. The method of claim 8, wherein after the forming the leakage current suppressing structure in the remaining portion of the leakage current suppressing layer, before forming the source region in at least the source forming region and forming the drain region in at least the drain forming region, the method further comprises:
selectively etching the part of the sacrificial layer, which is positioned in the transition region, along the length direction of the gate stack so as to enable the side wall of the rest part of the sacrificial layer to be recessed inwards relative to the side wall of the rest part of the channel layer, and obtaining a notch;
and forming an inner side wall in the notch.
10. The method of manufacturing a gate all around transistor according to any one of claims 7 to 9, wherein the leakage suppressing structure is made of Si 1-x Ge x The material of the channel layer is Si 1-y Ge y The sacrificial layer is made of Si 1-z Ge z (ii) a Wherein x is more than or equal to 0 and less than or equal to 1, y is more than or equal to 0 and less than or equal to 1, z is more than or equal to 0 and less than or equal to 1, | x-z | > 0.2, and | y-z | > 0.2.
11. The method for manufacturing the gate-all-around transistor according to any one of claims 7 to 9, wherein the formation process of the leakage current suppression layer comprises an epitaxial growth process and an in-situ doping process; and/or the presence of a gas in the gas,
the leakage inhibiting layer comprises a doping layer and an intrinsic layer positioned on the doping layer; the intrinsic layer has a thickness of 0 to 10 nm.
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