CN114759094A

CN114759094A - Semiconductor structure and preparation method

Info

Publication number: CN114759094A
Application number: CN202210459333.5A
Authority: CN
Inventors: 李德斌
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-04-27
Filing date: 2022-04-27
Publication date: 2022-07-15

Abstract

The embodiment of the disclosure relates to the field of semiconductors, and provides a semiconductor structure and a preparation method thereof, wherein the semiconductor structure comprises: a substrate including an active region; the channel layer is positioned on the surface of the substrate of the active region; the grid structure is positioned on the surface of the channel layer; the barrier layer is located on the surface of the substrate of the active region, the side face of the barrier layer is in contact with the side face of the channel layer, and the lattice constant of the material of the channel layer is larger than the lattice constants of the materials of the barrier layer and the substrate. The semiconductor structure provided by the embodiment of the disclosure can at least prevent the stress relaxation phenomenon of the channel layer.

Description

Semiconductor structure and preparation method

Technical Field

The embodiment of the disclosure relates to the field of semiconductors, in particular to a semiconductor structure and a preparation method thereof.

Background

With the continuous development of integrated circuit processes and process technologies, the feature size of a transistor (MOS) device is continuously reduced in order to improve the integration level of the integrated circuit. Under the process nodes of high dielectric material metal gate (HKMG), fin transistor (Finfet), etc., a series of problems need to be faced while increasing the operating speed of the MOS device and reducing its power consumption.

How to prevent the stress relaxation phenomenon generated by the thermal action of the channel layer and improve the stability of the semiconductor structure has become an important problem to be solved urgently by those skilled in the art.

Disclosure of Invention

Embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which at least facilitate prevention of stress relaxation in a channel layer.

According to some embodiments of the present disclosure, an aspect of the embodiments of the present disclosure provides a semiconductor structure, including: a substrate including an active region; the channel layer is positioned on the surface of the substrate of the active region; the grid structure is positioned on the surface of the channel layer; the barrier layer is located on the surface of the substrate of the active region, the side face of the barrier layer is in contact with the side face of the channel layer, and the lattice constant of the material of the channel layer is larger than the lattice constants of the materials of the barrier layer and the substrate.

According to some embodiments of the present disclosure, in another aspect, there is provided a method for manufacturing a semiconductor structure, including: providing a substrate, wherein the substrate comprises an active region; forming a channel layer, wherein the channel layer is positioned on the surface of the substrate of the active region; forming a gate structure, wherein the gate structure is positioned above the channel layer; and forming a barrier layer, wherein the barrier layer is positioned on the side surface of the channel layer on the surface of the substrate and is in contact with the side surface of the barrier layer, and the lattice constant of the material of the channel layer is larger than the lattice constant of the materials of the barrier layer and the substrate.

The technical scheme provided by the embodiment of the disclosure at least has the following advantages:

in the semiconductor structure provided by the embodiment of the disclosure, the barrier layer is arranged on the surface of the substrate, the side surface of the channel layer is in contact with the side surface of the barrier layer, the barrier layers are formed on two sides of the channel layer, the lattice boundary of the material of the channel layer is fixed, and the deformation of the film layer of the channel layer is avoided, so that the stress relaxation phenomenon of the channel layer is prevented. In addition, the purpose of extruding the channel layer under the grid structure is achieved by utilizing the difference between the lattice constant of the material of the channel layer and the lattice constant of the material of the barrier layer, and the compressive stress generated by the difference of the lattice constants can offset the stress relaxation phenomenon generated by the thermal action of part of the channel layer, so that the lattice of the material of the channel layer can not be relaxed towards the periphery.

Drawings

One or more embodiments are illustrated by corresponding figures in the drawings, which are not to be construed as limiting the embodiments, unless expressly stated otherwise, and the drawings are not to scale. One or more embodiments are illustrated by corresponding figures in the drawings, which are not to be construed as limiting the embodiments, unless expressly stated otherwise, and which are not to scale; in order to more clearly illustrate the embodiments of the present disclosure or technical solutions in the conventional art, the drawings required to be used in the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without inventive efforts.

Fig. 1 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present disclosure;

fig. 2 to fig. 4 are schematic structural diagrams corresponding to steps in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

fig. 5 to 10 are schematic structural diagrams corresponding to steps in a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure.

Detailed Description

As is known in the related art, the conventional semiconductor structure may have a stress relaxation phenomenon of the channel layer.

Analysis has found that one of the causes of stress relaxation in the channel layer is due to the stress relaxation. In the gate structure, a channel layer is generally formed on a surface of a substrate of an active region, and a material of the channel layer has a lattice constant greater than that of the substrate of the active region. Therefore, the substrate may generate a biaxial compressive stress applied to the channel layer due to the difference in lattice constant, so that the substrate generates a compressive deformation to the channel layer. The mobility of holes (pMOSFET) or electrons (nMOSFET) in the channel layer is increased, and the offset between the top of the valence band of the crystal lattice of the material of the channel layer and the top of the valence band of the crystal lattice of the material of the substrate is increased, so that the improvement of the performance of the pMOSFET or the nMOSFET is facilitated. However, there are several steps of high temperature thermal annealing exceeding 1000 ℃ and heat treatment for several hours in the DRAM process after forming the channel layer. The thermal treatment may affect the mobility of holes or electrons, and further affect the stress between the channel layer and the substrate, that is, the stress in the channel layer may be easily released by the long-time thermal treatment or the high-temperature thermal treatment, so that the deformation of the channel layer partially or completely disappears, and at the same time, the benefits of mobility increase and the like caused by the deformation of the channel layer disappear.

The embodiment of the disclosure provides a semiconductor structure and a manufacturing method thereof, which prevent a stress relaxation phenomenon of a channel layer due to a thermal effect by forming a barrier layer on a side surface of the channel layer. The barrier layer is positioned on the side surface of the channel layer and can block the lattice epitaxy of the material of the channel layer, so that the deformation of the film layer of the channel layer is avoided, and the stability of the semiconductor structure is improved. And the lattice constant of the material of the barrier layer is smaller than that of the material of the channel layer, the barrier layer can generate biaxial compressive stress towards the channel layer, namely the barrier layer generates compressive deformation to the channel layer, and the stress relaxation phenomenon generated by the thermal action of part of the channel layer can be counteracted, namely the stress relaxation phenomenon of the channel layer is prevented.

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in various embodiments of the disclosure, numerous technical details are set forth in order to provide a better understanding of the disclosure. However, the claimed subject matter of the present disclosure can be practiced without these specific details and with various changes and modifications based on the following examples. Fig. 1 is a schematic structural diagram of a semiconductor structure according to an embodiment of the disclosure.

According to some embodiments of the present disclosure, referring to fig. 1, an aspect of an embodiment of the present disclosure provides a semiconductor structure, including: a substrate 100, the substrate 100 including an active region (not shown); a channel layer 102, wherein the channel layer 102 is positioned on the surface of the substrate 100 of the active region; a gate structure 110, wherein the gate structure 110 is located on the surface of the channel layer 102; and a barrier layer 104, the barrier layer 104 being located on the surface of the substrate 100 in the active region, the side surface of the barrier layer 104 being in contact with the side surface of the channel layer 102, the lattice constant of the material of the channel layer 102 being greater than the lattice constant of the materials of the barrier layer 104 and the substrate 100.

In some embodiments, the material of the substrate 100 is a semiconductor material, and the semiconductor material may include any one of silicon, germanium, silicon carbide, or silicon germanium. The disclosed embodiments use a substrate100 is silicon as an example. The lattice constant of silicon is

The substrate 100 is doped with P-type doping elements, i.e., the semiconductor structure is a P-type transistor (pMOSFET). In other embodiments, the substrate 100 is doped with an N-type doping element, i.e., the semiconductor structure is an N-type transistor (nMOSFET). Specifically, the N-type doping element may be a group v element such As a phosphorus (P) element, a bismuth (Bi) element, an antimony (Sb) element, or an arsenic (As) element, and the P-type doping element may be a group iii element such As a boron (B) element, an aluminum (Al) element, a gallium (Ga) element, or an indium (In) element.

In some embodiments, the channel layer 102 may serve as a channel region of a semiconductor structure, a material of the channel layer 102 has a lattice constant greater than a lattice constant of a material of the substrate 100, and the material of the channel layer 102 is silicon germanium, which has high carrier mobility. And the lattice constant of silicon germanium is greater than that of silicon, due to the difference in lattice constant, the substrate 100 may generate a compressive stress to the square of the channel layer 102, thereby increasing the mobility of carriers (electrons or holes) in the channel layer 102, and increasing the driving current and the speed of the transistor composed of the active region, the channel layer 102, and the gate structure 110. The increase of mobility can offset the decrease of mobility caused by a vertical electric field generated by forming a plurality of transistors on the surface of the vertical substrate 100, that is, the semiconductor structure can be converted from a 2D dimension to a 3D dimension, which is beneficial to improving the storage density of the semiconductor structure. In other embodiments, the material of the channel layer may be silicon, and the mobility of electrons may be improved by implanting germanium ions into the channel layer. In still other embodiments, the material of the channel layer may be germanium, which has a high carrier mobility.

In some embodiments, the gate structure 110 includes a gate insulating layer 111, a gate conductive layer 112, a gate cap 113, and a gate sidewall 114. The gate insulating layer 111, the gate conductive layer 112, and the gate cap 113 are sequentially stacked on the surface of the channel layer 102, and the gate sidewall 114 is located on the side surfaces of the gate insulating layer 111, the gate conductive layer 112, and the gate cap 113. The gate insulating layer 111 is used to isolate the gate conductive layer 112 from the channel layer 102, and simultaneously reduces a direct tunneling current between the gate conductive layer 112 and the channel layer 102, thereby avoiding a leakage current generated by a parasitic capacitance. The gate conductive layer 112 may be made of metal tungsten, copper, tantalum, or silver, that is, the gate structure 110 is made of metal gate HKMG made of high dielectric material, the metal gate can overcome the depletion effect of the polysilicon gate structure, and eliminate the boron penetration effect, and meanwhile, the metal has low resistivity and smaller gate resistance, which is beneficial to reducing the resistance of the gate structure 110. The gate sidewall spacers 114 have a doping element of the same type as the doping element in the substrate 100. In other embodiments, the gate conductive layer 112 may be doped polysilicon, the band gap of the polysilicon is the same as or similar to the band gap of the channel layer 102 located at the bottom of the gate structure 110, i.e., the work function of the polysilicon is the same as or similar to the work function of the channel layer 102, so as to lower the threshold voltage of pMOSFET or nMOSFET, and the work function of the polysilicon can be controlled by changing the concentration of the doping element, so as to control the work function difference between the polysilicon layer and the channel layer 102, thereby lowering the threshold voltage of pMOSFET or nMOSFET. Moreover, the melting point of polysilicon is higher than that of most metals, which may affect the upper temperature limit of the high-temperature deposited gate material in the semiconductor process, and is beneficial to improving the device performance of the gate structure 110.

In some embodiments, the material of the gate insulating layer 111 may be silicon nitride, silicon oxide or other high dielectric constant material, and the high dielectric constant material may be silicon dioxide, silicon nitride, aluminum oxide, tantalum pentoxide, yttrium oxide, hafnium silicate oxide, hafnium dioxide, lanthanum oxide, zirconium dioxide, strontium titanate, zirconium silicate oxide. The gate cap 113 may be made of silicon oxide, silicon carbide, or silicon nitride, and the gate sidewall 114 may be made of amorphous silicon, or polysilicon.

In some embodiments, the lattice constant of the material of the barrier layer 104 is smaller than the lattice constant of the channel layer 102, and the barrier layer 104 is located on the side of the channel layer 102 on the one hand, and may function to block the lattice epitaxy of the material of the channel layer 102, and at the same time, the barrier layer 104 may reach the channel layer 102 under the pressing gate structure 110 due to the difference of the lattice constants, and the pressing stress presses the side of the channel layer 102, further avoiding the epitaxy of the lattice of the material of the channel layer 102.

In some embodiments, the lattice constant of the material of the barrier layer 104 is smaller than or equal to the lattice constant of the material of the substrate 100 of the active region, and the barrier layer 104 may generate compressive stress on the substrate 100 to avoid deformation of the substrate 100. Meanwhile, the lattice constant difference between the material of the barrier layer 102 and the material of the channel layer 102 is greater than or equal to the lattice constant between the material of the substrate 100 and the material of the channel layer 102, so that the compressive stress generated by the barrier layer 104 is greater than the compressive stress of the substrate 100 on the channel layer 102, when the channel layer 102 has a stress relaxation phenomenon, the lattice of the material of the channel layer 102 is more relaxed towards the direction of the substrate 100 with smaller compressive stress, and the phenomenon that the lattice of the material of the channel layer 102 is relaxed towards two sides to cause the deformation of the channel layer 102 is further avoided.

In some embodiments, the barrier layer 104 includes an epitaxial semiconductor layer, and the material of the barrier layer 104 is the same as the material of the substrate 100 of the active region, i.e., the barrier layer 104 may be formed by a surface epitaxy process of the substrate 100. Specifically, the material of the barrier layer 104 includes silicon or silicon carbide.

In some embodiments, the barrier layer 104 has a dopant element therein, which may be an N-type dopant element or a P-type dopant element. The region where the blocking layer 104 is located may be used as a part of a source terminal or a drain terminal of a transistor to be formed later, and the doping element may be used as a carrier.

In some embodiments, the substrate 100 of the active region includes a source terminal and a drain terminal; along the arrangement direction of the source terminal and the drain terminal, the side surface of the channel layer 102 contacts with the side surface of the barrier layer 101. In other embodiments, a fine gap exists between the side of barrier layer 104 and the side of channel layer 102, the gap having a width of

Barrier layer 104 surrounds the sides of channel layer 102.

In some embodiments, the top surface of the barrier layer 104 away from the substrate 100 is higher than the top surface of the channel layer 102 away from the substrate 100, the top surface of the barrier layer 104 is higher than the top surface of the channel layer 102, the side surfaces of the channel layer 102 and the barrier layer 104 are in full contact, and the barrier layer 104 may face the channel layer 100102 to form complete protection, and prevent the stress relaxation phenomenon of the channel layer 102 caused by the thermal action; the height difference m between the top surface of the barrier layer 104 and the top surface of the channel layer 102 is

m may specifically be

Or

In some embodiments, the bottom surface of barrier layer 104 is lower than the bottom surface of channel layer 102; the height difference n between the bottom surface of the barrier layer 104 and the bottom surface of the channel layer 102 is 3nm to 5nm, and n may be 3nm, 4.2nm, 4.8nm or 5 nm. On one hand, the side surface of the channel layer 102 can be completely protected, and the stress relaxation phenomenon of the channel layer 102 due to the thermal action is prevented; on the other hand, the integrity of the barrier layer 104 formed by epitaxy and the height of the barrier layer 104 higher than the height of the channel layer 102 are facilitated, the lattice defect of the barrier layer 104 and the resistance of the barrier layer 104 are reduced, and the electrical connection performance of the semiconductor structure is facilitated to be improved.

In some embodiments, the semiconductor structure further comprises: shallow Trench Isolation (STI) 120, the STI 120 surrounding the gate structure 110, the STI 120 further surrounding the active region of the substrate 100, and the STI 120 may be used to prevent leakage current between adjacent gate structures 110. The sidewall of the shallow trench isolation structure 120 contacting the substrate 100 is an inclined surface, which is beneficial to the tightness of the filling material for forming the shallow trench isolation structure 120 and the electrical performance of the shallow trench isolation structure 120.

In some embodiments, the depth of the shallow trench isolation structure 120 is 10nm to 100nm, the depth of the shallow trench isolation structure 120 may be 12nm, 50nm, 70nm or 100nm, and the depth of the shallow trench isolation structure 120 is in a range that is used to prevent leakage current between adjacent gate structures 110, and also used to eliminate a depletion region on the surface of the substrate 100 and shorten the pitch of the semiconductor structures.

In some embodiments, the shallow trench isolation structure 120 includes an isolation layer 121 and a buffer layer 122, the buffer layer 122 is located between the isolation layer 121 and the substrate 100, and the buffer layer 122 is used to block oxygen atoms in the isolation layer 121 from diffusing to the substrate 100 in the active region, and is beneficial to improving the interface characteristics between the substrate 100 and the isolation layer 121. The buffer layer 122 may have a thickness of

The thickness of the buffer layer 122 may be specifically

Or alternatively

The material of the isolation layer 121 may be silicon oxide or silicon oxynitride, and the material of the buffer layer 122 may be silicon oxide, silicon carbide or other insulating materials.

In the semiconductor structure provided by the embodiment of the present disclosure, the barrier layer 104 is disposed on the surface of the substrate 10, the side surface of the channel layer 102 contacts the side surface of the barrier layer 104, the barrier layer 104 is formed on two sides of the channel layer 102, and the lattice boundary of the material of the channel layer 102 is fixed, so as to prevent the film layer of the channel layer 102 from deforming, thereby preventing the stress relaxation phenomenon of the channel layer 102. In addition, the purpose of pressing the channel layer 102 under the gate structure 110 is achieved by utilizing the difference between the lattice constant of the material of the channel layer 102 and the lattice constant of the material of the barrier layer 104, and the compressive stress generated by the difference in the lattice constants can counteract the stress relaxation phenomenon of a part of the channel layer 102 due to the thermal action, thereby ensuring that the lattice of the material of the channel layer 102 is not relaxed to the periphery.

Accordingly, according to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure provides a method for manufacturing a semiconductor structure, which is used for manufacturing the semiconductor structure provided by the above embodiments.

Fig. 2 to fig. 4 are schematic structural diagrams corresponding to steps in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure.

Referring to fig. 2 to 3, a substrate 100 is provided, the substrate 100 including an active region; forming a channel layer 102, wherein the channel layer 102 is positioned on the surface of the substrate 100 of the active region; a gate structure 100 is formed, the gate structure being located over channel layer 102.

Specifically, referring to fig. 2, an initial substrate 105 is provided, and a semiconductor film 101 and a gate structure 110 are sequentially formed on a surface of the initial substrate 102.

The material of the initial substrate 105 is a semiconductor material, which may include any one of silicon, germanium, silicon carbide, or silicon germanium. The initial substrate 105 is doped with a P-type doping element or an N-type doping element, i.e., the semiconductor structure is a P-type transistor (pMOSFET) or an N-type transistor (nMOSFET).

In some embodiments, the lattice constant of the material of the semiconductor film 101 is greater than the lattice constant of the material of the initial substrate 105; the semiconductor film 101 is formed by a selective epitaxial process or a chemical vapor deposition process, and an etching selection ratio of a material of the semiconductor film 101 to a material of the initial substrate 102 is 0.8: 1-1: 1.2, and specifically, the etching selection ratio may be 0.8:1, 1:1.1 or 1: 1.2. The material of the semiconductor film 101 may be silicon germanium, or silicon.

In some embodiments, the gate insulating layer 111, the gate conductive layer 112, the gate cap 113, and the gate sidewall 114 are sequentially formed by Chemical Vapor Deposition (CVD), Metal Organic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE), Atomic Layer Deposition (ALD), or the like, and the gate insulating layer 111, the gate conductive layer 112, the gate cap 113, and the gate sidewall 114 together form the gate structure 110. The gate insulating layer 111, the gate conductive layer 112, and the gate cap 113 are sequentially stacked on the surface of the channel layer 102, and the gate sidewall 114 is located on the side surfaces of the gate insulating layer 111, the gate conductive layer 112, and the gate cap 113.

In some embodiments, forming the shallow trench isolation structure 120 after forming the gate sidewall 114 of the gate structure 110, the shallow trench isolation structure 120 surrounding the gate structure 110, the shallow trench isolation structure 120 further surrounding the substrate 100 of the active region; the shallow trench isolation structure 120 has a depth of 10nm to 100 nm.

In some embodiments, the shallow trench isolation structure 120 includes an isolation layer 121 and a buffer layer 122, the buffer layer 122 is located between the isolation layer 121 and the substrate 100, and the thickness of the buffer layer 122 may be

The thickness of the buffer layer 122 may be specifically

Or

The material of the isolation layer 121 may be silicon oxide or silicon oxynitride, and the material of the buffer layer 122 may be silicon oxide, silicon carbide, or other insulating materials.

Specifically, after the gate sidewall spacers 114 are formed, an isolation oxide layer is formed on the surface of the substrate 100 and the conductive film 101, so that the substrate 100 for protecting the active region is damaged in the process of removing the nitride layer formed later.

The nitride mask layer with the groove is formed on the surface of the isolation oxide layer, the position of the groove corresponds to the position of the subsequently formed shallow trench isolation structure, the nitride mask layer is high in strength, the substrate 100 of the active region is protected when the shallow trench isolation structure is formed, and the substrate 100 can be prevented from being damaged by the planarization of the formed shallow trench isolation structure.

Etching the isolation oxide layer and the substrate 100 with partial thickness along the trench by using the nitride mask layer as a mask to form a trench; the buffer layer 122 and the isolation layer 122 are formed, and the remaining isolation oxide layer and the nitride mask layer are removed. In some embodiments, the trench is formed using a photolithographic process. The shallow trench isolation structure 120 is planarized using a chemical mechanical polishing process.

In some embodiments, the isolation oxide layer may be made of silicon oxide or aluminum oxide, and the nitride mask layer may be made of silicon nitride, titanium nitride, aluminum nitride, gallium nitride, or indium nitride.

Referring to fig. 3, the semiconductor film 101 (refer to fig. 2) exposed outside the gate structure 100 is etched away, an initial substrate 105 (refer to fig. 2) is etched to a partial thickness to form a first groove 103, the remaining initial substrate 105 (refer to fig. 2) serves as the substrate 100, and the remaining semiconductor film 101 (refer to fig. 2) serves as the channel layer 102.

In some embodiments, the semiconductor film 101 is etched away using a dry etching process (refer to fig. 2), which may be any one of an isotropic plasma etching process, a reverse ion etching process (RIE), or a physical sputtering and ion milling etching process.

In some embodiments, the depth of the first groove 103 may be 3nm to 5nm in a direction perpendicular to the surface of the substrate 100, so as to ensure that the semiconductor film 101 (refer to fig. 2) exposed outside the gate structure 110 is entirely etched, so that the lattice constant of the material of the subsequently formed barrier layer matches the lattice constant of the material of the substrate 100. Moreover, the exposed surface area of the substrate 100 is large, which is beneficial to a barrier layer formed by subsequent epitaxy, and ensures the integrity of the barrier layer and the top surface of the barrier layer is higher than the top surface of the channel layer 102.

It is understood that the bottom of the first groove 103 is curved due to isotropy of etching.

Referring to fig. 4, a barrier layer 104 is formed, the barrier layer is located on the side surface of the channel layer 102 on the surface of the substrate 100 and contacts the side surface of the barrier layer 102, the lattice constant of the material of the channel layer 102 is greater than the lattice constant of the material of the barrier layer 104, and the barrier layer 104 fills the first recess 103 (refer to fig. 3).

In some embodiments, the barrier layer 104 is formed using a selective epitaxial growth process; the source materials used in the selective epitaxial growth process include a source gas and a dopant source gas for providing a dopant element. The source gas may be a silicon source gas, and the silicon source gas may specifically be silane, disilane, dichlorosilane, or trichlorosilane; the doping element source gas comprises an N-type element source gas or a P-type element source gas, and the N-type element source gas can be phosphine, arsine or antimony hydride; the P-type element source gas may be specifically borane. In other embodiments, the source gas may also be a germanium source gas, and the germanium source gas may specifically be germane. The temperature of the selective epitaxial growth process is 800 ℃ to 850 ℃, and the temperature of the selective epitaxial growth can be 800 ℃, 825 ℃ or 849 ℃.

In the embodiments, the gate structure is formed first and then the barrier layer is formed, but in other embodiments of the present disclosure, the semiconductor structure may be prepared by forming the barrier layer and then the gate structure. Fig. 5 to 10 are schematic structural diagrams corresponding to steps in a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure. A method for fabricating a semiconductor structure according to another embodiment of the present disclosure will be described in detail with reference to fig. 5 to 10, and the same parts as those in the above embodiments will not be described in detail.

Referring to fig. 5 to 7, a substrate 200 is provided, the substrate 200 including an active region; a channel layer 202 is formed, and the channel layer 202 is positioned on the surface of the substrate 200 of the active region.

Specifically, referring to fig. 5, a substrate 205 is provided, including active regions within the substrate 205.

The material of the substrate 205 may include any one of silicon, germanium, silicon carbide, or silicon germanium. The substrate 205 is doped with a P-type doping element or an N-type doping element, that is, the semiconductor structure is a P-type transistor (pMOSFET) or an N-type transistor (nMOSFET).

Referring to fig. 6, a portion of the thickness of the substrate 205 is patterned to form a second recess 201 in the substrate.

Specifically, a second groove 201 is formed in the substrate of a portion of the active region, the second groove 201 is formed by a dry etching process or a wet etching process, and the second groove 201 is used for forming a channel layer subsequently.

Referring to fig. 7, a channel layer 202 is formed, the channel layer 202 being located in the second recess 201 (refer to fig. 6), and a height of the channel layer 202 being equal to or less than a depth of the second recess 201 in a direction perpendicular to the surface of the substrate 205.

In some embodiments, the height of the channel layer 202 is less than the depth of the second recess 201, and the height difference between the top surface of the channel layer 202 and the top surface of the substrate 205 is

The lattice constant of the material of the channel layer 202 is greater than the lattice constant of the material of the substrate 202.

Referring to fig. 8, a barrier layer 204 is formed, the barrier layer 204 is positioned on the lateral surface of the substrate on the channel layer 202, the lateral surface of the channel layer 202 is in contact with the lateral surface of the barrier layer 204, and the lattice constant of the material of the channel layer 202 is greater than the lattice constant of the material of the barrier layer 204. The bottom surface of the barrier layer 204 is lower than the bottom surface of the channel layer 202, and a height difference m between the bottom surface of the barrier layer 204 and the bottom surface of the channel layer 202 is 3nm to 5 nm.

Specifically, the barrier layer 204 is formed by performing a doping process on a portion of the thickness of the substrate 205. The doping process may be in-situ doping or ion doping.

Referring to fig. 9, a gate structure 210 is formed, the gate structure 210 being located over the channel layer 202. The gate structure 210 includes a gate insulating layer 211, a gate conductive layer 212, a gate cap 213, and a gate sidewall 214. The gate insulating layer 211, the gate conductive layer 212, and the gate cap 213 are sequentially stacked on the surface of the channel layer 202, and the gate sidewall 214 is located on the side surfaces of the gate insulating layer 211, the gate conductive layer 212, and the gate cap 213.

Referring to fig. 10, a portion of the thickness of the substrate 205 (refer to fig. 9) is etched such that the top surface of the remaining substrate is flush with the top surface of the channel layer 202; forming a shallow trench isolation structure 220, wherein the shallow trench isolation structure 220 surrounds the gate structure 210, and the shallow trench isolation structure 220 also surrounds the substrate 200 of the active region; the shallow trench isolation structure 220 has a depth of 10nm to 100 nm. The shallow trench isolation structure 220 includes an isolation layer 221 and a buffer layer 222, wherein the buffer layer 222 is located between the isolation layer 221 and the substrate 200.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the present disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure in practice. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the disclosure, and it is intended that the scope of the disclosure be limited only by the claims appended hereto.

Claims

1. A semiconductor structure, comprising:

a substrate including an active region;

the channel layer is positioned on the surface of the substrate of the active region;

the grid structure is positioned on the surface of the channel layer;

the barrier layer is located on the surface of the substrate of the active region, the side face of the barrier layer is in contact with the side face of the channel layer, and the lattice constant of the material of the channel layer is larger than the lattice constant of the materials of the barrier layer and the substrate.

2. The semiconductor structure of claim 1, wherein a lattice constant of a material of the barrier layer is equal to or less than a lattice constant of a material of the base of the active region.

3. The semiconductor structure of claim 1, wherein the barrier layer comprises an epitaxial semiconductor layer.

4. The semiconductor structure of claim 3, wherein the barrier layer is the same material as the substrate of the active region.

5. The semiconductor structure of any of claims 1 to 4, wherein the material of the barrier layer comprises silicon or silicon carbide.

6. The semiconductor structure of claim 1, wherein the barrier layer has a dopant element therein, the dopant element being N-type or P-type.

7. The semiconductor structure of claim 1, wherein the substrate of the active region comprises a source terminal and a drain terminal; and the side surface of the channel layer is in contact with the side surface of the barrier layer along the arrangement direction of the source end and the drain end.

8. The semiconductor structure of claim 1, wherein the barrier layer surrounds the channel layer sides.

9. The semiconductor structure of claim 1, wherein a top surface of the barrier layer away from the substrate is higher than a top surface of the channel layer away from the substrate; the height difference between the top surface of the barrier layer and the top surface of the channel layer is

10. The semiconductor structure of claim 1 or 9, wherein the barrier layer bottom surface is lower than the channel layer bottom surface; the height difference between the bottom surface of the barrier layer and the bottom surface of the channel layer is 3 nm-5 nm.

11. The semiconductor structure of claim 1, wherein the material of the channel layer comprises silicon germanium or germanium.

12. A method of fabricating a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises an active region;

forming a channel layer on the surface of the substrate of the active region;

forming a gate structure over the channel layer; and forming a barrier layer, wherein the barrier layer is positioned on the side surface of the substrate, the side surface of the channel layer is in contact with the side surface of the barrier layer, and the lattice constant of the material of the channel layer is larger than the lattice constants of the materials of the barrier layer and the substrate.

13. The method of claim 12, wherein the process steps of forming the channel layer and the barrier layer comprise:

providing an initial substrate, and sequentially forming a semiconductor film and the gate structure on the surface of the initial substrate;

etching to remove the semiconductor film exposed outside the gate structure;

and forming the barrier layer, wherein the barrier layer is positioned on the surface of the initial substrate and the side surface of the semiconductor film, the rest of the initial substrate is used as the substrate, and the rest of the semiconductor film is used as the channel layer.

14. The method for manufacturing a semiconductor structure according to claim 13, wherein a first groove is formed by etching a part of the initial substrate while removing the semiconductor film exposed outside the gate structure by etching; the first groove is filled with the barrier layer.

15. The method of fabricating a semiconductor structure according to any of claims 12 to 14, wherein the barrier layer is formed using a selective epitaxial growth process; the temperature of the selective epitaxial growth process is 800 ℃ to 850 ℃.

16. The method of claim 12, wherein the process steps of forming the channel layer and the barrier layer comprise:

providing a substrate;

patterning the substrate with partial thickness, and forming a second groove in the substrate;

forming the channel layer, wherein the channel layer is positioned in the second groove, and the height of the channel layer is less than or equal to the depth of the second groove along the direction vertical to the surface of the substrate;

and carrying out doping treatment on the substrate with the partial thickness to form the barrier layer.