CN109755290B - Nanowire transistor and preparation method thereof - Google Patents
Nanowire transistor and preparation method thereof Download PDFInfo
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- CN109755290B CN109755290B CN201711068065.XA CN201711068065A CN109755290B CN 109755290 B CN109755290 B CN 109755290B CN 201711068065 A CN201711068065 A CN 201711068065A CN 109755290 B CN109755290 B CN 109755290B
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
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- H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
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Abstract
The invention discloses a nanowire transistor and a preparation method thereof, wherein the preparation method comprises the following steps: forming a sacrificial layer and a nanowire which are stacked with each other on a substrate; forming a dummy gate, wherein the dummy gate is positioned above the stacked sacrificial layer and the nanowire; removing the sacrificial layer and the nanowires between the adjacent dummy gates to form source/drain regions; forming an isolation structure, wherein the isolation structure is positioned on the surface of the substrate at the bottom of the source/drain region to isolate the source/drain region from the substrate; and forming source/drain electrodes in the source/drain regions, the source/drain electrodes being located above the isolation structures and contacting the side surfaces of the adjacent nanowires. The isolation structure isolates the source/drain electrode from the substrate, and avoids the phenomenon of current leakage between the source/drain electrode and the substrate. Meanwhile, an internal side wall exists between the grid structure and the source/drain electrode, and the problem of overlarge parasitic capacitance between the source/drain electrode and the grid structure is solved.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a nanowire transistor and a preparation method thereof.
Background
In the past, the reduction of transistor size and the increase of integration level of integrated circuits have been the constant subjects pursued by the semiconductor industry. From finfets (fin transistors) to NWFETs (nanowire transistors), the physical size of the gates is continuously decreasing. In the NWFET, the gate thickness and the source/drain width are small, which effectively enhances the gate control function. However, the reduction in size of the transistor itself tends to generate parasitic capacitance, which affects the performance of the transistor. At present, in order to solve this problem, researchers have proposed a technical solution of forming a sidewall on the bottom of the gate, so as to cut off the current path of the parasitic transistor and improve the dc characteristics of the NWFET.
However, in the prior art, the source/drain of the NWFET nanowire transistor is in direct contact with the substrate, and no effective isolation is performed between the two. When the nanowire transistor operates, a leakage phenomenon easily occurs where the source/drain of the nanowire transistor is in contact with the substrate.
Therefore, there is a need in the art for a method for forming electrical isolation between the substrate and the source/drain of the nanowire transistor, thereby reducing the leakage current.
Disclosure of Invention
The invention provides a nanowire transistor and a preparation method thereof, which realize the electrical isolation between a source/drain electrode and a substrate and reduce the overlarge capacitance between the bottom grid electrode and the source/drain electrode of the nanowire transistor.
In the present invention, there is provided a nanowire transistor comprising: a gate structure disposed on the substrate; the source/drain electrodes are positioned on two sides of the grid structure; the nanowire is arranged in the grid structure, and two side surfaces of the nanowire are in contact with the source/drain electrode; and an isolation structure formed between the substrate and the source/drain to isolate the substrate and the source/drain.
According to an aspect of the present invention, the number of the nanowires is 1 or more, and when the number of the nanowires is plural, the plurality of nanowires are longitudinally distributed at intervals inside the gate structure.
According to one aspect of the invention, the isolation structure covers the substrate under the source/drain so that the source/drain is not in contact with the substrate.
According to an aspect of the invention, the highest point of both sides of the isolation structure is lower than the top surface of the bottommost nanowire.
According to an aspect of the invention, the highest point of both sides of the isolation structure is not higher than the bottom surface of the bottommost nanowire.
According to one aspect of the invention, an isolation structure comprises: the semiconductor device comprises a side wall isolation structure and a bottom isolation structure, wherein the side wall isolation structure is positioned on two sides of the isolation structure, and the bottom isolation structure is positioned between the side wall isolation structures and is in contact with the side wall isolation structures.
According to one aspect of the invention, the two side surfaces of the isolation structure are respectively two side surfaces of the sidewall isolation structure, which are not in contact with the bottom isolation structure.
According to one aspect of the invention, the sidewall isolation structure is a sidewall spacer and the bottom isolation structure is a bottom spacer or a bottom barrier layer.
According to one aspect of the invention, the bottom barrier layer comprises a diffusion barrier layer and/or a conduction barrier layer.
According to an aspect of the invention, further comprising: when the sidewall isolation structure is a sidewall spacerAnd when the bottom isolation structure is a bottom side wall, the side wall isolation structure and the bottom isolation structure are made of the same material, namely SiO 2SiN, SiON, SiOCN.
According to an aspect of the invention, when the sidewall isolation structure is a sidewall spacer and the bottom isolation structure is a bottom barrier layer, the sidewall isolation structure is made of SiO2The bottom isolation structure is made of one or more of Si, SiGe, Ge, GaAs, SiC and SiGeC.
According to one aspect of the invention, the method further comprises the following steps: and the internal side wall is positioned between the source/drain electrode and the grid electrode structure contacted with the bottom surface of the nanowire.
According to one aspect of the invention, a gate structure comprises: the gate structure comprises a gate and a gate dielectric layer covering the surface of the gate.
According to one aspect of the invention, the method further comprises the following steps: a protective structure covering a top surface of the topmost nanowire.
According to an aspect of the invention, further comprising: the first side wall covers two side walls of the grid structure above the protection structure; a first dielectric layer covering the source/drain electrodes; the second dielectric layer covers the grid structure, the first dielectric layer and the surfaces of the first side walls; and a metal line penetrating the second dielectric layer and contacting the gate structure.
The invention also discloses a preparation method of the nanowire transistor, which comprises the following steps: forming a sacrificial layer and a nanowire which are stacked with each other on a substrate; forming a dummy gate, wherein the dummy gate is positioned above the stacked sacrificial layer and the nanowire; removing the sacrificial layer and the nanowires between the adjacent dummy gates to form source/drain regions; forming an isolation structure, wherein the isolation structure is positioned on the surface of the substrate at the bottom of the source/drain region to isolate the source/drain region from the substrate; and forming source/drain electrodes in the source/drain regions, the source/drain electrodes being located above the isolation structures and contacting the side surfaces of the adjacent nanowires.
According to one aspect of the invention, the bottom-most sacrificial layer is in contact with the substrate surface and the bottom-most nanowire is not in contact with the substrate.
According to an aspect of the present invention, the number of stacked nanowires is 1 or more.
According to one aspect of the invention, an isolation structure covers the substrate below the source/drain regions.
According to one aspect of the invention, an isolation structure is formed comprising: and forming a side wall isolation structure and a bottom isolation structure, wherein the side wall isolation structures are positioned at two sides of the bottom isolation structure, and the formed bottom isolation structure is positioned between the side wall isolation structures and is in contact with the side wall isolation structures.
According to one aspect of the invention, the step of forming sidewall and bottom isolation structures comprises: forming a second side wall, wherein the second side wall covers the side faces of the pseudo gates, the side faces of the nanowires, the side faces of the sacrificial layers and the surface of the bottom substrate of the source/drain region on two sides of the source/drain region; forming a dielectric layer covering the surface of the second side wall at the bottom of the source/drain region, wherein the top surface of the dielectric layer is lower than the top surface of the bottommost nanowire and higher than the bottom surface of the bottommost sacrificial layer; and removing parts of the second side walls on the two sides of the source/drain region, and enabling the top surfaces of the rest second side walls on the two sides of the source/drain region to be flush with the top surface of the dielectric layer so as to form a side wall and a bottom side wall, wherein the rest second side walls on the two sides of the source/drain region are the side wall side walls, the side wall side walls are side wall isolation structures, the second side walls located at the bottom of the dielectric layer are bottom side walls, and the bottom side walls are bottom isolation structures.
According to an aspect of the invention, the highest point of both sides of the isolation structure is lower than the top surface of the bottommost nanowire.
According to an aspect of the invention, the highest point of both sides of the isolation structure is not higher than the bottom surface of the bottommost nanowire.
According to one aspect of the invention, the two side surfaces of the isolation structure are respectively the side surfaces of the sidewall isolation structure which are not in contact with the bottom isolation structure.
According to one aspect of the invention, the sidewall isolation structure is a sidewall spacer and the bottom isolation structure is a bottom spacer or a bottom barrier layer.
According to an aspect of the present inventionWhen the sidewall isolation structure is a sidewall spacer and the bottom isolation structure is a bottom spacer, the sidewall isolation structure and the bottom isolation structure are made of the same material, i.e. SiO2SiN, SiC and SiOCN.
According to an aspect of the invention, when the sidewall isolation structure is a sidewall spacer and the bottom isolation structure is a bottom barrier layer, the sidewall isolation structure is made of SiO2The bottom isolation structure is made of one or more of Si, SiGe, Ge, GaAs, SiC and SiGeC.
According to one aspect of the invention, the step of forming sidewall isolation structures and bottom isolation structures further comprises: removing the dielectric layer; removing the bottom side wall and exposing the substrate; and forming a bottom barrier layer on the surface of the substrate between the side wall spacers, wherein the bottom barrier layer is a bottom isolation structure.
According to one aspect of the invention, the bottom barrier layer comprises a diffusion barrier layer and/or a conduction barrier layer.
According to one aspect of the invention, the diffusion barrier layer is of an opposite ion type to the source/drain doping, and the ions doped in the diffusion barrier layer are one or more of boron (B), gallium (Ga).
According to one aspect of the invention, the conduction barrier is of the same ion type as the source/drain doping, doped with: one or more of boron (B), gallium (Ga), or one or more of arsenic (As), rhodium (Rh).
According to an aspect of the invention, further comprising: removing part of the sacrificial layer before forming the second side wall to form openings on two sides of each sacrificial layer; and filling each opening to form the inner side wall when forming the second side wall.
According to one aspect of the invention, the depth of the opening ranges from 2nm to 20 nm.
According to an aspect of the present invention, after forming the source/drain electrodes, further comprising: forming a first dielectric layer covering the source/drain electrode; removing the dummy gate and the sacrificial layer to form a trench; and forming a gate structure within the trench.
According to an aspect of the invention, after forming the gate structure, further comprising: forming a second dielectric layer covering the gate structure and the first dielectric layer; and forming a metal line through the second dielectric layer, the metal line contacting the gate structure.
According to an aspect of the present invention, before forming the dummy gate, the method further includes: and forming a protective structure, wherein the protective structure covers the stacked sacrificial layer and the top surface of the nanowire.
According to an aspect of the present invention, after forming the dummy gate, before forming the isolation structure, further comprising: and forming first side walls covering the two side walls of the pseudo gate.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
since the nanowire transistor of the embodiment of the invention has the isolation structure therein, the isolation structure is positioned between the substrate and the source/drain electrode to isolate the substrate and the source/drain electrode. The isolation structure is used for isolating the source/drain electrode from the substrate and eliminating current leakage between the source/drain electrode and the substrate.
Further, the highest point of the two side surfaces of the isolation structure is lower than the bottom surface of the bottommost nanowire. The position distribution can effectively prevent the parasitic resistance in the nanowire transistor from being increased due to the fact that the top surface of the bottom blocking layer is too high, and therefore the performance of the nanowire transistor is improved better.
Further, the nanowire transistor further comprises an inner side wall, and the inner side wall is located between the source/drain electrode and the grid electrode structure which is in contact with the bottom surface of the nanowire. May serve to isolate the source/drain from the gate structure.
The embodiment of the invention forms an isolation structure when the nanowire transistor is formed, and the isolation structure is positioned on the surface of the substrate of the isolation structure positioned at the bottom of the source/drain region so as to isolate the source/drain region from the substrate. The isolation structure is formed to isolate the source/drain from the substrate subsequently, eliminating current leakage between the source/drain and the substrate.
And further, forming a dielectric layer covering the surface of the second side wall at the bottom of the source/drain region, wherein the top surface of the dielectric layer is lower than the top surface of the bottommost nanowire and higher than the bottom surface of the sacrificial layer contacted with the substrate. The dielectric layer is formed to provide an etch stop for subsequent etching to remove portions of the second sidewalls so that the top surfaces of the sidewalls are also at the same location.
Furthermore, the highest point of the non-contact side surface of the side wall isolation structure and the bottom isolation structure is not higher than the top surface of the sacrificial layer in contact with the substrate. The top surface of the sidewall isolation structure is limited to avoid an excessively high surface, which promotes the conduction between the source/drain and the channel, thereby achieving a better effect.
Further, before forming the second side wall, removing part of the sacrificial layer to form openings on two sides of each sacrificial layer; and when the second side wall is formed, filling all the openings to form the inner side wall. The purpose of doing so is to form an internal side wall between the subsequently formed gate structure and the source/drain, increase the distance between the source/drain and the gate structure, and effectively solve the problem of the overlarge capacitance between the gate and the source/drain of the nanowire transistor.
Drawings
FIGS. 1-9 are schematic cross-sectional structures of a nanowire transistor formation process according to one embodiment of the invention;
FIGS. 10-15 are schematic cross-sectional structure diagrams of a nanowire transistor formation process according to yet another embodiment of the invention;
fig. 16-25 are schematic cross-sectional views illustrating a nanowire transistor formation process according to still another embodiment of the present invention.
Detailed Description
As described above, a current leakage phenomenon occurs between the substrate and the source/drain of the conventional nanowire transistor.
The research finds that the reasons causing the problems are as follows: there is no effective isolation between the substrate and the source/drain of the nanowire transistor. Therefore, the above problem can be solved by providing a scheme of forming an isolation structure between the substrate and the source/drain.
Further research shows that the distance between the grid electrode and the source/drain electrode of the nanowire transistor is short, no effective isolation structure exists, and the parasitic capacitance is overlarge. Therefore, it is proposed to form an inner sidewall spacer between the bottom of the gate and the source/drain to solve the above-mentioned problems.
In order to solve the problem, the invention provides a nanowire transistor and a preparation method thereof, wherein an effective isolation structure is formed between a substrate and a source/drain electrode, and the leakage of current at the bottom of the source/drain electrode caused by direct contact between the substrate and the source/drain electrode is avoided. Meanwhile, an internal side wall is formed between the grid electrode and the source/drain electrode of the nanowire transistor to electrically isolate the grid electrode from the source/drain electrode, so that the problem of overlarge capacitance between the bottom of the grid electrode and the source/drain electrode of the nanowire transistor is solved.
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be understood that the relative arrangement of parts and steps, numerical expressions and numerical values set forth in these embodiments should not be construed as limiting the scope of the invention unless it is specifically stated otherwise.
Further, it will be appreciated that the dimensions of the various elements shown in the figures are not necessarily drawn to scale relative to actual dimensions, for example, the thickness or width of some layers may be exaggerated relative to other layers for ease of illustration.
The following description of the exemplary embodiment(s) is merely illustrative and is not intended to limit the invention or its application or uses in any way.
Techniques, methods, and apparatus that are known to one of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the present description where applicable.
It should be noted that like reference numerals and letters refer to like items in the following figures, and thus, once an item is defined or illustrated in one figure, further discussion thereof will not be required in the subsequent description of the figures.
A first embodiment.
Referring to fig. 1, a substrate 100, a sacrificial layer 110 and a nanowire 120 stacked on each other are formed on the substrate 100, and a dummy gate 150 is formed over the sacrificial layer 110 and the nanowire 120.
The substrate 100 is the basis for the subsequent formation of gates, source/drains, and other processes. The material of the substrate 100 includes Si, SiGe, etc., and is not particularly limited herein.
The sacrificial layer 110 is the basis for the subsequent formation of the gate. The material of the sacrificial layer 110 includes: si, SiGe, SiC, etc., and are not particularly limited herein.
The nanowire 120 serves as a channel region for a subsequent nanowire transistor. The material of the nanowire 120 includes: si, SiGe, SiC, etc., and are not particularly limited herein. Since the nanowires 120 are not in contact with the substrate 100, the material of the nanowires 120 may be the same as or different from that of the substrate 100, and is not particularly limited herein.
Obviously, since the sacrificial layer 110 and the nano-wire 120 are stacked on each other, it is satisfied that the materials of the sacrificial layer 110 and the nano-wire 120 are different. Preferably, in the embodiment of the present invention, the material of the sacrificial layer 110 is SiGe, and the material of the nanowire 120 is Si.
The thickness of the sacrificial layer 110 and the thickness of the nanowires 120 are both between 4nm and 30nm (here, the thickness is 4nm or more and 30nm or less, i.e., the range includes the end values, and the range is expressed as the same as the value). The thicknesses of the sacrificial layer 110 and the nanowires 120 may be the same or different, and are not particularly limited herein. In one embodiment of the present invention, the sacrificial layer 110 has a thickness of 4nm and the nanowires 120 have a thickness of 30 nm. In another embodiment of the present invention, the sacrificial layer 110 has a thickness of 15nm and the nanowires 120 have a thickness of 20 nm.
The number of layers of the sacrificial layer 110 and the nanowire 120 is not particularly limited, and may be one layer or multiple layers. But it is sufficient that the bottommost sacrificial layer 110 is in contact with the surface of the substrate 100 and the bottommost nanowires 120 are not in contact with the substrate 100.
Specifically, in the embodiment of the present invention, the number of the sacrificial layer 110 and the number of the nanowires 120 are two, that is, a first sacrificial layer 110a covering the surface of the substrate 100 is formed, a first nanowire 120a covering the surface of the first sacrificial layer 110a is formed, a second sacrificial layer 110b covering the surface of the first nanowire 120a is formed, and a second nanowire 120b covering the surface of the second sacrificial layer 110b is formed. The first nanowire 120a and the second nanowire 120b both belong to the nanowire 120. Similarly, the first sacrificial layer 110a and the second sacrificial layer 110b both belong to the sacrificial layer 110.
In the embodiment of the present invention, a dummy gate 150 is further formed on the surface of the topmost nanowire 120 b. The dummy gate 150 is the basis for the subsequent formation of the gate. Specifically, in the embodiment of the present invention, the material of the dummy gate 150 includes polysilicon (Poly-Si) and the like.
Here, the gate electrode is not directly formed, and the dummy gate 150 is used instead to avoid the damage to the gate electrode caused by the subsequent process, which affects the performance of the nanowire transistor.
It should be noted that, in other embodiments of the present invention, the material of the dummy gate 150 may also be other materials as long as the condition that the structure of the dummy gate 150 is not damaged in the subsequent process is satisfied.
In the embodiment of the present invention, before forming the dummy gate 150, the method further includes: forming a protective structure 130. The protective structure 130 covers the top surface of the topmost nanowire 120b and covers the sacrificial layer 110 and the sidewalls of the nanowire 120 in the stack. Here, the protection structure 130 serves to prevent damage to the stacked sacrificial layer 110 and the nanowire 120 due to a subsequent process. In other embodiments of the present invention, the protection structure 130 may be used as a gate dielectric layer of a part of a MOS transistor.
The material of the protective structure 130 includes oxide, nitride, and the like. Specifically, in the embodiment of the present invention, the material of the protection structure 130 is SiO2。
In the embodiment of the present invention, after forming the dummy gate 150, before forming the isolation structure, the method further includes: a first sidewall 140 covering both sidewalls of the dummy gate 150 is formed. The first sidewall 140 serves to protect the dummy gate 150 from being damaged by a subsequent process. The material of the first sidewall spacers 140 is oxide, nitride, etc., and is not particularly limited herein.
Referring to fig. 2, the sacrificial layer 110 and the nanowires 120 stacked between adjacent dummy gates 150 are removed, exposing the substrate 100, and forming source/drain regions 160.
The removal of the sacrificial layer 110 and the nanowires 120 stacked between adjacent dummy gates 150 is to facilitate the subsequent formation of isolation structures within the source/drain regions 160. The process of removing the sacrificial layer 110 and the nanowires 120 stacked between the adjacent dummy gates 150 includes a dry etching process and/or a wet etching process. Specifically, in the embodiment of the present invention, the process of removing the sacrificial layer 110 and the nanowires 120 stacked between the adjacent dummy gates 150 is a dry etching process. And the dry etching is a Reactive Ion Etch (RIE) process.
Source/drain regions 160 provide space for the subsequent formation of isolation structures and source/drains. Since the sacrificial layer 110 and the nanowires 120 are directly formed on the surface of the substrate, the substrate 100 is exposed after the sacrificial layer 110 and the nanowires 120 are removed.
Here, the method of exposing the substrate 100 includes: removing only the sacrificial layer 110 and the nanowires 120 to expose the surface of the substrate 100, i.e., not etching the substrate 100; or after removing the sacrificial layer 110 and the nanowires 120, the substrate 100 is further etched to expose the substrate 100, i.e., a groove is formed on the substrate 100. Here, a method of exposing the substrate 100 is not particularly limited. Preferably, in the embodiment of the present invention, the method of exposing the substrate 100 is: after removing the sacrificial layer 110 and the nanowires 120, the substrate 100 is further etched appropriately, and after removing a portion of the substrate 100, the substrate 100 is exposed, i.e., a groove is formed on the substrate 100. This approach allows the isolation structure subsequently formed at the bottom of the source/drain 160 to be relatively thick, more effectively eliminating leakage of current between the substrate 100 and the source/drain.
The process of etching a portion of substrate 100 may be the same as or different from the process of etching to form source/drain regions 160. In the embodiment of the present invention, the process of etching a portion of the substrate 100 is the same as the process of etching the sacrificial layer 110 and the nanowires 120.
In the embodiment of the present invention, the method further includes: the protective structure 130 is etched away before the sacrificial layer 110 and the nanowires 120 are etched away. The process of etching to remove the protective structure 130 may or may not be the same as the process of etching the sacrificial layer 110 and the nanowires 120. Specifically, in the embodiment of the present invention, the process of etching to remove the protection structure 130 is the same as the process of etching the sacrificial layer 110 and the nanowires 120.
Referring to fig. 3, second sidewalls 170 are formed in the source/drain regions 160.
In the embodiment of the present invention, the second sidewall spacers 170 cover sidewalls of the dummy gate 150, sidewalls of the nanowire 120, sidewalls of the sacrificial layer 110, and a surface of the substrate 100 at the bottom of the source/drain region 160 on both sides of the source/drain region 160.
The second sidewall 170 is the basis for the subsequent formation of sidewall and bottom isolation structures. The second sidewall 170 is made of SiO2SiN, SiON, SiOCN. The thickness of the second sidewall 170 is between 2nm and 20 nm.
The process of forming the second sidewall spacers 170 includes, but is not limited to, an atomic layer deposition process (ALD process), a chemical vapor deposition process (CVD process), and the like. Specifically, in the embodiment of the present invention, the process of forming the second side wall 170 is an ALD process. The second sidewall spacers 170 formed by the ALD process have a more uniform structure.
Referring to fig. 4, a dielectric layer 180 is formed to cover the surface of the second sidewall 170 at the bottom of the source/drain region 160.
In the embodiment of the present invention, the material of the dielectric layer 180 includes organic material, polysilicon, etc. If the material of the dielectric layer 180 is organic, the process for forming the dielectric layer 180 includes a spin coating process; if the material of the dielectric layer 180 is polysilicon, the dielectric layer 180 is formed by directly growing polysilicon. Specifically, in the embodiment of the present invention, the material of the dielectric layer 180 is an organic material, and the forming process of the dielectric layer 180 is a spin coating process. Compared with the direct growth of the polycrystalline Si, the dielectric layer 180 formed by the spin coating process has a more uniform structure.
Here, it should be noted that in other embodiments of the present invention, the material of the dielectric layer 180 may also be other materials, which are not particularly limited as long as the condition for providing the termination position for etching the second sidewall 170 is satisfied.
The top surface of dielectric layer 180 is lower than the top surface of the bottommost nanowire 120 and higher than the bottom surface of the bottommost sacrificial layer 110. Specifically, in the embodiment of the present invention, the top surface of the dielectric layer 180 is not higher than the bottom surface of the bottommost nanowire 120, i.e., not higher than the bottom surface of the nanowire 120 a; and is higher than the bottom surface of the bottommost sacrificial layer 110, i.e., higher than the bottom surface of the sacrificial layer 110 a. Here, the top surface of the dielectric layer 180 is limited to a position where etching is stopped when the second sidewall spacers 170 are subsequently etched. The etching is stopped at this position, and the top surfaces of the remaining second sidewalls 170 at the bottoms of the source/drain regions 160 are also made higher than the top surfaces of the second sidewalls 170 at the bottoms of the source/drain regions 160, so that the cross-sectional shapes of the second sidewalls 170 at the bottoms of the source/drain regions 160 are shallow U-shaped, and the shallow U-shaped sidewalls can more effectively isolate the subsequent source/drain regions from the substrate 100.
It should be noted that in practical processes, it is difficult to make the top surface of the dielectric layer 180 located at the position just described. Therefore, the thicker dielectric layer 180 can be formed first, and then the dielectric layer 180 is etched, and the etching stop position is controlled, so that the top surface of the etched dielectric layer 180 is located at the position. Specifically, in the embodiment of the present invention, the thicker dielectric layer 180 is formed first, and then the dielectric layer 180 is etched back, so that the top surface of the dielectric layer 180 is located at the above position.
Referring to fig. 5, portions of the second sidewalls 170 on both sides of the source/drain regions 160 are removed to form isolation structures.
The purpose of removing part of the second sidewalls 170 is to only leave the second sidewalls 170 at the bottom of the source/drain regions 160 to form isolation structures.
The process of removing portions of the second sidewalls 170 includes dry etching and/or wet etching. Specifically, in the embodiment of the present invention, the process of etching and removing part of the second sidewall 170 is wet etching. The solution used for wet etching comprises: h3PO4、H2O2SC1, deionized water, HCl, HF, NH4And F is mixed with one or more of the F.
In the embodiment of the present invention, when removing a portion of the second sidewall spacers 170, the side surfaces of all the nanowires 120 are exposed. That is, in the present embodiment, the side surfaces of all the nanowires 120a and 120b are exposed. This allows the nanowires 120 to contact the subsequently formed source/drain electrodes for conduction purposes.
As previously described, dielectric layer 180 provides an etch stop for etching a portion of second sidewall 170. Therefore, in the embodiment of the present invention, the remaining second sidewalls at the bottom of the source/drain regions 160 are sidewall spacers 171, and the top surfaces of the sidewall spacers 171 are flush with the top surface of the dielectric layer 180. I.e., the top surface of sidewall spacers 171 is not higher than the bottom surface of the bottommost nanowire 120a and higher than the bottom surface of the bottommost sacrificial layer 110 a.
It should be noted that it is difficult to ensure that the top surfaces of the sidewall spacers 171 are exactly flush with the top surface of the dielectric layer 180 due to the actual etching process. Therefore, in particular, when implementing the nanowire transistor according to an embodiment of the present invention, it is required to ensure that the highest points of the two side surfaces of the isolation structure are lower than the top surface of the bottommost nanowire 120, i.e., the top surface of the nanowire 120 a. Specifically, in the embodiment of the present invention, the highest point of the two side surfaces of the isolation structure is not higher than the bottom surface of the bottommost nanowire 120, i.e., the bottom surface of the nanowire 120 a. And the two side surfaces of the isolation structure are respectively the side surfaces of the side wall isolation structure which are not in contact with the bottom isolation structure.
To this end, in the embodiment of the present invention, the remaining portion of the second sidewall 170 includes: sidewall spacers 171 and bottom spacer 172, and bottom spacer 172 is located between sidewall spacers 171 and connected to sidewall spacers 171. Obviously, the materials of the second sidewall 170, the sidewall spacers 171, and the bottom sidewall 172 are the same, and the materials are as described above.
To this end, isolation structures are formed at the bottom of the source/drain regions 160, including sidewall isolation structures and bottom isolation structures. Notably, the bottom isolation structure covers the surface of the substrate 100 between the sidewall isolation structures and is connected to the sidewall isolation structures. In the embodiment of the present invention, the sidewall isolation structure is a sidewall spacer 171, and the bottom isolation structure is a bottom spacer 172.
In the embodiment of the present invention, the sidewall spacers 171 and the bottom sidewall spacers 172 are located between the subsequent source/drain and the substrate 100, so that the substrate 100 and the source/drain are isolated, the current leakage between the source/drain and the substrate 100 is prevented, and the performance of the nanowire transistor is improved.
Referring to fig. 6, source/drains 1310 are formed in the source/drain regions 160.
Source/drain 1310 is for contact with nanowire 120 (channel region). Therefore, in the embodiment of the present invention, it is preferable that the top surface of the source/drain 1310 is higher than the top surface of the topmost nanowire 120b, that is, the source/drain 1310 covers both sides of the nanowire 120 completely, and the source/drain 1310 covers the surface of the isolation structure.
The process steps for forming the source/drain 1310 include: a source/drain material layer (not shown) is formed overlying the surface of the isolation structure and then doped to form source/drain 1310. In an embodiment of the present invention, the process of forming the source/drain material layer includes an epitaxial growth process. The epitaxial growth process comprises the following steps: a Chemical Vapor Deposition (CVD) epitaxial process or a Molecular Beam Epitaxy (MBE) process. Specifically, in the embodiment of the present invention, the process of forming the source/drain material layer is an MBE process.
The material of the source/drain material layer may be selected according to different types of the source/drain 1310. When the source/drain 1310 is PMOS, the source/drain material layer includes but is not limited to SiGe, Si, etc., and the doped material includes but is not limited to boron (B), gallium (Ga), etc.; when the source/drain 1310 is an NMOS, the material of the source/drain material layer includes, but is not limited to, SiC, Si, etc., and the doped material includes, but is not limited to, phosphorus (P), arsenic (As), rhodium (Rh), etc.
The process of doping the source/drain material layer includes: in situ doping, diffusion, ion implantation, or a combination thereof. Specifically, in the embodiment of the present invention, the process of doping the source/drain material layer is in-situ epitaxial doping.
In one embodiment of the present invention, the source/drain 1310 is a highly doped source/drain 1310. Highly doped means that the ion concentration of the doping is greater than 1 x 1020atoms/cm3。
It should be noted that, since the dielectric layer 180 is formed previously, in the embodiment of the present invention, after removing a portion of the sidewall spacers 170 and before forming the source/drain 1310, the method further includes: dielectric layer 180 is removed.
The dielectric layer 180 is removed to subsequently form source/drain 1310 directly on the surface of the isolation structure. The process of removing dielectric layer 180 includes: dry etching and/or wet etching. Specifically, in the embodiment of the present invention, the process of removing the dielectric layer 180 is dry etching.
Referring to fig. 7, a first dielectric layer 1320 is formed on top of the source/drain 1310.
In the embodiment of the present invention, after forming the source/drain 1310, the method further includes: a first dielectric layer 1320 is formed overlying the source/drain 1310.
The first dielectric layer 1320 serves as a dielectric isolation in the nanowire transistor, while also protecting the source/drain 1310 from damage in subsequent processes.
In an embodiment of the present invention, the material of the first dielectric layer 1320 includes, but is not limited to, SiOxSiOCH, SiN, and the like.
In a specific process implementation, since it is difficult to form the first dielectric layer 1320 only on the surface of the source/drain 1310, the first dielectric layer 1320 is also formed on the top of the dummy gate 150. Since the dummy gate 150 is removed later, the top of the dummy gate 150 is exposed after the first dielectric layer 1320 is formed. Specifically, in the embodiment of the present invention, the top of the dummy gate 150 is exposed by first forming the first dielectric layer 1320 covering the dummy gate 150 and the source/drain 1310, and then removing a portion of the first dielectric layer 1320 to expose the top of the dummy gate 150.
The process of removing portions of the first dielectric layer 1320 includes: dry and/or wet etching, Chemical Mechanical Planarization (CMP), and the like. Specifically, in the embodiment of the present invention, the first dielectric layer 1320 is planarized by a CMP process, thereby exposing the top of the dummy gate 150.
Referring to fig. 8, the dummy gate 150 and the sacrificial layer 110 are removed to form a trench (not shown), and a gate structure is formed in the trench.
The dummy gate 150 and the sacrificial layer 110 are removed to form a gate structure in the trench. The process of removing the dummy gate 150 and the sacrificial layer 110 includes: dry etching and/or wet etching. Specifically, in the embodiment of the present invention, the process of removing the dummy gate 150 and the sacrificial layer 110 includes dry etching.
In an embodiment of the present invention, a gate structure includes: gate dielectric 1330 and gate 1340.
The purpose of the gate dielectric layer 1330 is to isolate the source/drain 1310, the nanowire 120 and the gate 1340, and to avoid excessive parasitic capacitance between the source/drain 1310 and the gate 1340.
In the embodiment of the present invention, the process steps for forming the gate dielectric layer 1330 and the gate 1340 include: an internal dielectric layer (not shown) is formed to cover the trench, and then a high dielectric material layer (not shown, having a dielectric constant k of 15-50) is formed on the surface of the internal dielectric layer. Gate dielectric 1330 and gate 1340 fill the trench. In the embodiment of the present invention, the gate electrode 1340 covers the gate dielectric layer 1330, and the gate dielectric layer 1330 covers the nanowire 120.
Obviously, in the embodiment of the present invention, the gate dielectric layer 1330 includes: an inner dielectric layer and a high dielectric material layer.
The materials of the inner dielectric layer include, but are not limited to: SiON, SiOxEtc., and are not particularly limited herein. Specifically, in the embodiment of the present invention, the material of the internal dielectric layer is SiO2。
Materials of the high dielectric material layer include, but are not limited to: HfO2、ZrO2And so on. Specifically, in the embodiment of the invention, the material of the high dielectric material layer is HfO2。
The process of forming the gate dielectric layer 1330 and the gate electrode 1340 includes: an ALD process, a CVD process, a physical vapor deposition Process (PVD), a Chemical Vapor Deposition (CVD) epitaxy process, a Molecular Beam Epitaxy (MBE) process, etc., are not particularly limited herein. Specifically, in the embodiment of the present invention, the forming process of the gate dielectric layer 1330 and the gate 1340 is an ALD process.
In the embodiment of the present invention, before removing the sacrificial layer 110, the method further comprises removing the protective structure 130 covering the top surface of the topmost nanowire 120b and covering the sidewalls of the stacked sacrificial layer 110 and nanowires 120.
Referring to fig. 9, a metal line 1360 is formed on top of the gate 1340, and a second dielectric layer 1350 is formed covering the gate structure and the first dielectric layer 1320.
The second dielectric layer 1350 is formed to protect the gate 1340 and the metal line 1360.
Notably, the first dielectric layer 1320 and the second dielectric layer 1350 both function as dielectric protection. Therefore, the first dielectric layer 1320 and the second dielectric layer 1350 may or may not be the same material. Specifically, in the embodiment of the present invention, the first dielectric layer 1320 and the second dielectric layer 1350 are made of the same material.
In summary, according to the first embodiment of the present invention, a sidewall isolation structure and a bottom isolation structure are formed between the bottom of the source/drain 1310 and the substrate 100. Compared with the nanowire transistor without the sidewall isolation structure and the bottom isolation structure in the prior art, the isolation structure effectively isolates the substrate 100 from the source/drain 1310, eliminates the leakage of current between the substrate 100 and the source/drain 1310, and improves the performance of the nanowire transistor.
Accordingly, with continued reference to fig. 9, an embodiment of the present invention further provides a nanowire transistor, including: substrate 100, nanowires 120, isolation structures, source/drains 1310, and gate structures.
The substrate 100 is the basis for subsequent gate structures and isolation structures. The material of the substrate 100 includes Si, SiGe, etc., and is not particularly limited herein.
The nanowires 120 serve as channel regions of the semiconductor device. The material of the nanowires 120 includes: si, SiGe, SiC, etc., and are not particularly limited herein. The nanowires 120 are not in contact with the substrate 100. The number of the nanowires 120 is 1 or more, and is not particularly limited herein. When the number of the nanowires 120 is plural, the plural nanowires 120 are longitudinally distributed at intervals inside the gate structure, as shown in fig. 9, the direction indicated by the arrow is a longitudinal direction. Specifically, in the embodiment of the present invention, the number of the nanowires 120 is two, and is 120a and 120b from bottom to top.
The isolation structure is located on the surface of the substrate 100 and is used to isolate the substrate 100 from the source/drain 1310. The isolation structures include sidewall isolation structures and bottom isolation structures, wherein the sidewall isolation structures are located on both sides of the bottom isolation structures, and the bottom isolation structures are located between the sidewall isolation structures and are in contact with the sidewall isolation structures. Specifically, in the embodiment of the present invention, the sidewall isolation structure is a sidewall spacer 171, and the bottom isolation structure is a bottom spacer 172. The side wall isolation structure and the bottom isolation structure are made of the same material and are made of SiO 2SiN, SiON, SiOCN.
The two side surfaces of the isolation structure are two side surfaces of the side wall isolation structure which are not in contact with the bottom isolation structure. The highest point of both sides of the isolation structure is lower than the top surface of the bottommost nanowire 120. Specifically, in the embodiment of the present invention, the highest point of the two side surfaces of the isolation structure is lower than the bottom surface of the bottommost nanowire 120, that is, lower than the bottom surface of the nanowire 120 a.
The source/drain 1310 is located at both sides of the gate structure, and the source/drain 1310 contacts both sides of the nanowire 120. In an embodiment of the present invention, the source/drain 1310 covers an isolation structure. When the source/drain 1310 is PMOS, the material of the source/drain 1310 includes but is not limited to SiGe, Si, etc., and the doped substance includes but is not limited to boron (B), gallium (Ga), etc.; when the source/drain 1310 is an NMOS, the source/drain material includes, but is not limited to, SiC, Si, etc., and the doped material includes, but is not limited to, phosphorus (P), arsenic (As), rhodium (Rh), etc.
A gate structure is located over the substrate 100 and between the source/drain 1310. The gate structure includes a gate dielectric 1330 and a gate 1340.
The purpose of the gate dielectric layer 1330 is to isolate the source/drain 1310, the nanowire 120 and the gate 1340, and to avoid excessive parasitic capacitance between the source/drain 1310 and the gate 1340. In this embodiment of the present invention, the gate dielectric layer 1330 includes: an inner dielectric layer (not shown) and a layer of high dielectric material (not shown).
The material of the inner dielectric layer comprises: SiON, SiOxEtc., and are not particularly limited herein. Specifically, in the embodiment of the present invention, the material of the internal dielectric layer is SiO2。
Materials of the high dielectric material layer include, but are not limited to: HfO2、ZrO2And the like. Specifically, in the embodiment of the invention, the material of the high dielectric material layer is HfO2。
In an embodiment of the present invention, the nanowire transistor further comprises: a first dielectric layer 1320, a second dielectric layer 1350, and a metal line 1360.
A first dielectric layer 1320 covers the top of the source/drain 1310. The first dielectric layer 1320 serves as dielectric isolation in the nanowire transistor, while also protecting the source/drain 1310 from damage in subsequent processes. In an embodiment of the present invention, the material of the first dielectric layer 1320 includes, but is not limited to, SiOxSiOCH, SiN, and the like.
A second dielectric layer 1350 covers the gate structure and the first dielectric layer 1320. The purpose of the second dielectric layer 1350 is to protect the gate 1340 and the metal line 1360.
Notably, the first dielectric layer 1320 and the second dielectric layer 1350 both function as dielectric protection. Therefore, the first dielectric layer 1320 and the second dielectric layer 1350 may or may not be the same material. Specifically, in the embodiment of the present invention, the first dielectric layer 1320 and the second dielectric layer 1350 are made of the same material.
In an embodiment of the present invention, the nanowire transistor further comprises: a protective structure 130 and a first sidewall 140.
The protective structure 130 covers the top surface of the topmost nanowire 120b and covers the sidewalls of the stacked sacrificial layer 110 and nanowires 120. Here, the protection structure 130 serves to prevent damage to the stacked sacrificial layer 110 and the nanowire 120 due to a subsequent process. In other embodiments of the present invention, the protection structure 130 may be used as a gate dielectric layer of a part of a MOS transistor. The material of the protective structure 130 includes oxide, nitride, and the like. Specifically, in the embodiment of the present invention, the material of the protection structure 130 is SiO 2。
The first sidewalls 140 cover both sidewalls of the dummy gate 150. The first sidewall 140 serves to protect the dummy gate 150 from being damaged by a subsequent process. The material of the first sidewall spacers 140 is oxide, nitride, etc., and is not particularly limited herein.
In summary, in the nanowire transistor provided in the first embodiment of the present invention, the sidewall isolation structure and the bottom isolation structure are included between the source/drain and the substrate, so that electrical isolation between the source/drain and the substrate is achieved, current leakage between the source/drain and the substrate is eliminated, and performance of the nanowire transistor is improved.
A second embodiment.
The second embodiment is different from the first embodiment in that the second embodiment uses a bottom barrier layer instead of the bottom sidewall in the first embodiment, thereby realizing isolation between the source/drain and the substrate.
Referring to fig. 10, fig. 10 is a schematic cross-sectional structure diagram of further performing an etching process on the basis of etching to remove the dielectric layer (since the process steps before etching the dielectric layer in the second embodiment are the same as those in the first embodiment, specific reference may be made to the related description of the first embodiment, and details are not repeated here).
In the embodiment of the present invention, the method further includes: after the dielectric layer is removed, the bottom sidewall is removed, exposing the substrate 200.
The purpose of removing the bottom sidewall spacers is to form a bottom isolation structure on the surface of the substrate 200 at the bottom of the source/drain region 260, which can isolate the source/drain from the substrate. The process of removing the bottom sidewall is a Reactive Ion Etch (RIE) process.
Referring to fig. 11, a bottom isolation structure is formed between the sidewall spacers 271 at the bottom of the source/drain region 260.
In an embodiment of the present invention, after removing the dielectric layer, the method further includes: removing bottom sidewalls (not shown) at the bottom of the source/drain regions 260; a bottom barrier layer 272 is then formed on the surface of the substrate 200 between the sidewall spacers 271.
The bottom barrier layer 272 serves to subsequently isolate the source/drain from the substrate 200, reducing leakage of current between the source/drain and the substrate 200.
Both the bottom sidewall spacers (as described in the first embodiment) and the bottom barrier layer 272 may isolate the source/drain from the substrate 200. In the embodiment of the present invention, the bottom barrier layer 272 serves as a bottom isolation structure, and the sidewall spacers 271 serve as sidewall isolation structures, which together form an isolation structure. The position relationship between the sidewall isolation structure and the bottom isolation structure, and the highest points of the top surface or the two side surfaces of the isolation structure are the same as those in the first embodiment, and are not described herein again.
Here, the material of the sidewall spacers 271 is the same as that of the sidewall spacers in the first embodiment, as described above. And the material of the bottom barrier layer 272 is one or more of Si, SiGe, Ge, GaAs, SiC, SiGeC.
Processes for forming the bottom barrier layer 272 include, but are not limited to: atomic layer deposition processes, chemical vapor deposition epitaxy processes, molecular beam epitaxy processes, and the like. Specifically, in the embodiment of the present invention, the process of forming the bottom isolation structure is a molecular beam epitaxy process. The bottom barrier layer 272 grown by an epitaxial process facilitates the subsequent formation of source/drain on the bottom isolation structure.
In the embodiment of the present invention, the types of the bottom isolation structure include: a diffusion barrier layer or a conduction barrier layer; a stacked structure of the diffusion barrier layer and the conduction barrier layer is also possible, and no particular limitation is imposed here.
Here, it is to be noted that the names of the diffusion barrier layer and the conduction barrier layer are consistent with their roles. The diffusion barrier layer can prevent diffusion of particles between the source/drain and the substrate 200; the conduction barrier layer can prevent conduction of parasitic capacitance between the source/drain and the substrate 200.
Specifically, in the embodiment of the present invention, when the bottom barrier layer 272 is a diffusion barrier layer, the bottom barrier layer 272 may be undoped or lightly doped. When the bottom barrier layer 272 is not doped, the bottom barrier layer 272 can isolate the source/drain from the substrate 200, cut off a leakage path of current, and improve the performance of the nanowire transistor. When the bottom barrier layer 272 is lightly doped, the doping type is the same as the ion type of the subsequent source/drain doping. Preferably, when the bottom barrier layer 272 is a P-type semiconductor doped with boron (B), gallium (Ga), the material of the bottom isolation structure is SiC, SiGeC, or the like; when the bottom barrier layer 272 is an N-type semiconductor doped with phosphorus (P), arsenic (As), rhodium (Rh), the material of the bottom barrier layer 272 is SiC or the like, and is not particularly limited herein.
In the embodiment of the present invention, when the bottom barrier layer 272 is lightly doped, the ion concentration of the doping is less than or equal to 1 × 1017atoms/cm3. And medium doping (ion concentration greater than 1 × 10)17atoms/cm3Less than 1X 1020atoms/cm3) Or high doping (ion concentration of 1X 10 or more)20atoms/cm3) Compared with the bottom barrier layer 272, the bottom barrier layer 272 with the shallow doping can reduce the leakage of current and has better performance.
In the embodiment of the present invention, when the bottom barrier layer 272 is a conductive barrier layer, the bottom barrier layer 272 is moderately doped, and the doping type is opposite to the ion type of the source/drain doping to be formed subsequently. Preferably, when the bottom barrier layer 272 is a P-type semiconductor doped with boron (B), gallium (Ga), the material of the bottom barrier layer 272 is Si, SiGe, SiGeC, or the like; when the bottom barrier layer 272 is an N-type semiconductor doped with phosphorus (P), arsenic (As), rhodium (Rh), the material of the bottom barrier layer 272 is Si, SiC, or the like. Furthermore, the bottom barrier 272 is lightly doped with ions at a concentration of 1 × 10 17atoms/cm3～1×1020atoms/cm3In the meantime.
In an embodiment of the present invention, the source of doping the bottom barrier layer 272 includes, but is not limited to: SiH silicon source2Cl2、SiH4、Si2H6(ii) a Germanium source GeH4(ii) a Doping gas source: b is2H6(boron), AsH3(As)、CH3CH3、CH3SiH3(carbon content 0.1-5%), PH3(phosphorus), and the like.
Here, it is noted that the top surface of the bottom barrier layer 272 is not higher than the bottom surface of the bottommost nanowire 220 a. If the top surface of the bottom barrier layer 272 is higher than the bottom surface of the bottommost nanowire 220a, the parasitic resistance between subsequently formed source/drains and the substrate 200 increases, affecting the performance of the nanowire transistor.
As mentioned above, the bottom barrier layer 272 may also be a stacked structure of a diffusion barrier layer and a conduction barrier layer. At this time, the uppermost layer of the stacked structure in contact with the subsequent source/drain may be a diffusion barrier layer or a conduction barrier layer, which is not specifically limited herein, and the selection of specific materials and the doped type are the same as those described above, and are not described herein again.
Referring to fig. 12, source/drains 2310 are formed in the source/drain regions 260.
The function, process, steps, doping concentration and position of the top surface of the source/drain 2310 are the same as those of the first embodiment, and are not described herein again.
The material of the source/drain 2310 is selected according to the material type of the bottom isolation structure, as described above.
Referring to fig. 13, a first dielectric layer 2320 is formed on top of the source/drain 2310.
The function, process, steps and material selection for forming the first dielectric layer 2320 are the same as those in the first embodiment, and are not described herein again.
Referring to fig. 14, dummy gate 250 and sacrificial layer 210 are removed to form trenches (not shown) in which gate dielectric layer 2330 and gate electrode 2340 are formed.
The functions, processes, steps, material selection and the positional relationship between the structures of removing the dummy gate 250 and the sacrificial layer 210 and forming the gate dielectric layer 2330 and the gate electrode 2340 are the same as those of the first embodiment, and are not described herein again.
Referring to fig. 15, a metal line 2360 is formed on the surface of the gate 2340, and a second dielectric layer 2350 is formed to cover the second sub-gate structure and the first dielectric layer 2320.
The function, process, steps and material selection for forming the second dielectric layer 2350 and the metal line 2360 are the same as those in the first embodiment, and are not repeated herein.
In summary, according to the second embodiment of the present invention, the isolation structures existing between the source/drain 2310 and the substrate 200 include sidewall isolation structures and bottom isolation structures. The isolation between the source/drain 2310 and the substrate 200 reduces the leakage of current, and improves the performance of the nanowire transistor.
Accordingly, with continued reference to fig. 15, an embodiment of the present invention further provides a nanowire transistor, and the nanowire transistor provided in the second embodiment of the present invention is different from the nanowire transistor of the first embodiment in that: the bottom sidewall of the first embodiment is replaced by the bottom barrier layer of the second embodiment, and the top surface of the bottom barrier layer is not exactly the same height as the top surface of the bottom sidewall. The positional relationship of other structures is the same as that of the nanowire transistor of the first embodiment, and details are not described here.
The bottom barrier layer 272 serves to subsequently isolate the source/drain from the substrate 200, reducing leakage of current between the source/drain and the substrate 200. In the present embodiment, the bottom barrier layer 272 is a bottom isolation structure, and the types of the bottom isolation structure include: a diffusion barrier layer or a conduction barrier layer; a stacked structure of the diffusion barrier layer and the conduction barrier layer is also possible, and no particular limitation is imposed here.
In an embodiment of the present invention, the top surface of the bottom barrier layer 272 is not higher than the bottom surface of the bottommost nanowire 220 a.
To sum up, in the nanowire transistor provided in the second embodiment, the sidewall isolation structure and the bottom isolation structure effectively isolate the substrate 200 from the source/drain 2310, so that leakage is reduced, and the performance of the nanowire transistor is improved.
A third embodiment.
Compared with the second embodiment, the third embodiment is different in that openings are formed at two sides of each stacked sacrificial layer, and second side walls are filled in the openings to form internal side walls, so that source/drain electrodes and gates are isolated.
Referring to fig. 16, fig. 16 is a schematic cross-sectional structure diagram of a process for further performing an etching process on each stacked sacrificial layer to form an opening on the basis of forming the source/drain region 360 (since the previous process steps of the third embodiment are the same as those of the first embodiment, reference may be specifically made to the related description of the first embodiment, and further description is not repeated here).
In the embodiment of the present invention, after forming the source/drain region 360 and before forming the second sidewall, the method further includes: portions of the sacrificial layer 310 are removed to form openings 361 on both sides of each sacrificial layer.
The opening 361 is formed to fill the second sidewall inside the opening 361.
In the embodiment of the present invention, the depth of the opening 361 is between 2nm and 20nm, which is not particularly limited. In one embodiment of the present invention, the depth of the opening 361 is 2 nm. In another embodiment of the present invention, the depth of the opening 361 is 20 nm.
The process of forming the opening 361 includes dry etching and/or wet etching. Specifically, in the embodiment of the present invention, the process of forming the opening 361 includes wet etching, and is a lateral wet etching process. The lateral direction here refers to the direction indicated by the arrow in fig. 16.
The solution for the transverse wet etching comprises: NH (NH)4OH、NaOH、KOH、H2O2、CH3COOH, deionized water, HCl, HF, NH4And F is mixed with one or more of the F.
Referring to fig. 17, a second sidewall 370 is formed, and the second sidewall 370 fills the opening 361.
In the embodiment of the present invention, the second sidewall 370 is formed to cover the sidewalls of the dummy gate 350, the sidewalls of the nanowire 320, the sidewalls of the sacrificial layer 310 and the surface of the substrate 300 at the bottom of the source/drain region 360 at two sides of the source/drain region 360, and at the same time, the second sidewall 370 is ensured to fill all the openings 361.
The second sidewall 370 fills all the openings 361 to form an inner sidewall in the openings 361 for the purpose of isolating the source/drain from the gate.
In the embodiment of the present invention, the thickness of the second sidewall 370 is between 2nm and 20nm, as described in the first embodiment. The thickness of the second sidewall 370 may be the same as the depth of the opening 361, or may be different from the depth of the opening 361. But should satisfy the condition that the opening 361 is internally filled with the second sidewall 370. Preferably, in the embodiment of the present invention, the thickness of the second sidewall 370 is slightly larger than the depth of the opening 361.
Here, the function, the process, and the material selection for forming the second sidewall 370 are the same as those of the second embodiment, and will not be described herein.
Referring to fig. 18, a dielectric layer 380 is formed to cover the surface of the second sidewall 370 at the bottom of the source/drain region 360.
The function, process and material selection for forming the dielectric layer 380 are the same as those of the first embodiment, and are not described herein.
Referring to fig. 19, a portion of the second sidewall spacers 370 is removed to form isolation structures.
The function, process and steps of removing part of the second sidewall 370 are the same as those of the first embodiment, and are not described herein.
Please refer to the first embodiment for the position relationship of the isolation structures and the height of the top surfaces thereof.
In the embodiment of the present invention, when removing part of the second side wall 370, the inner side wall 373 is reserved. The inner sidewall 373 functions to increase the distance between the subsequent gate and the source/drain, and reduce the excessive parasitic capacitance between the gate and the source/drain.
Obviously, in the embodiment of the present invention, the material of the second sidewall 370 and the material of the inner sidewall 373 are the same, as described above.
Referring to fig. 20, dielectric layer 380 and bottom sidewalls are removed.
The action, process and steps for removing the dielectric layer 380 and the bottom sidewall spacers are the same as those in the second embodiment, and are not described herein again.
It should be noted that after removing the dielectric layer 380, the source/drain may be directly formed on the bottom sidewall spacers (as in the first embodiment), or the bottom sidewall spacers may be continuously removed to form the bottom isolation structure (as in the second embodiment), which is not limited herein. In the embodiment of the present invention, after the dielectric layer 380 is removed, the bottom sidewall spacers are continuously removed to form a bottom isolation structure, exposing the substrate 300.
Referring to fig. 21, bottom isolation structures are formed between the sidewall isolation structures at the bottom of the source/drain regions 360.
The function, type, process, steps, material selection, position of the top surface and doping type of the bottom isolation structure are the same as those of the second embodiment, and are not described herein.
Here, it should be noted that the sidewall spacers 371 serve as sidewall isolation structures, and the bottom barrier layer 372 serves as a bottom isolation structure.
Referring to fig. 22, source/drains 3310 are formed in the source/drain regions 360.
The function, process, and material selection of the source/drain 3310 are the same as those of the second embodiment, and are not described herein.
Referring to fig. 23, a first dielectric layer 3320 is formed on top of the source/drain 3310.
The function, process, steps and material selection of the first dielectric layer 3320 are the same as those in the second embodiment, and are not described herein.
Referring to fig. 24, the dummy gate 350 and the sacrificial layer 310 are removed to form a trench, and a gate dielectric layer 3330 and a gate electrode 3340 are formed in the trench.
The functions, processes, steps, material selection and the positional relationship between the structures of removing the dummy gate 350 and the sacrificial layer 310 and forming the gate dielectric layer 3330 and the gate electrode 3340 are the same as those of the second embodiment, and are not described herein again.
Referring to fig. 25, a metal line 3360 is formed on the surface of the gate 3340, and a second dielectric layer 3350 is formed to cover the second sub-gate structure and the first dielectric layer 3320.
The function, process, steps and material selection for forming the second dielectric layer 3350 and the metal line 3360 are the same as those in the second embodiment, and are not repeated herein.
In summary, according to the third embodiment of the present invention, the isolation structure existing between the source/drain 3310 and the substrate 300 includes: sidewall isolation structures and bottom isolation structures at the bottom of the source/drain regions 360. The isolation between the source/drain 3310 and the substrate 300 reduces current leakage. Meanwhile, an inner sidewall 373 exists between the gate 3340 and the source/drain 3310, increasing the distance between the gate 3340 and the source/drain 3310, solving the problem of excessive parasitic capacitance between the gate 3340 and the source/drain 3310, and improving the performance of the nanowire transistor.
Accordingly, with continued reference to fig. 25, a nanowire transistor is further provided in the embodiment of the present invention, and the nanowire transistor provided in the third embodiment of the present invention is different from the nanowire transistor of the second embodiment in that: and an internal side wall is arranged between the grid structure and the source/drain electrode, so that the distance between the grid structure and the source/drain electrode is increased. The positional relationship of other structures is the same as that of the nanowire transistor of the second embodiment, and details are not described here.
In the embodiment of the present invention, the method further includes: an inner side wall 373.
The inner sidewall 373 is located between the source/drain 3310 and the gate structure. The inner sidewall 373 increases the distance between the gate structure and the source/drain 3310, reduces the excessive parasitic capacitance between the two, and improves the performance of the nanowire transistor.
As described above, in the nanowire transistor provided in the third embodiment, the sidewall isolation structure and the bottom isolation structure effectively isolate the substrate 300 from the source/drain 3310, and thus, leakage current is reduced; the inner sidewall 373 increases the distance between the source/drain 3310 and the gate structure, and reduces the excessive parasitic capacitance between the source/drain 3310 and the gate structure.
Thus far, the present invention has been described in detail. Some details well known in the art have not been described in order to avoid obscuring the concepts of the present invention. It will be fully apparent to those skilled in the art from the foregoing description how to practice the presently disclosed embodiments.
Although some specific embodiments of the present invention have been described in detail by way of illustration, it should be understood by those skilled in the art that the above illustration is only for the purpose of illustration and is not intended to limit the scope of the invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (29)
1. A nanowire transistor, comprising:
a gate structure disposed on the substrate;
the source/drain electrodes are positioned on two sides of the grid structure;
the nanowire is arranged inside the grid electrode structure, and two side surfaces of the nanowire are in contact with the source/drain electrode; and
an isolation structure formed between the substrate and the source/drain to isolate the substrate and the source/drain;
wherein, the isolation structure includes: the semiconductor structure comprises side wall isolation structures and bottom isolation structures, wherein the side wall isolation structures are positioned at two sides of the isolation structures, and the bottom isolation structures are positioned between the side wall isolation structures and are in contact with the side wall isolation structures;
the sidewall isolation structure is a sidewall spacer, the bottom isolation structure is a bottom barrier layer, and the bottom barrier layer comprises a diffusion barrier layer and/or a conduction barrier layer.
2. The nanowire transistor of claim 1, wherein the number of the nanowires is 1 or more, and when the number of the nanowires is plural, the nanowires are longitudinally distributed at intervals inside the gate structure.
3. The nanowire transistor of claim 1, wherein the isolation structure covers the substrate under the source/drain such that the source/drain is not in contact with the substrate.
4. The nanowire transistor of claim 3, wherein the highest point of both sides of the isolation structure is lower than the top surface of the bottommost nanowire.
5. The nanowire transistor of claim 4, wherein the highest point of both sides of the isolation structure is no higher than the bottom surface of the bottommost nanowire.
6. The nanowire transistor of claim 1, wherein the two sides of the isolation structure are respectively sides of the sidewall isolation structure that are not in contact with the bottom isolation structure.
7. The nanowire transistor of claim 1, wherein when the sidewall isolation structure is the sidewall spacer and the bottom isolation structure is the bottom barrier layer, the sidewall isolation structure is made of SiO2SiN, SiON and SiOCN, and the material of the bottom isolation structure is one or more of Si, SiGe, Ge, GaAs, SiC and SiGeC.
8. The nanowire transistor of claim 1, further comprising: and the internal side wall is positioned between the source/drain electrode and the grid electrode structure contacted with the bottom surface of the nanowire.
9. The nanowire transistor of claim 1, wherein the gate structure comprises: the grid electrode structure comprises a grid electrode and a grid medium layer covering the surface of the grid electrode.
10. The nanowire transistor of claim 1, further comprising: a protective structure covering a top surface of a topmost one of the nanowires.
11. The nanowire transistor of claim 10, further comprising:
the first side wall covers two side walls of the grid structure above the protection structure;
a first dielectric layer covering the source/drain electrodes;
the second dielectric layer covers the gate structure, the first dielectric layer and the surfaces of the first side walls; and
a metal line extending through the second dielectric layer and contacting the gate structure.
12. A method of fabricating a nanowire transistor, comprising:
Forming a sacrificial layer and a nanowire stacked on each other on a substrate;
forming a dummy gate over the sacrificial layer and the nanowire of the stack;
removing the sacrificial layer and the nanowires between the adjacent dummy gates to form source/drain regions;
forming an isolation structure on the surface of the substrate at the bottom of the source/drain region to isolate the source/drain region from the substrate; and
forming a source/drain electrode in the source/drain region, wherein the source/drain electrode is positioned above the isolation structure and is contacted with the side surface of the adjacent nanowire;
wherein the isolation structure formed comprises:
forming a side wall isolation structure and a bottom isolation structure, wherein the side wall isolation structure is positioned at two sides of the bottom isolation structure, and the bottom isolation structure is positioned between the side wall isolation structures and is in contact with the side wall isolation structures;
the sidewall isolation structure is a sidewall spacer, the bottom isolation structure is a bottom barrier layer, and the bottom barrier layer comprises a diffusion barrier layer and/or a conduction barrier layer.
13. The method of claim 12, wherein the bottom-most sacrificial layer is in contact with a surface of the substrate and the bottom-most nanowire is not in contact with the substrate.
14. The method for manufacturing a nanowire transistor according to claim 12, wherein the number of the stacked nanowires is 1 or more.
15. The method of claim 12, wherein the isolation structure covers the substrate under the source/drain region.
16. The method of manufacturing a nanowire transistor according to claim 12,
the step of forming the sidewall isolation structure and the bottom isolation structure comprises:
forming a second side wall, wherein the second side wall covers the pseudo gate side surfaces, the nanowire side surfaces, the sacrificial layer side surfaces and the substrate surface at the bottom of the source/drain region on two sides of the source/drain region;
forming a dielectric layer covering the surface of the second side wall at the bottom of the source/drain region, wherein the top surface of the dielectric layer is lower than the top surface of the bottommost nanowire and higher than the bottom surface of the bottommost sacrificial layer; and
and removing parts of the second side walls on two sides of the source/drain region to enable the top surfaces of the second side walls left on two sides of the source/drain region to be flush with the top surface of the dielectric layer so as to form the side wall side walls and the bottom side walls, wherein the second side walls left on two sides of the source/drain region are the side wall side walls, the side wall side walls are the side wall isolation structures, the second side walls located at the bottom of the dielectric layer are the bottom side walls, and the bottom side walls are the bottom isolation structures.
17. The method of claim 16, wherein the isolation structure has two sides with the highest point lower than the top surface of the bottommost nanowire.
18. The method of claim 16, wherein the highest point of the two sides of the isolation structure is not higher than the bottom surface of the bottom nanowire.
19. The method of claim 18, wherein the two sides of the isolation structure are the sides of the sidewall isolation structure that are not in contact with the bottom isolation structure.
20. The method of claim 16, wherein the sidewall spacer structure is made of SiO2SiN, SiON and SiOCN, and the material of the bottom isolation structure is one or more of Si, SiGe, Ge, GaAs, SiC and SiGeC.
21. The method of fabricating a nanowire transistor according to claim 16,
the step of forming the sidewall isolation structure and the bottom isolation structure further comprises:
removing the dielectric layer;
removing the bottom side wall and exposing the substrate; and
And forming the bottom barrier layer on the surface of the substrate between the side wall spacers, wherein the bottom barrier layer is the bottom isolation structure.
22. The method of claim 12, wherein the diffusion barrier layer is doped with ions of a type opposite to that of the source/drain, and the ions doped in the diffusion barrier layer are one or more of boron (B) and gallium (Ga).
23. The method of claim 12, wherein the conduction barrier layer is doped with the same ion type as the source/drain doping, and comprises: one or more of boron (B), gallium (Ga), or one or more of arsenic (As), rhodium (Rh).
24. The method of fabricating a nanowire transistor of claim 16, further comprising:
removing part of the sacrificial layer before forming the second side wall so as to form openings on two sides of each sacrificial layer; and
and when the second side walls are formed, filling each opening to form the inner side walls.
25. The method of claim 24, wherein the depth of the opening is in a range of 2nm to 20 nm.
26. The method of manufacturing a nanowire transistor according to claim 12,
after forming the source/drain, further comprising:
forming a first dielectric layer covering the source/drain electrodes;
removing the dummy gate and the sacrificial layer to form a trench; and
and forming a gate structure in the groove.
27. The method of fabricating a nanowire transistor of claim 26,
after forming the gate structure, further comprising:
forming a second dielectric layer overlying the gate structure and the first dielectric layer; and
forming a metal line through the second dielectric layer, the metal line contacting the gate structure.
28. The method of manufacturing a nanowire transistor according to claim 12,
before forming the dummy gate, the method further comprises:
forming a protective structure covering the top surfaces of the stacked sacrificial layers and nanowires.
29. The method of manufacturing a nanowire transistor according to claim 12,
after forming the dummy gate, before forming the isolation structure, further comprising: and forming first side walls covering two side surfaces of the pseudo gate.
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| US20140264253A1 (en) * | 2013-03-14 | 2014-09-18 | Seiyon Kim | Leakage reduction structures for nanowire transistors |
| CN106611792A (en) * | 2015-10-23 | 2017-05-03 | 三星电子株式会社 | Semiconductor device and manufacturing method therefor |
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| CN104054181A (en) * | 2011-12-30 | 2014-09-17 | 英特尔公司 | Variable gate width for gate all-around transistors |
| US20140264253A1 (en) * | 2013-03-14 | 2014-09-18 | Seiyon Kim | Leakage reduction structures for nanowire transistors |
| CN106611792A (en) * | 2015-10-23 | 2017-05-03 | 三星电子株式会社 | Semiconductor device and manufacturing method therefor |
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