CN109755290A - Nano-wire transistor and preparation method thereof - Google Patents
Nano-wire transistor and preparation method thereof Download PDFInfo
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- CN109755290A CN109755290A CN201711068065.XA CN201711068065A CN109755290A CN 109755290 A CN109755290 A CN 109755290A CN 201711068065 A CN201711068065 A CN 201711068065A CN 109755290 A CN109755290 A CN 109755290A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0646—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
Abstract
The invention discloses a kind of nano-wire transistors and preparation method thereof, comprising: the sacrificial layer and nano wire being stacked with are formed in substrate；Pseudo- grid are formed, pseudo- grid are located above the sacrificial layer and nano wire stacked；The sacrificial layer and nano wire between adjacent pseudo- grid are removed, to form source/drain region；Isolation structure is formed, isolation structure is located at the substrate surface of source/drain region bottom, source/drain region and substrate is isolated；With form source/drain in source/drain region, source/drain is located above isolation structure, and contacts with the side of adjacent nano wire.Source/drain and substrate is isolated in isolation structure, avoids between the two that there is a phenomenon where leakage of current.Meanwhile there are internal side wall between gate structure and source/drain, solve the problems, such as that parasitic capacitance is excessive between source/drain and gate structure.
Description
Technical field
The present invention relates to field of semiconductor manufacture, in particular to a kind of nano-wire transistor and preparation method thereof.
Background technique
All the time, transistor size is reduced, the integrated level of raising integrated circuit is the master of the eternal pursuit of semicon industry
Topic.From FinFET (fin transistor) to NWFET (nano wire transistor), the physical size of grid constantly reduces.In NWFET
In, gate and source/drain region width are smaller, this effectively enhances the adjusting function of grid.But own dimensions
Reduction is easy to produce parasitic capacitance, influences the performance of transistor.Currently, in order to solve this problem, researcher proposes in grid
The technical solution of side wall is formed on pole bottom, cuts off the access of parasitic transistor electric current, improves the DC characteristic of NWFET.
But in the prior art at present, NWFET nano-wire transistor source/drain is directly contacted with substrate, between the two
It is not isolated effectively.When nano-wire transistor work, the place of nano-wire transistor source/drain and substrate contact holds
Leaky easily occurs.
Therefore, the prior art needs one kind and is able to achieve between substrate and nano-wire transistor source/drain to form electric isolation,
The method for reducing electric leakage.
Summary of the invention
The present invention provides a kind of nano-wire transistor and preparation method thereof, realizes the electricity between source/drain and substrate
Isolation, and reduce capacitor excessive between nano-wire transistor bottom grid and source/drain.
A kind of nano-wire transistor is provided in the present invention, comprising: the gate structure being set on substrate；Source/drain, source/
Drain electrode is located at the two sides of gate structure；Nano wire, nano wire are set to inside gate structure, the two sides of nano wire with source/
Drain contact；And isolation structure, isolation structure are formed between substrate and source/drain, with isolation liner bottom and source/drain.
According to an aspect of the present invention, nano wire number is one or more, when nano wire is multiple, multiple nanometers
Line longitudinally spaced distributions are inside gate structure.
According to an aspect of the present invention, isolation structure covering source/drain below substrate so that source/drain not with lining
Bottom contact.
According to an aspect of the present invention, the highest point of isolation structure two sides is lower than the top table of bottommost nano wire
Face.
According to an aspect of the present invention, the highest point of isolation structure two sides is not higher than the bottom table of bottommost nano wire
Face.
According to an aspect of the present invention, isolation structure includes: sidewall isolation structure and bottom isolation structure, wherein side
Wall isolation structure is located at the two sides of isolation structure, bottom isolation structure between sidewall isolation structure, and with side wall isolation junction
Structure is in contact.
According to an aspect of the present invention, the two sides of isolation structure be respectively sidewall isolation structure with bottom isolation junction
Non-contacting two sides of structure.
According to an aspect of the present invention, sidewall isolation structure be side wall side wall, bottom isolation structure be bottom side wall or
Bottom barrier.
According to an aspect of the present invention, bottom barrier includes diffusion barrier layer and/or conducting barrier layer.
According to an aspect of the present invention, further includes: when sidewall isolation structure is side wall side wall, and bottom isolation structure is
When the side wall of bottom, sidewall isolation structure is identical with the material of bottom isolation structure, is SiO2, one of SiN, SiON, SiOCN
Or it is a variety of.
According to an aspect of the present invention, when sidewall isolation structure be side wall side wall, and bottom isolation structure be bottom hinder
When barrier, the material of sidewall isolation structure is SiO2, one of SiN, SiON, SiOCN or a variety of, the material of bottom isolation structure
Material is one of Si, SiGe, Ge, GaAs, SiC, SiGeC or a variety of.
According to an aspect of the present invention, further includes: internal side wall, internal side wall be located at source/drain and with nano wire
Between the gate structure that bottom surface is in contact.
According to an aspect of the present invention, gate structure includes: the gate dielectric layer of grid and covering gate surface.
According to an aspect of the present invention, further includes: protection structure, the top of the nano wire of protection structure covering top
Surface.
According to an aspect of the present invention, further includes: the first side wall, the grid knot of the first side wall covering protection superstructure
The two sidewalls of structure；First dielectric layer, the first dielectric layer cover source/drain；Second dielectric layer, the second dielectric layer cover grid knot
Structure, the first dielectric layer and the first side wall surface；And metal wire, metal wire are contacted through the second dielectric layer and with gate structure.
The invention also discloses a kind of preparation methods of nano-wire transistor, comprising: is stacked in substrate formation sacrificial
Domestic animal layer and nano wire；Pseudo- grid are formed, pseudo- grid are located above the sacrificial layer and nano wire stacked；Remove the sacrifice between adjacent pseudo- grid
Layer and nano wire, to form source/drain region；Isolation structure is formed, isolation structure is located at the substrate surface of source/drain region bottom,
Source/drain region and substrate is isolated；With form source/drain in source/drain region, source/drain is located above isolation structure, and with
The side of adjacent nano wire contacts.
According to an aspect of the present invention, the sacrificial layer and substrate surface contact of bottommost, bottommost nano wire not with lining
Bottom contact.
According to an aspect of the present invention, the number of the nano wire of stacking is one or more.
According to an aspect of the present invention, the substrate below isolation structure covering source/drain region.
According to an aspect of the present invention, the isolation structure of formation includes: to form sidewall isolation structure and bottom isolation junction
Structure, sidewall isolation structure are located at the two sides of bottom isolation structure, the bottom isolation structure of formation between sidewall isolation structure,
And it is in contact with sidewall isolation structure.
According to an aspect of the present invention, it forms sidewall isolation structure and the step of bottom isolation structure includes: to form the
Two side walls, the second side wall cover pseudo- grid side, nano wire side, sacrificial layer side and the source/drain region of source/drain region two sides
Base substrate surface；The dielectric layer on covering the second side wall of source/drain region bottom surface is formed, the top surface of dielectric layer is lower than most
The top surface of the nano wire of bottom, and it is higher than the bottom surface of the sacrificial layer of bottommost；With the portion for removing source/drain region two sides
Divide the second side wall, keeps source/drain region two sides remaining second side coping surface concordant with the top surface of dielectric layer, with shape
At side wall side wall and bottom side wall, wherein remaining second side wall in source/drain region two sides is side wall side wall, and side wall side wall is
Sidewall isolation structure, the second side wall positioned at dielectric layer bottom is bottom side wall, and bottom side wall is bottom isolation structure.
According to an aspect of the present invention, the highest point of isolation structure two sides is lower than the top table of bottommost nano wire
Face.
According to an aspect of the present invention, the highest point of isolation structure two sides is not higher than the bottom table of bottommost nano wire
Face.
According to an aspect of the present invention, the two sides of isolation structure be respectively sidewall isolation structure with bottom isolation junction
The non-contacting side of structure.
According to an aspect of the present invention, sidewall isolation structure be side wall side wall, bottom isolation structure be bottom side wall or
Bottom barrier.
According to an aspect of the present invention, when sidewall isolation structure be side wall side wall, and bottom isolation structure be bottom side
When wall, sidewall isolation structure is identical as the material of bottom isolation structure, is SiO2, one of SiN, SiC, SiOCN or a variety of.
According to an aspect of the present invention, when sidewall isolation structure be side wall side wall, and bottom isolation structure be bottom hinder
When barrier, the material of sidewall isolation structure is SiO2, one of SiN, SiON, SiOCN or a variety of, the material of bottom isolation structure
Material is one of Si, SiGe, Ge, GaAs, SiC, SiGeC or a variety of.
According to an aspect of the present invention, the step of forming sidewall isolation structure and bottom isolation structure further include: remove
Dielectric layer；Remove bottom side wall, exposure substrate；And the substrate surface between side wall side wall forms bottom barrier, bottom resistance
Barrier is bottom isolation structure.
According to an aspect of the present invention, bottom barrier includes diffusion barrier layer and/or conducting barrier layer.
According to an aspect of the present invention, diffusion barrier layer and the ionic type of source drain doping are on the contrary, diffusion barrier layer
The ion of interior doping is one of boron (B), gallium (Ga) or a variety of.
According to an aspect of the present invention, conducting barrier layer is identical as the ionic type of source drain doping, doped with: boron
(B), one of gallium (Ga) or one of a variety of or arsenic (As), rhodium (Rh) or a variety of.
According to an aspect of the present invention, further includes: before forming the second side wall, partial sacrificial layer is removed, every
The two sides of layer sacrificial layer form opening；When with forming the second side wall, each opening is filled to form internal side wall.
According to an aspect of the present invention, the depth bounds of opening are 2nm~20nm.
According to an aspect of the present invention, after forming source/drain, further includes: form covering source/drain first is situated between
Electric layer；Pseudo- grid and sacrificial layer are removed, to form groove；Gate structure is formed in the trench.
According to an aspect of the present invention, after formation of the gate structure, further includes: form covering gate structure and first
Second dielectric layer of dielectric layer；Run through the metal wire of the second dielectric layer with formation, metal wire is contacted with gate structure.
According to an aspect of the present invention, it is formed before pseudo- grid, further includes: form protection structure, protection structure covers heap
The top surface of folded sacrificial layer and nano wire.
According to an aspect of the present invention, after forming pseudo- grid, before forming isolation structure, further includes: formation is covered
Cover the first side wall of pseudo- grid two sidewalls.
Compared with prior art, the advantages of technical solution of the embodiment of the present invention has is as follows:
Due to having isolation structure in the nano-wire transistor of the embodiment of the present invention, isolation structure is located at substrate and source/drain
Between pole, with isolation liner bottom and source/drain.The purpose of isolation structure is that source/drain and substrate is isolated, and elimination source/
The leakage of electric current between drain electrode and substrate.
Further, the highest point of isolation structure two sides is lower than the bottom surface of bottommost nano wire.Such position
Distribution can effectively prevent bottom barrier top surface excessively high and increase the dead resistance inside nano-wire transistor, thus more preferably
Raising nano-wire transistor performance.
Further, further include internal side wall in nano-wire transistor, internal side wall be located at source/drain and with nano wire
Between the gate structure that bottom surface is in contact.Can play the role of that source/drain and gate structure is isolated.
The embodiment of the present invention is formed with isolation structure when forming nano-wire transistor, and isolation structure is located at isolation structure
Substrate surface positioned at source/drain region bottom, source/drain region and substrate is isolated.The purpose of formation isolation structure is subsequent
Source/drain and substrate are isolated, the leakage of electric current between source/drain and substrate is eliminated.
Further, the dielectric layer on covering the second side wall of source/drain region bottom surface is formed, the top surface of dielectric layer is low
In the top surface of the nano wire of bottommost, and it is higher than the bottom surface for the sacrificial layer being in contact with substrate.Form dielectric layer
Purpose is to remove part second side wall for subsequent etching to provide etching final position, also is located at side wall side coping surface together
The position of sample.
Further, the highest point of sidewall isolation structure and the non-contact side of bottom isolation structure is not higher than and substrate contact
Sacrificial layer top surface.The height of limitation sidewall isolation structure top surface is to promote source/drain in order to avoid surface is excessively high
The conducting of pole and channel, and then reach better effect.
Further, before forming the second side wall, partial sacrificial layer is removed, is opened with being formed in the two sides of every layer of sacrificial layer
Mouthful；When forming the second side wall, fills all openings and form private side wall.The purpose done so is in the grid knot being subsequently formed
Internal side wall is formed between structure and source/drain, is increased the distance between source/drain and gate structure, is efficiently solved nano wire
The excessive problem of capacitor between transistor gate and source/drain.
Detailed description of the invention
Fig. 1-Fig. 9 is the schematic diagram of the section structure of nano-wire transistor forming process according to an embodiment of the invention；
Figure 10-Figure 15 is the cross-section structure signal of the nano-wire transistor forming process of another embodiment according to the present invention
Figure；
Figure 16-Figure 25 is the cross-section structure signal of the nano-wire transistor forming process of further embodiment according to the present invention
Figure.
Specific embodiment
As previously mentioned, the phenomenon that there are current leakages between existing nano-wire transistor substrate and source/drain.
It has been investigated that the reason of causing the above problem are as follows: between the substrate and source/drain of nano-wire transistor not into
Row is effectively isolated.It is therefore proposed that forming the scheme of isolation structure between substrate and source/drain, can solve the above problems.
It has also been found that, it is closer between nanowire crystal tube grid and source/drain after further research, without effective
Isolation structure, parasitic capacitance are excessive.It is therefore proposed that forming internal side wall between gate bottom and source/drain, can solve
State problem.
In order to solve this problem, the present invention provides a kind of nano-wire transistors and preparation method thereof, in substrate and source/drain
Effective isolation structure is formed between pole, and substrate is avoided directly to contact with source/drain and lead to letting out for source/drain base current
Leakage.Meanwhile internal side wall is formed between nanowire crystal tube grid and source/drain, to grid and source/drain carry out electricity every
From solving the problems, such as that capacitor is excessive between nano-wire transistor gate bottom and source/drain.
Carry out the various exemplary embodiments of detailed description of the present invention now with reference to attached drawing.It should be understood that unless in addition specific
Illustrate, the component and the positioned opposite of step, numerical expression and numerical value otherwise illustrated in these embodiments is not understood that
For limitation of the scope of the invention.
In addition, it should be understood that for ease of description, the size of all parts shown in attached drawing is not necessarily according to reality
The proportionate relationship on border is drawn, such as certain layers of thickness or width can be exaggerated relative to other layers.
The description of exemplary embodiment is merely illustrative below, in any sense all not as to the present invention and
Its any restrictions applied or used.
Technology, method and apparatus known to person of ordinary skill in the relevant may be not discussed in detail, but suitable
In the case of these technologies, method and apparatus, these technologies, method and apparatus should be considered as a part of this specification.
It should be noted that similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined or illustrates in attached drawing, then will not need that it is further discussed in the explanation of subsequent attached drawing.
First embodiment.
Referring to FIG. 1, substrate 100, forms the sacrificial layer 110 and nano wire 120 being stacked with, sacrificial on substrate 100
Pseudo- grid 150 are formed above domestic animal layer 110 and nano wire 120.
Substrate 100 is the basis for being subsequently formed grid, source/drain and other techniques.The material of substrate 100 include Si,
SiGe etc. herein and is not particularly limited.
Sacrificial layer 110 is the basis for being subsequently formed grid.The material of sacrificial layer 110 includes: Si, SiGe, SiC etc., at this
In and be not particularly limited.
Channel region of the nano wire 120 as subsequent nano-wire transistor.The material of nano wire 120 includes: Si, SiGe, SiC
Deng herein and being not particularly limited.Since nano wire 120 is not contacted with substrate 100, so the material and lining of nano wire 120
The material at bottom 100 can be identical or not identical, is not particularly limited herein.
It will be evident that sacrificial layer 110 and nano wire should be met because sacrificial layer 110 is stacked with nano wire 120
120 material is different.Preferably, in embodiments of the present invention, the material of sacrificial layer 110 is SiGe, nano wire 120
Material is Si.
The thickness of sacrificial layer 110 and nano wire 120 (herein, with a thickness of 4nm is more than or equal to, is less than in 4nm~30nm
Equal to 30nm, that is, range includes endpoint value, and range statement hereafter is identical as meaning herein) between.Sacrificial layer 110 with
The thickness of nano wire 120 can be identical or not identical, is not specifically limited herein.In one embodiment of the present of invention
In, sacrificial layer 110 with a thickness of 4nm, nano wire 120 with a thickness of 30nm.In another embodiment of the present invention, sacrificial layer
110 with a thickness of 15nm, nano wire 120 with a thickness of 20nm.
Sacrificial layer 110 and the number of plies of nano wire 120 are not specifically limited, and be can be one layer and are also possible to multilayer.But it should expire
The sacrificial layer 110 of sufficient bottommost is contacted with the surface of substrate 100, and the nano wire 120 of bottommost is not contacted with substrate 100.
Specifically, in embodiments of the present invention, the number of plies of sacrificial layer 110 and nano wire 120 is respectively two layers, that is, is formed and covered
The first sacrificial layer 110a on 100 surface of cover lining bottom re-forms the first nano wire 120a on the first surface sacrificial layer 110a of covering, then
The the second sacrificial layer 110b for forming the first surface nano wire 120a of covering re-forms the second of the second surface sacrificial layer 110b of covering
Nano wire 120b.First nano wire 120a, the second nano wire 120b belong to nano wire 120.Likewise, the first sacrificial layer
110a, the second sacrificial layer 110b belong to sacrificial layer 110.
In embodiments of the present invention, the surface nano wire 120b of top is also formed with pseudo- grid 150.Pseudo- grid 150 are subsequent
Form the basis of grid.Specifically, in embodiments of the present invention, the material of pseudo- grid 150 includes polysilicon (Poly-Si) etc..
Herein, grid why is not directly formed, and is first to avoid subsequent technique process with the purpose that pseudo- grid 150 replace
Grid is caused to damage, influences the performance of nano-wire transistor.
It should be noted that in other embodiments of the invention, the material of pseudo- grid 150 can also be other materials, only
Meet the condition that pseudo- 150 structure of grid is not damaged in the subsequent process.
In embodiments of the present invention, it is formed before pseudo- grid 150, further includes: form protection structure 130.Protection structure 130 is covered
The top surface and the sacrificial layer 110 of covering stacking and the side wall of nano wire 120 of lid top nano wire 120b.Herein, it protects
The effect of protection structure 130 is in order to avoid sacrificial layer 110 and nano wire 120 of the subsequent technique to stacking damage.In this hair
In bright other embodiments, protection structure 130 can be used as the gate dielectric layer of part MOS transistor.
The material for protecting structure 130 includes oxide, nitride etc..Specifically, in embodiments of the present invention, protecting structure
130 material is SiO2。
In embodiments of the present invention, it is formed after pseudo- grid 150, before forming isolation structure, further includes: it is pseudo- to form covering
First side wall 140 of 150 two sidewalls of grid.The effect of first side wall 140 is that pseudo- grid 150 is protected not destroyed by subsequent technique.The
The material of one side wall 140 is oxide, nitride etc., herein and is not particularly limited.
Referring to FIG. 2, the sacrificial layer 110 and nano wire 120 stacked between adjacent pseudo- grid 150 is removed, exposure substrate 100,
Form source/drain region 160.
Remove the sacrificial layer 110 stacked between adjacent pseudo- grid 150 and nano wire 120 be easy for it is subsequent in source/drain region 160
Interior formation isolation structure.The technique for removing the sacrificial layer 110 and nano wire 120 that stack between adjacent pseudo- grid 150 includes that dry method is carved
Etching technique and/or wet-etching technology.Specifically, in embodiments of the present invention, removing the sacrifice stacked between adjacent pseudo- grid 150
The technique of layer 110 and nano wire 120 is dry etch process.And dry etching is reactive ion etching (Reactive Ion
Etch, RIE) technique.
Source/drain region 160 provides space to be subsequently formed isolation structure and source/drain.Due to sacrificial layer 110 and nanometer
Line 120 is directly formed in substrate surface, so substrate 100 is just exposed after removing sacrificial layer 110 and nano wire 120.
Herein, the method for exposing substrate 100 includes: only to remove sacrificial layer 110 and nano wire 120, exposes substrate
100 surface does not perform etching substrate 100；Or it after removing sacrificial layer 110 and nano wire 120, is further continued for substrate
100 are suitably etched, and substrate 100 is exposed, i.e., form groove on substrate 100.Herein, to the side of exposure substrate 100
Method is simultaneously not specifically limited.Preferably, in embodiments of the present invention, the method for exposure substrate 100 are as follows: removing sacrificial layer 110
It after nano wire 120, is further continued for suitably etching substrate 100, after removing section substrate 100, exposes substrate 100, i.e.,
Groove is formed on substrate 100.This method keeps the subsequent isolation structure formed in 160 bottom of source/drain relatively thick, more effectively
Eliminate the leakage of electric current between substrate 100 and source/drain in ground.
The technique that the technique of etched portions substrate 100 forms source/drain region 160 with etching may be the same or different.
In embodiments of the present invention, the technique of etched portions substrate 100 and etching sacrificial layer 110 are identical as the technique of nano wire 120.
In embodiments of the present invention, further includes: before etching removes sacrificial layer 110 and nano wire 120, etching is except deprotection
Structure 130.Etching can be identical as the technique of etching sacrificial layer 110 and nano wire 120 except the technique of deprotection structure 130,
It can not be identical.Specifically, in embodiments of the present invention, etching except deprotection structure 130 technique and etching sacrificial layer 110 and
The technique of nano wire 120 is identical.
Referring to FIG. 3, forming the second side wall 170 in source/drain region 160.
In embodiments of the present invention, 150 side wall of pseudo- grid, the nano wire of the second side wall 170 covering 160 two sides of source/drain region
100 surface of 120 side walls, 110 side wall of sacrificial layer and 160 base substrate of source/drain region.
Second side wall 170 is the basis for being subsequently formed sidewall isolation structure and bottom isolation structure.The material of second side wall 170
Material is SiO2, one of SiN, SiON, SiOCN or a variety of.The thickness of second side wall 170 is between 2nm~20nm.
The technique for forming the second side wall 170 includes but is not limited to atom layer deposition process (ALD technique), chemical vapor deposition
Technique (CVD technique) etc..Specifically, in embodiments of the present invention, the technique for forming the second side wall 170 is ALD technique.ALD work
170 structure of the second side wall that skill is formed is more uniform.
Referring to FIG. 4, forming the dielectric layer 180 on covering 160 the second side wall of bottom of source/drain region, 170 surface.
The purpose for forming dielectric layer 180 is that removing part second side wall 170 for subsequent etching provides etching final position,
The top surface of 160 bottom remainder side wall of source/drain region is set to be in suitable position.
In embodiments of the present invention, the material of dielectric layer 180 includes organic matter, polysilicon etc..If the material of dielectric layer 180
For organic matter, then the technique for forming dielectric layer 180 includes spin coating proceeding；If the material of dielectric layer 180 is polysilicon, using straight
The mode for connecing growing polycrystalline silicon forms dielectric layer 180.Specifically, in embodiments of the present invention, the material of dielectric layer 180 is organic
Object, 180 formation process of dielectric layer are spin coating proceeding.Compared with directly growing polycrystalline Si, 180 knot of dielectric layer of spin coating proceeding formation
Structure is more uniform.
Herein, it should be noted that in other embodiments of the invention, the material of dielectric layer 180 can also be it
His material, is not specifically limited herein, provides the condition of final position as long as can satisfy for the second side wall 170 of etching.
The top surface of dielectric layer 180 is lower than the top surface of the nano wire 120 of bottommost, and is higher than the sacrifice of bottommost
The bottom surface of layer 110.Specifically, in embodiments of the present invention, the top surface of dielectric layer 180 is not higher than bottommost nano wire
120 bottom surface is not higher than the bottom surface of nano wire 120a；And be higher than the bottom surface of bottommost sacrificial layer 110, i.e.,
Higher than the bottom surface of sacrificial layer 110a.Here, the position for limiting 180 top surface of dielectric layer is for subsequent etching second side
When wall 170, terminate etching in this position.Etching stopping also makes to be located at 160 liang of side bottoms of source/drain region in this position
The top surface of remaining second side wall 170 is higher than the top surface of 160 the second side wall of bottom 170 of source/drain region, and the two is made to exist
The cross sectional shape of 160 bottom of source/drain region is in shallow u-shaped, and the side wall of this shallow u-shaped structure can more efficiently be isolated subsequent
Source/drain and substrate 100.
It should be noted that in actual process, it is more difficult to so that the top surface of dielectric layer 180 is placed exactly in preceding rheme
It sets.Therefore it can also be initially formed thicker dielectric layer 180, then dielectric layer 180 is performed etching again, control etching stop bit
It sets, so that the top surface of dielectric layer 180 is located at aforementioned location after etching.Specifically, in embodiments of the present invention, using first shape
At thicker dielectric layer 180, then returns again and carve dielectric layer 180, the top surface of dielectric layer 180 is made to be in above-mentioned position.
Referring to FIG. 5, removing the second side wall of part 170 of 160 two sides of source/drain region, isolation structure is formed.
The purpose for removing part second side wall 170 is only to retain the second side wall 170 of 160 bottom of source/drain region, with shape
At isolation structure.
The technique for removing part second side wall 170 includes dry etching and/or wet etching.Specifically, of the invention real
It applies in example, the technique that etching removes part second side wall 170 is wet etching.Solution used in wet etching includes: H3PO4、
H2O2, SC1, deionized water, HCl, HF, NH4One or more of F mixing.
In embodiments of the present invention, when removing part second side wall 170, the side of all nano wires 120 is exposed.I.e.
In embodiments of the present invention, the side of exposure all nano wire 120a and nano wire 120b.Make nano wire 120 and subsequent shape in this way
At source/drain be in contact, achieve the purpose that conducting.
As previously mentioned, dielectric layer 180 is that the second side wall of etched portions 170 provides etching stopping position.So specifically
, in embodiments of the present invention, remaining second side wall of 160 liang of side bottoms of source/drain region is side wall side wall 171, side wall side wall
171 top surface is concordant with the top surface of dielectric layer 180.I.e. the top surface of side wall side wall 171 is not higher than bottommost
The bottom surface of nano wire 120a and the bottom surface for being higher than bottommost sacrificial layer 110a.
It should be noted that due to actual etching technics it is difficult to ensure that the top surface and dielectric layer of side wall side wall 171
180 top surface is strictly concordant.So specifically, to be protected when implementing the nano-wire transistor of one embodiment of the invention
The highest point for demonstrate,proving isolation structure two sides is lower than the top surface of bottommost nano wire 120, the i.e. top surface of nano wire 120a.
Specifically, in embodiments of the present invention, the highest point of isolation structure two sides is not higher than the bottom table of bottommost nano wire 120
Face, the i.e. bottom surface of nano wire 120a.And the two sides of isolation structure be respectively sidewall isolation structure with bottom isolation junction
The non-contacting side of structure.
So far, in embodiments of the present invention, the remaining part of the second side wall 170 includes: side wall side wall 171 and bottom side wall
172, and bottom side wall 172 is connected between side wall side wall 171, and with side wall side wall 171.It will be evident that the second side wall 170,
The material of side wall side wall 171 and bottom side wall 172 be it is identical, material is as previously described.
So far, isolation structure is formd in 160 bottom of source/drain region, isolation structure includes sidewall isolation structure and bottom
Isolation structure.It will be evident that 100 surface of substrate and and sidewall isolation structure between bottom isolation structure covering sidewall isolation structure
It is connected.In embodiments of the present invention, sidewall isolation structure is side wall side wall 171, and bottom isolation structure is bottom side wall 172.
In embodiments of the present invention, side wall side wall 171 and bottom side wall 172 be located at subsequent source/drain and substrate 100 it
Between, realize the isolation to substrate 100 and source/drain, it is therefore prevented that the leakage of current between source/drain and substrate 100 improves
The performance of nano-wire transistor.
Referring to FIG. 6, forming source/drain 1310 in source/drain region 160.
Source/drain 1310 with nano wire 120 (channel region) for contacting.Therefore, in embodiments of the present invention, it is preferred that
The top surface of source/drain 1310 is higher than the top surface of top nano wire 120b, i.e. realization 1310 pairs of nanometers of source/drain
120 two sides of line are completely covered, and source/drain 1310 covers the surface of isolation structure simultaneously.
Formed source/drain 1310 processing step include: be initially formed covering isolation structure surface source drain material layer (not
Mark), then source drain material layer is doped, form source/drain 1310.In embodiments of the present invention, source drain material is formed
The technique of layer includes epitaxial growth technology.Epitaxial growth technology includes: outside chemical vapor deposition (CVD) epitaxy technique or molecular beam
Prolong (MBE) technique.Specifically, in embodiments of the present invention, the technique for forming source drain material layer is MBE technique.
The material of source drain material layer can be selected according to the different type of source/drain 1310.When source/drain 1310 is
When PMOS, the material of source drain material layer includes but is not limited to SiGe, Si etc., and the substance of doping includes but is not limited to boron (B), gallium
(Ga) etc.；When source/drain 1310 is NMOS, the material of source drain material layer includes but is not limited to SiC, Si etc., the substance of doping
Including but not limited to phosphorus (P), arsenic (As), rhodium (Rh) etc..
Technique to the doping of source drain material layer includes: doping in situ, diffusion, ion implanting or combinations thereof.Specifically,
In the embodiment of the present invention, the technique to the doping of source drain material layer is epi dopant in situ.
In embodiments of the present invention, source/drain 1310 is highly doped source/drain 1310.It is highly doped refer to doping from
Sub- concentration is greater than 1 × 1020atoms/cm3。
It should be noted that in embodiments of the present invention, removing part side wall 170 due to being previously formed dielectric layer 180
Later, it is formed before source/drain 1310, further includes: remove dielectric layer 180.
Removing dielectric layer 180 is directly to form source/drain 1310 on isolation structure surface in order to subsequent.Remove dielectric layer
180 technique includes: dry etching and/or wet etching.Specifically, in embodiments of the present invention, removing the work of dielectric layer 180
Skill is dry etching.
Referring to FIG. 7, forming the first dielectric layer 1320 at the top of source/drain 1310.
In embodiments of the present invention, after forming source/drain 1310, further includes: form the of covering source/drain 1310
One dielectric layer 1320.
First dielectric layer 1320 plays the role of dielectric isolation in nano-wire transistor, while also protecting source/drain
1310 are not destroyed in the subsequent process.
In embodiments of the present invention, the material of the first dielectric layer 1320 includes but is not limited to SiOx, SiOCH, SiN etc..
In concrete technology implementation, since the first dielectric layer 1320 is difficult to be only formed in the surface of source/drain 1310, because
This, also will form the first dielectric layer 1320 at the top of pseudo- grid 150.Pseudo- grid 150 are removed due to subsequent, so forming the
It will be exposed at the top of pseudo- grid 150 after one dielectric layer 1320.Specifically, in embodiments of the present invention, 150 top of exposure puppet grid
Method be to be initially formed the first dielectric layer 1320 for covering pseudo- grid 150 and source/drain 1310, then remove the first dielectric of part again
Layer 1320 exposes pseudo- 150 top of grid.
The technique for removing part of first dielectric layer 1320 includes: dry etching and/or wet etching, chemical-mechanical planarization
(CMP) etc..Specifically, in embodiments of the present invention, the first dielectric layer 1320 is planarized using CMP process, and then exposes
Pseudo- 150 top of grid.
Referring to FIG. 8, removing pseudo- grid 150 and sacrificial layer 110 to form groove (not shown), grid knot is formed in the trench
Structure.
The purpose for removing pseudo- grid 150 and sacrificial layer 110 is to form gate structure in the trench.Remove pseudo- grid 150 and sacrificial
The technique of domestic animal layer 110 includes: dry etching and/or wet etching.Specifically, in embodiments of the present invention, removing 150 He of pseudo- grid
The technique of sacrificial layer 110 includes dry etching.
In embodiments of the present invention, gate structure includes: gate dielectric layer 1330 and grid 1340.
The purpose of gate dielectric layer 1330 is for source/drain 1310, nano wire 120 to be isolated with grid 1340, avoids
Occurs excessive parasitic capacitance between source/drain 1310 and grid 1340.
In embodiments of the present invention, forming gate dielectric layer 1330 and the processing step of grid 1340 includes: to be initially formed covering
The inner dielectric layer (not shown) of groove, then form high dielectric material layer in internal dielectric layer surface and (do not mark, dielectric constant k
Between 15~50).Gate dielectric layer 1330 and grid 1340 are full of groove.In embodiments of the present invention, 1340 cover grid of grid
Dielectric layer 1330, gate dielectric layer 1330 cover nano wire 120.
It will be evident that in embodiments of the present invention, gate dielectric layer 1330 includes: inner dielectric layer and high dielectric material layer.
The material of inner dielectric layer includes but is not limited to: SiON, SiOxDeng herein and being not specifically limited.Specifically,
In embodiments of the present invention, the material of inner dielectric layer is SiO2。
The material of high dielectric material layer includes but is not limited to: HfO2、ZrO2Deng.Specifically, in embodiments of the present invention, it is high
The material of dielectric materials layer is HfO2。
Grid 1340 is metal gates.The material of grid 1340 include but is not limited to TiN, TiAlC, TiAl, TaN, W, Ti,
One layer or multilayer laminated material of the compositions such as Al.Specifically, in embodiments of the present invention, the material of grid 1340 be TiN and
The laminated material of TiAl composition.
The technique for forming gate dielectric layer 1330 and grid 1340 includes: ALD technique, CVD technique, physical gas-phase deposition
(PVD), chemical vapor deposition (CVD) epitaxy technique, molecular beam epitaxy (MBE) technique etc., herein and are not particularly limited.Tool
Body, in embodiments of the present invention, the formation process of gate dielectric layer 1330 and grid 1340 is ALD technique.
It in embodiments of the present invention, further include removing at the top of covering top nano wire 120b before removing sacrificial layer 110
The protection structure 130 for 120 side wall of sacrificial layer 110 and nano wire that surface and covering stack.
Referring to FIG. 9, forming metal wire 1360 at the top of grid 1340, covering gate structure and the first dielectric layer are formed
1320 the second dielectric layer 1350.
The purpose for forming the second dielectric layer 1350 is to protect grid 1340 and metal wire 1360.
Metal wire 1360 is contacted with gate structure, realizes the connection with grid 1340.And metal wire 1360 is situated between through second
Electric layer 1350.Since metal wire 1360 will be with the contact of semiconductor device on top, so the top surface of metal wire 1360 is sudden and violent
Expose.
It will be evident that first medium layer 1320 and the second dielectric layer 1350 play the role of dielectric protection.Therefore, first is situated between
Matter layer 1320 can be identical with the material of the second dielectric layer 1350, can not also be identical.Specifically, in embodiments of the present invention,
First medium layer 1320 is identical as the material of the second dielectric layer 1350.
In conclusion first embodiment according to the present invention, is formed with side between 1310 bottom of source/drain and substrate 100
Wall isolation structure and bottom isolation structure.With in the prior art without the nano wire of sidewall isolation structure and bottom isolation structure crystalline substance
Body pipe is compared, and this isolation structure is effectively isolated substrate 100 and source/drain 1310, eliminate substrate 100 and source/
The leakage of electric current, improves the performance of nano-wire transistor between drain electrode 1310.
Correspondingly, with continued reference to FIG. 9, the embodiments of the present invention also provide a kind of nano-wire transistors, comprising: substrate
100, nano wire 120, isolation structure, source/drain 1310 and gate structure.
Substrate 100 is the basis of subsequent gate structure and isolation structure.The material of substrate 100 includes Si, SiGe etc., at this
In and be not particularly limited.
Channel region of the nano wire 120 as semiconductor devices.The material of nano wire 120 includes: Si, SiGe, SiC etc.,
Here it and is not particularly limited.Nano wire 120 is not contacted with substrate 100.The number of nano wire 120 is one or more, herein
And it is not particularly limited.When nano wire 120 is multiple, multiple 120 longitudinally spaced distributions of nano wire are inside gate structure, such as
In Fig. 9, direction indicated by arrow is longitudinal.Specifically, in embodiments of the present invention, the number of nano wire 120 is two, from
Under to being above followed successively by 120a, 120b.
Isolation structure is located at 100 surface of substrate, for isolation liner bottom 100 and source/drain 1310.Isolation structure includes side wall
Isolation structure and bottom isolation structure, wherein sidewall isolation structure is located at the two sides of bottom isolation structure, bottom isolation structure position
It is in contact between sidewall isolation structure, and with sidewall isolation structure.Specifically, in embodiments of the present invention, side wall isolation junction
Structure is side wall side wall 171, and bottom isolation structure is bottom side wall 172.The material phase of sidewall isolation structure and bottom isolation structure
It together, is SiO2, one of SiN, SiON, SiOCN or a variety of.
Isolation structure two sides be respectively sidewall isolation structure with non-contacting two sides of bottom isolation structure.Isolation
The highest point of structure two sides is lower than the top surface of bottommost nano wire 120.Specifically, in embodiments of the present invention, isolation
The highest point of structure two sides is lower than the bottom surface of bottommost nano wire 120, that is, is lower than the bottom surface of nano wire 120a.
Source/drain 1310 is located at the two sides of gate structure, and source/drain 1310 is in contact with the two sides of nano wire 120.
In embodiments of the present invention, source/drain 1310 covers isolation structure.When source/drain 1310 is PMOS, source/drain 1310
Material includes but is not limited to SiGe, Si etc., and the substance of doping includes but is not limited to boron (B), gallium (Ga) etc.；When source/drain 1310
When for NMOS, the material of source/drain includes but is not limited to SiC, Si etc., and the substance of doping includes but is not limited to phosphorus (P), arsenic
(As), rhodium (Rh) etc..
Gate structure is located at 100 top of substrate, and gate structure is between source/drain 1310.Gate structure includes grid
Dielectric layer 1330 and grid 1340.
The purpose of gate dielectric layer 1330 is for source/drain 1310, nano wire 120 to be isolated with grid 1340, avoids
Occurs excessive parasitic capacitance between source/drain 1310 and grid 1340.In embodiments of the present invention, gate dielectric layer 1330 wraps
It includes: inner dielectric layer (not shown) and high dielectric material layer (not shown).
The material of inner dielectric layer includes: SiON, SiOxDeng herein and being not specifically limited.Specifically, in the present invention
In embodiment, the material of inner dielectric layer is SiO2。
The material of high dielectric material layer includes but is not limited to: HfO2、ZrO2Deng.Specifically, in embodiments of the present invention, it is high
The material of dielectric materials layer is HfO2。
Grid 1340 is metal gates.The material of grid 1340 include but is not limited to TiN, TiAlC, TiAl, TaN, W, Ti,
One layer or multilayer laminated material of the compositions such as Al.Specifically, in embodiments of the present invention, the material of grid 1340 be TiN and
The laminated material of TiAl composition.
In embodiments of the present invention, nano-wire transistor further include: the first dielectric layer 1320, the second dielectric layer 1350 and gold
Belong to line 1360.
The top of first dielectric layer 1320 covering source/drain 1310.First dielectric layer 1320 rises in nano-wire transistor
To the effect of dielectric isolation, while source/drain 1310 also being protected not to be destroyed in the subsequent process.In the embodiment of the present invention
In, the material of the first dielectric layer 1320 includes but is not limited to SiOx, SiOCH, SiN etc..
Second dielectric layer 1350 covers gate structure and the first dielectric layer 1320.The purpose of second dielectric layer 1350 is to protect
Grille pole 1340 and metal wire 1360.
It will be evident that first medium layer 1320 and the second dielectric layer 1350 play the role of dielectric protection.Therefore, first is situated between
Matter layer 1320 can be identical with the material of the second dielectric layer 1350, can not also be identical.Specifically, in embodiments of the present invention,
First medium layer 1320 is identical as the material of the second dielectric layer 1350.
Metal wire 1360 is contacted with gate structure, realizes the connection with grid 1340.And metal wire 1360 is situated between through second
Electric layer 1350.Since metal wire 1360 will be with the contact of semiconductor device on top, so the top surface of metal wire 1360 is sudden and violent
Expose.
In embodiments of the present invention, nano-wire transistor further include: protection structure 130 and the first side wall 140.
Protect the sacrificial layer 110 and nanometer that structure 130 covers the top surface of top nano wire 120b and covering stacks
The side wall of line 120.Herein, the effect of protection structure 130 is the sacrificial layer 110 and nanometer in order to avoid subsequent technique to stacking
Line 120 damages.In other embodiments of the invention, protection structure 130 can be used as the gate medium of part MOS transistor
Layer.The material for protecting structure 130 includes oxide, nitride etc..Specifically, in embodiments of the present invention, protection structure 130
Material is SiO2。
First side wall 140 covers pseudo- 150 two sidewalls of grid.The effect of first side wall 140 is to protect pseudo- grid 150 not subsequent
Processing damage.The material of first side wall 140 is oxide, nitride etc., herein and is not particularly limited.
In conclusion containing between source/drain and substrate in the nano-wire transistor that first embodiment of the invention provides
Sidewall isolation structure and bottom isolation structure, realize the electric isolation to source/drain and substrate, eliminate electric current between the two
Leakage, improve the performance of nano-wire transistor.
Second embodiment.
Second embodiment and first embodiment the difference is that, second embodiment is using bottom barrier instead of the
Bottom side wall in one embodiment, and then realize being isolated between source/drain and substrate.
Referring to FIG. 10, Figure 10 is the cross-section structure for further executing etching technics on the basis of etching removes dielectric layer
Schematic diagram (since in a second embodiment, the processing step before etch media layer is identical with the first embodiment, specifically refers to
The associated description of first embodiment, this is no longer going to repeat them).
In embodiments of the present invention, further includes: after removal dielectric layer, remove bottom side wall, exposure substrate 200.
The purpose of removal bottom side wall is can be to source/drain in 200 surface of the substrate formation of 260 bottom of source/drain region
The bottom isolation structure being isolated with substrate.The technique for removing bottom side wall is reactive ion etching (Reactive Ion
Etch, RIE) technique.
Figure 11 is please referred to, forms bottom isolation structure between the side wall side wall 271 of 260 bottom of source/drain region.
In an embodiment of the present invention, after removing dielectric layer, further includes: remove the bottom side of 260 bottom of source/drain region
Wall (not shown)；Then 200 surface of substrate between side wall side wall 271 forms bottom barrier 272.
The effect of bottom barrier 272 be it is subsequent source/drain is isolated with substrate 200, reduce source/drain and lining
The leakage of electric current between bottom 200.
Bottom side wall (as in the first embodiment) and bottom barrier 272 can carry out source/drain and substrate 200
Isolation.In embodiments of the present invention, bottom barrier 272 is used as bottom isolation structure, and side wall side wall 271 is isolated as side wall
Structure, the two collectively form isolation structure.The positional relationship and top surface of its sidewall isolation structure and bottom isolation structure
Or the highest point of isolation structure two sides is consistent with first embodiment, details are not described herein.
Herein, the material of side wall side wall 271 is as the material of side wall side wall in first embodiment, as previously described.And
The material of bottom barrier 272 is one of Si, SiGe, Ge, GaAs, SiC, SiGeC or a variety of.
Formed bottom barrier 272 technique include but is not limited to: atom layer deposition process, chemical vapor deposition process,
Chemical vapor deposition epitaxy technique, molecular beam epitaxial process etc..Specifically, in embodiments of the present invention, forming bottom isolation junction
The technique of structure is molecular beam epitaxial process.The bottom barrier 272 grown using epitaxy technique, can make subsequent in bottom isolation junction
The process that source/drain is formed on structure is more easier.
In embodiments of the present invention, the type of bottom isolation structure includes: diffusion barrier layer or conducting barrier layer；It can also be with
It is the laminated construction of diffusion barrier layer and conducting barrier layer, herein and is not particularly limited.
Herein, it should be pointed out that the title on diffusion barrier layer and conducting barrier layer functions consistent.Diffusion
Barrier layer can prevent the diffusion of particle between source/drain and substrate 200；Conducting barrier layer can prevent source/drain and substrate
The conducting of parasitic capacitance between 200.
Specifically, in embodiments of the present invention, when bottom barrier 272 is diffusion barrier layer, bottom barrier 272 can
Not to be doped or shallowly be adulterated.When bottom barrier 272 is not doped, bottom barrier 272 can be isolated source/drain with
Substrate 200 cuts off the leakage path of electric current, improves the performance of nano-wire transistor.When bottom barrier 272 is shallowly adulterated,
The type that it is adulterated is identical as the ionic type of subsequent source drain doping.Preferably, when bottom barrier 272 is to be doped
Boron (B), gallium (Ga) P-type semiconductor when, the material of bottom isolation structure is SiC, SiGeC etc.；When bottom barrier 272 is quilt
When being doped with the N-type semiconductor of phosphorus (P), arsenic (As), rhodium (Rh), the material of bottom barrier 272 is SiC etc., herein not
Make concrete restriction.
In embodiments of the present invention, when bottom barrier 272 is shallowly adulterated, the ion concentration of doping is less than or equal to 1 ×
1017atoms/cm3.(ion concentration is greater than 1 × 10 with medium-doped17atoms/cm3, less than 1 × 1020atoms/cm3) or it is high
(ion concentration is more than or equal to 1 × 10 for doping20atoms/cm3) bottom barrier 272 compare, the bottom barrier shallowly adulterated
272 can more reduce the leakage of electric current, and performance is more excellent.
In embodiments of the present invention, when bottom barrier 272 is conducting barrier layer, bottom barrier 272 is mixed by medium
Miscellaneous, the type of doping is opposite with the ionic type for being subsequently formed source drain doping.Preferably, when bottom barrier 272 is quilt
When being doped with the P-type semiconductor of boron (B), gallium (Ga), the material of bottom barrier 272 is Si, SiGe, SiGeC etc.；When bottom hinders
Barrier 272 is when being doped the N-type semiconductor of phosphorus (P), arsenic (As), rhodium (Rh), and the material of bottom barrier 272 is Si, SiC
Deng.Moreover, the ion concentration of 272 medium-doped of bottom barrier is 1 × 1017atoms/cm3~1 × 1020atoms/cm3It
Between.
In embodiments of the present invention, being doped gas source to bottom barrier 272 includes but is not limited to: silicon source SiH2Cl2、
SiH4、Si2H6；Ge source GeH4；Adulterate gas source: B2H6(boron), AsH3(As)、CH3CH3、CH3SiH3(carbon content 0.1%~5%),
PH3(phosphorus) etc..
Herein, it should be noted that the top surface of bottom barrier 272 is not higher than the bottom of bottommost nano wire 220a
Portion surface.If the top surface of bottom barrier 272 is higher than the bottom surface of bottommost nano wire 220a, it is subsequently formed
Dead resistance between source/drain and substrate 200 increases, and influences the performance of nano-wire transistor.
As previously mentioned, bottom barrier 272 can also be diffusion barrier layer and the laminated construction on barrier layer be connected.At this point,
Laminated construction top layer can be diffusion barrier layer with what subsequent source/drain was in contact, be also possible to that barrier layer is connected, herein not
Make concrete restriction, the selection of specific material and the type being doped with it is consistent above, this will not be repeated here.
Figure 12 is please referred to, forms source/drain 2310 in source/drain region 260.
Form the position of the effect of source/drain 2310, process, step, the concentration of doping and top surface, with
First embodiment is identical, and therefore not to repeat here.
It should be noted that the material of source/drain 2310 will be selected according to the material category of bottom isolation structure, such as
It is preceding described.
Figure 13 is please referred to, forms the first dielectric layer 2320 at the top of source/drain 2310.
The selection for forming the effect of the first dielectric layer 2320, technique, step and material is identical with the first embodiment,
This is not repeated.
Figure 14 is please referred to, removes pseudo- grid 250 and sacrificial layer 210 to form groove (not shown), grid is formed in the trench and is situated between
Matter layer 2330 and grid 2340.
Remove pseudo- grid 250 and sacrificial layer 210, and formed the effect of gate dielectric layer 2330 and grid 2340, technique, step,
Positional relationship between material selection and structure is identical with the first embodiment, and therefore not to repeat here.
Figure 15 is please referred to, metal wire 2360 is formed on 2340 surface of grid, forms covering the second sub- gate structure and first
Second dielectric layer 2350 of dielectric layer 2320.
The selection of the effect of the second dielectric layer 2350 and metal wire 2360, technique, step and material is formed with
One embodiment is identical, and therefore not to repeat here.
In conclusion according to a second embodiment of the present invention, existing isolation structure between source/drain 2310 and substrate 200
Including sidewall isolation structure and bottom isolation structure.The buffer action of the two reduces between source/drain 2310 and substrate 200
The leakage of electric current improves the performance of nano-wire transistor.
Correspondingly, please continue to refer to Figure 15, the embodiments of the present invention also provide a kind of nano-wire transistor, the present invention the
Two embodiments provide nano-wire transistor and first embodiment nano-wire transistor the difference is that: first embodiment
Bottom side wall is replaced by the bottom barrier of second embodiment, and the top surface of bottom barrier and bottom side coping
Apparent height is not exactly the same.The positional relationship of other structures is consistent with the nano-wire transistor of first embodiment, herein not
It repeats.
The effect of bottom barrier 272 be it is subsequent source/drain is isolated with substrate 200, reduce source/drain and lining
The leakage of electric current between bottom 200.In embodiments of the present invention, bottom barrier 272 is bottom isolation structure, bottom isolation structure
Type include: diffusion barrier layer or conducting barrier layer；It is also possible to diffusion barrier layer and the laminated construction on barrier layer is connected,
Here it and is not particularly limited.
In embodiments of the present invention, the top surface of bottom barrier 272 is not higher than the bottom of bottommost nano wire 220a
Surface.
In conclusion in the nano-wire transistor that second embodiment provides, sidewall isolation structure and bottom isolation structure
Substrate 200 and source/drain 2310 are effectively isolated, less electric leakage improves the performance of nano-wire transistor.
3rd embodiment.
Compared with second embodiment, 3rd embodiment is opened the difference is that being formed in every layer of sacrificial layer two sides of stacking
Mouthful, and the second side wall is inserted in opening, form internal side wall, realize being isolated to source/drain and grid.
Figure 16 is please referred to, Figure 16 is sacrificial further to execute every layer etching and stacking on the basis of forming source/drain region 360
Domestic animal layer is to form the schematic diagram of the section structure of the technique of opening (due to the processing step and first embodiment before 3rd embodiment
It is identical, the associated description of first embodiment is specifically referred to, this is no longer going to repeat them).
In embodiments of the present invention, it after forming source/drain region 360, is formed before the second side wall, further includes: removing unit
Divide sacrificial layer 310, to form opening 361 in the two sides of every layer of sacrificial layer.
Formed opening 361 purpose be it is subsequent opening 361 inside be packed into the second side wall.
In embodiments of the present invention, be open 361 depth between 2nm~20nm, be not specifically limited here.In this hair
In bright one embodiment, be open 361 depth be 2nm.In another embodiment of the present invention, 361 depth of being open is
20nm。
The technique for forming opening 361 includes dry etching and/or wet etching.Specifically, in embodiments of the present invention, shape
Technique at opening 361 includes wet etching, and is lateral wet-etching technology.Transverse direction herein refers to arrow institute in Figure 16
The direction of finger.
The solution of lateral wet etching includes: NH4OH、NaOH、KOH、H2O2、CH3COOH, deionized water, HCl, HF, NH4F
One or more of mixing.
Figure 17 is please referred to, the second side wall 370 is formed, the second side wall 370 filling is open inside 361.
In embodiments of the present invention, formation the second side wall 370 covering 360 two sides of source/drain region 350 side wall of pseudo- grid,
300 surface of 320 side wall of nano wire, 310 side wall of sacrificial layer and 360 base substrate of source/drain region, and guarantee the second side wall simultaneously
370 are packed into inside all openings 361.
The purpose that second side wall 370 is packed into inside all openings 361 is the internal side wall of formation in opening 361, with
Realize subsequent being isolated to source/drain and grid.
In embodiments of the present invention, the thickness of the second side wall 370 is between 2nm~20nm, as in the first embodiment.The
The thickness of two side walls 370 can be identical as the depth of opening 361, can also be different from the depth of opening 361.But opening should be met
The condition of the second side wall 370 is packed into inside 361.Preferably, in embodiments of the present invention, the thickness of the second side wall 370 is bigger
In 361 depth that are open.
Herein, formed the selection of the effect of the second side wall 370, process and material with second embodiment one
It causes, details are not described herein.
Figure 18 is please referred to, the dielectric layer 380 on covering 360 the second side wall of bottom of source/drain region, 370 surface is formed.
Effect, technique, the material selection for forming dielectric layer 380 are consistent with first embodiment, and therefore not to repeat here.
Figure 19 is please referred to, part second side wall 370 is removed, forms isolation structure.
The effect of removing part second side wall 370, technique, step are consistent with first embodiment, and therefore not to repeat here.
The height of the positional relationship of isolation structure and its top surface, please refers to first embodiment.
In embodiments of the present invention, when removing part second side wall 370, to retain internal side wall 373.Internal side wall 373
Effect be to increase the distance between subsequent gate and source/drain, reduce excessive parasitic electric between grid and source/drain
Hold.
It will be evident that in embodiments of the present invention, the material of the second side wall 370 and internal side wall 373 be it is identical, such as preceding institute
It states.
Figure 20 is please referred to, dielectric layer 380 and bottom side wall are removed.
It removes dielectric layer 380 and the effect of bottom side wall, technique, step is consistent with second embodiment, therefore not to repeat here.
Herein, it should be noted that after removing dielectric layer 380, directly can form source/drain on the side wall of bottom
(such as first embodiment) can continue to remove bottom side wall to form bottom isolation structure (such as second embodiment), here not
Do concrete restriction.In embodiments of the present invention, after removing dielectric layer 380, continue to remove bottom side wall to form bottom isolation junction
Structure, exposure substrate 300.
Figure 21 is please referred to, forms bottom isolation structure between the sidewall isolation structure of 360 bottom of source/drain region.
Form effect, type, technique, step, material selection, the position of top surface and the doping of bottom isolation structure
Type it is consistent with second embodiment, therefore not to repeat here.
Herein, it should be noted that side wall side wall 371 is used as sidewall isolation structure, and bottom barrier 372 is used as bottom
Isolation structure.
Figure 22 is please referred to, forms source/drain 3310 in source/drain region 360.
Effect, process, the material selection for forming source/drain 3310 are consistent with second embodiment, do not go to live in the household of one's in-laws on getting married herein
It states.
Figure 23 is please referred to, forms the first dielectric layer 3320 at the top of source/drain 3310.
The selection for forming the effect of the first dielectric layer 3320, technique, step and material is consistent with second embodiment,
This is not repeated.
Figure 24 is please referred to, pseudo- grid 350 and sacrificial layer 310 is removed to form groove, forms gate dielectric layer 3330 in the trench
With grid 3340.
Remove pseudo- grid 350 and sacrificial layer 310, and formed the effect of gate dielectric layer 3330 and grid 3340, technique, step,
Positional relationship between material selection and structure is identical as second embodiment, and therefore not to repeat here.
Figure 25 is please referred to, metal wire 3360 is formed on 3340 surface of grid, forms covering the second sub- gate structure and first
Second dielectric layer 3350 of dielectric layer 3320.
The selection of the effect of the second dielectric layer 3350 and metal wire 3360, technique, step and material is formed with
Two embodiments are identical, and therefore not to repeat here.
In conclusion according to a third embodiment of the present invention, existing isolation structure between source/drain 3310 and substrate 300
It include: the sidewall isolation structure and bottom isolation structure of 360 bottom of source/drain region.The buffer action of the two, reduces source/drain
The leakage of electric current between pole 3310 and substrate 300.Meanwhile there are internal side walls between grid 3340 and source/drain 3310
373, the distance between grid 3340 and source/drain 3310 are increased, is solved parasitic between grid 3340 and source/drain 3310
The excessive problem of capacitor, improves the performance of nano-wire transistor.
Correspondingly, a kind of nano-wire transistor is additionally provided please continue to refer to Figure 25, in the embodiment of the present invention, the present invention
3rd embodiment provide nano-wire transistor and second embodiment nano-wire transistor the difference is that: in gate structure
There are internal side wall between source/drain, the distance between gate structure and source/drain are increased.It closes the position of other structures
System is consistent with the nano-wire transistor of second embodiment, and this will not be repeated here.
In embodiments of the present invention, further includes: internal side wall 373.
Internal side wall 373 is between source/drain 3310 and gate structure.Internal side wall 373 increase gate structure with
The distance between source/drain 3310 reduces the excessive parasitic capacitance occurred between the two, improves nano-wire transistor
Performance.
In conclusion in the nano-wire transistor that 3rd embodiment provides, sidewall isolation structure and bottom isolation structure
Substrate 300 and source/drain 3310 are effectively isolated, less electric leakage；Internal side wall 373 increases source/drain 3310 and grid
Distance between the structure of pole, reduces parasitic capacitance excessive between source/drain 3310 and gate structure.
So far, the present invention is described in detail.In order to avoid covering design of the invention, it is public that this field institute is not described
The some details known.Those skilled in the art as described above, completely it can be appreciated how implementing technology disclosed herein
Scheme.
Although some specific embodiments of the invention are described in detail by example, the skill of this field
Art personnel it should be understood that above example merely to being illustrated, the range being not intended to be limiting of the invention.The skill of this field
Art personnel are it should be understood that can without departing from the scope and spirit of the present invention modify to above embodiments.This hair
Bright range is defined by the following claims.
Claims (37)
1. a kind of nano-wire transistor characterized by comprising
The gate structure being set on substrate；
Source/drain, the source/drain are located at the two sides of the gate structure；
Nano wire, the nano wire are set to inside the gate structure, the two sides of the nano wire with the source/drain
Contact；With
Isolation structure, the isolation structure are formed between the substrate and the source/drain, the substrate and described is isolated
Source/drain.
2. nano-wire transistor according to claim 1, which is characterized in that the nano wire number is one or more, when
When the nano wire is multiple, the multiple nano wire longitudinally spaced distributions are inside the gate structure.
3. nano-wire transistor according to claim 1, which is characterized in that the isolation structure covers the source/drain
The substrate of lower section so that the source/drain not with the substrate contact.
4. nano-wire transistor according to claim 3, which is characterized in that the highest point of the isolation structure two sides is low
The top surface of the nano wire described in bottommost.
5. nano-wire transistor according to claim 4, which is characterized in that the highest point of the isolation structure two sides is not
Higher than the bottom surface of nano wire described in bottommost.
6. nano-wire transistor according to claim 4, which is characterized in that the isolation structure includes: side wall isolation junction
Structure and bottom isolation structure, wherein the sidewall isolation structure is located at the two sides of the isolation structure, the bottom isolation structure
It is in contact between the sidewall isolation structure, and with the sidewall isolation structure.
7. nano-wire transistor according to claim 6, which is characterized in that the two sides of the isolation structure are respectively institute
It is stating sidewall isolation structure with the non-contacting side of bottom isolation structure.
8. nano-wire transistor according to claim 6, which is characterized in that the sidewall isolation structure is side wall side wall,
The bottom isolation structure is bottom side wall or bottom barrier.
9. nano-wire transistor according to claim 8, which is characterized in that the bottom barrier includes diffusion barrier layer
The conducting barrier layer and/or.
10. nano-wire transistor according to claim 8, which is characterized in that when the sidewall isolation structure is the side
Wall side wall, and when the bottom isolation structure is the bottom side wall, the sidewall isolation structure and the bottom isolation structure
Material it is identical, be SiO2, one of SiN, SiON, SiOCN or a variety of.
11. nano-wire transistor according to claim 8, which is characterized in that when the sidewall isolation structure is the side
Wall side wall, and when the bottom isolation structure is the bottom barrier, the material of the sidewall isolation structure is SiO2、SiN、
One of SiON, SiOCN or a variety of, the material of the bottom isolation structure are in Si, SiGe, Ge, GaAs, SiC, SiGeC
It is one or more.
12. nano-wire transistor according to claim 1, which is characterized in that further include: internal side wall, the private side
Wall is between the source/drain and the gate structure being in contact with the bottom surface of the nano wire.
13. nano-wire transistor according to claim 1, which is characterized in that the gate structure includes: grid and covering
The gate dielectric layer of the gate surface.
14. nano-wire transistor according to claim 1, which is characterized in that further include: protection structure, the protection knot
Structure covers the top surface of the nano wire of top.
15. nano-wire transistor according to claim 14, which is characterized in that further include:
First side wall, first side wall cover the two sidewalls of the gate structure of the protection superstructure；
First dielectric layer, first dielectric layer cover the source/drain；
Second dielectric layer, second dielectric layer cover the gate structure, first dielectric layer and the first side wall table
Face；With
Metal wire, the metal wire are contacted through second dielectric layer and with the gate structure.
16. a kind of preparation method of nano-wire transistor characterized by comprising
The sacrificial layer and nano wire being stacked with is formed on the substrate；
Pseudo- grid are formed, the puppet grid are located above the sacrificial layer and the nano wire of the stacking；
The sacrificial layer and the nano wire between the adjacent pseudo- grid are removed, to form source/drain region；
Isolation structure is formed, the isolation structure is located at the substrate surface of the source/drain region bottom, described in isolation
Source/drain region and the substrate；With
Form source/drain in the source/drain region, the source/drain is located above the isolation structure, and with adjacent institute
State the side contact of nano wire.
17. the preparation method of nano-wire transistor according to claim 16, which is characterized in that the sacrifice of bottommost
Layer contacted with the surface of the substrate, the nano wire of bottommost not with the substrate contact.
18. the preparation method of nano-wire transistor according to claim 16, which is characterized in that the nano wire of stacking
Number be one or more.
19. the preparation method of nano-wire transistor according to claim 16, which is characterized in that the isolation structure covering
The substrate below the source/drain region.
20. the preparation method of nano-wire transistor according to claim 19, which is characterized in that
Formed the isolation structure include:
It forms sidewall isolation structure and bottom isolation structure, the sidewall isolation structure is located at the two of the bottom isolation structure
Side, bottom isolation structure are in contact between the sidewall isolation structure, and with the sidewall isolation structure.
21. the preparation method of nano-wire transistor according to claim 20, which is characterized in that
The step of forming the sidewall isolation structure and the bottom isolation structure include:
The second side wall is formed, second side wall covers the pseudo- grid side of the source/drain region two sides, the nanometer line side
Substrate surface described in face, the sacrificial layer side and the source/drain region bottom；
The dielectric layer for covering the second side wall surface described in the source/drain region bottom is formed, the top surface of the dielectric layer is low
In the top surface of the nano wire of bottommost, and it is higher than the bottom surface with the sacrificial layer of bottommost；With
Part second side wall for removing the source/drain region two sides, makes the source/drain region two sides remaining described second
The top surface of side wall is concordant with the top surface of the dielectric layer, to form the side wall side wall and the bottom side wall,
In, remaining second side wall in source/drain region two sides is the side wall side wall, and the side wall side wall is the side wall
Isolation structure, second side wall positioned at the dielectric layer bottom is the bottom side wall, and the bottom side wall is described
Bottom isolation structure.
22. the preparation method of nano-wire transistor according to claim 21, which is characterized in that the isolation structure two sides
Top surface of the highest point in face lower than nano wire described in bottommost.
23. the preparation method of nano-wire transistor according to claim 21, which is characterized in that the isolation structure two sides
Bottom surface of the highest point in face not higher than nano wire described in bottommost.
24. the preparation method of nano-wire transistor according to claim 23, which is characterized in that the two of the isolation structure
Side be respectively the sidewall isolation structure with the non-contacting side of bottom isolation structure.
25. the preparation method of nano-wire transistor according to claim 21, which is characterized in that the sidewall isolation structure
For side wall side wall, the bottom isolation structure is bottom side wall or bottom barrier.
26. the preparation method of nano-wire transistor according to claim 25, which is characterized in that when the side wall isolation junction
Structure is the side wall side wall, and when the bottom isolation structure is the bottom side wall, the sidewall isolation structure and the bottom
The material of portion's isolation structure is identical, is SiO2, one of SiN, SiC, SiOCN or a variety of.
27. the preparation method of nano-wire transistor according to claim 25, which is characterized in that when the side wall isolation junction
Structure be the side wall side wall, and the bottom isolation structure be the bottom barrier when, the material of the sidewall isolation structure
For SiO2, one of SiN, SiON, SiOCN or a variety of, the material of the bottom isolation structure is Si, SiGe, Ge, GaAs,
One of SiC, SiGeC or a variety of.
28. the preparation method of nano-wire transistor according to claim 21, which is characterized in that
The step of forming the sidewall isolation structure and the bottom isolation structure further include:
Remove the dielectric layer；
Remove the bottom side wall, the exposure substrate；With
The substrate surface between the side wall side wall forms the bottom barrier, and the bottom barrier is the bottom
Portion's isolation structure.
29. the preparation method of nano-wire transistor according to claim 28, which is characterized in that the bottom barrier packet
Include diffusion barrier layer and/or conducting barrier layer.
30. the preparation method of nano-wire transistor according to claim 29, which is characterized in that the diffusion barrier layer with
The ionic type of the source drain doping on the contrary, the ion adulterated in the diffusion barrier layer be boron (B), one in gallium (Ga)
Kind is a variety of.
31. the preparation method of nano-wire transistor according to claim 29, which is characterized in that the conducting barrier layer with
The ionic type of the source drain doping is identical, doped with: one of boron (B), gallium (Ga) or a variety of or arsenic (As), rhodium
One of (Rh) or it is a variety of.
32. the preparation method of nano-wire transistor according to claim 21, which is characterized in that further include:
Before forming second side wall, the part sacrificial layer is removed, is opened with being formed in the two sides of every layer of sacrificial layer
Mouthful；With
When forming second side wall, each opening is filled to form internal side wall.
33. the preparation method of nano-wire transistor according to claim 32, which is characterized in that the depth model of the opening
It encloses for 2nm~20nm.
34. the preparation method of nano-wire transistor according to claim 16, which is characterized in that
After forming the source/drain, further includes:
Form the first dielectric layer for covering the source/drain；
The pseudo- grid and the sacrificial layer are removed, to form groove；With
Gate structure is formed in the groove.
35. the preparation method of nano-wire transistor according to claim 34, which is characterized in that
After forming the gate structure, further includes:
Form the second dielectric layer for covering the gate structure and first dielectric layer；With
The metal wire for running through second dielectric layer is formed, the metal wire is contacted with the gate structure.
36. the preparation method of nano-wire transistor according to claim 16, which is characterized in that
It is formed before the pseudo- grid, further includes:
Form protection structure, the top surface of the sacrificial layer and the nano wire that the protection structure covering stacks.
37. the preparation method of nano-wire transistor according to claim 16, which is characterized in that
After forming the pseudo- grid, before forming the isolation structure, further includes: form the covering pseudo- grid two sides
First side wall.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111710717A (en) * | 2020-05-12 | 2020-09-25 | 中国科学院微电子研究所 | Semiconductor device, manufacturing method thereof and electronic equipment |
| WO2020236694A1 (en) * | 2019-05-20 | 2020-11-26 | Applied Materials, Inc. | Bottom isolation by selective top deposition in gaa transistors |
| EP3944330A1 (en) * | 2020-07-21 | 2022-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Latch-up prevention |
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| WO2020236694A1 (en) * | 2019-05-20 | 2020-11-26 | Applied Materials, Inc. | Bottom isolation by selective top deposition in gaa transistors |
| US11189710B2 (en) | 2019-05-20 | 2021-11-30 | Applied Materials, Inc. | Method of forming a bottom isolation dielectric by directional sputtering of a capping layer over a pair of stacks |
| CN111710717A (en) * | 2020-05-12 | 2020-09-25 | 中国科学院微电子研究所 | Semiconductor device, manufacturing method thereof and electronic equipment |
| CN111710717B (en) * | 2020-05-12 | 2024-02-13 | 中国科学院微电子研究所 | Semiconductor device, manufacturing method thereof and electronic equipment |
| EP3944330A1 (en) * | 2020-07-21 | 2022-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Latch-up prevention |
| EP4109548A1 (en) * | 2021-06-24 | 2022-12-28 | INTEL Corporation | Nanoribbon sub-fin isolation by backside si substrate removal etch selective to source and drain epitaxy |
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| CN109755290B (en) | 2022-07-19 |
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