CN106611792A - Semiconductor device and manufacturing method therefor - Google Patents

Semiconductor device and manufacturing method therefor Download PDF

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Publication number
CN106611792A
CN106611792A CN201610146132.4A CN201610146132A CN106611792A CN 106611792 A CN106611792 A CN 106611792A CN 201610146132 A CN201610146132 A CN 201610146132A CN 106611792 A CN106611792 A CN 106611792A
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nano wire
gate electrode
semiconductor devices
area
drain
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CN106611792B (en
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金东权
徐康
徐康一
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L2029/7858—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Manufacturing & Machinery (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor device is provided as follows. A fin-type pattern includes first and second oxide regions in an upper portion of the fin-type pattern. The fin-type pattern is extended in a first direction. A first nanowire is extended in the first direction and spaced apart from the fin-type pattern. A gate electrode surrounds a periphery of the first nanowire, extending in a second direction intersecting the first direction. The gate electrode is disposed on a region of the fin-type pattern. The region is positioned between the first and the second oxide regions. A first source/drain is disposed on the first oxide region and connected with an end portion of the first nanowire.

Description

Semiconductor devices and its manufacture method
Technical field
Present inventive concept is related to semiconductor devices and its manufacture method.
Background technology
Multiple-gate transistor has been suggested to integrated multiple transistors without reducing its performance.Multiple-grid crystal Pipe includes three dimension channel.The current handling capability of multiple-gate transistor can increase long without increasing its grid Degree.Furthermore, it is possible to suppress short-channel effect (SCE).
The content of the invention
According to the exemplary implementations of present inventive concept, there is provided a kind of semiconductor devices is as follows.Fin figure Case is included in the first and second oxide regions in the top of fin pattern.Fin pattern is in a first direction Extend.First nano wire extends in a first direction and opens with fin pattern spacing.Gate electrode surrounds first The periphery of nano wire simultaneously upwardly extends in the second party for intersecting first direction.Gate electrode is arranged on fin pattern A region on.The region is located between the first oxide region and the second oxide region.First source/drain sets Put on the first oxide region and be connected with the end part of the first nano wire.
According to the exemplary implementations of present inventive concept, there is provided a kind of semiconductor devices is as follows.Substrate has There is oxide region.First and second nano wires are spaced apart with substrate, extend in a first direction, and It is spaced apart from each other on one direction.First gate electrode is around the periphery of the first nano wire and is intersecting first direction Second party upwardly extend.Second gate electrode is around the periphery of the second nano wire and prolongs in a second direction Stretch.First and second gate spacers are separately positioned on the side wall of first gate electrode and the side wall of the second gate electrode On.Groove is arranged between first gate electrode and the second gate electrode.Groove is by the first and second gate spacers And the oxide region of substrate limits.Oxide region limit the basal surface of groove and not with least part of the One and second gate electrode crossover.Source/drain is arranged on oxide region and fills groove.
According to the exemplary implementations of present inventive concept, there is provided a kind of semiconductor devices is as follows.Substrate has There is the first depression and the second depression being spaced apart from each other.First and second oxide regions filling first depression and Second depression.Nano wire is arranged on substrate and is spaced apart with substrate.Gate electrode surrounds nano wire.Grid electricity Pole is arranged between the first oxide region and the second oxide region.Source electrode and drain electrode respectively with the first oxide Area and the second oxide region are overlapping.
According to the exemplary implementations of present inventive concept, there is provided a kind of semiconductor devices is as follows.First receives Rice noodles are spaced apart with substrate and extend in a first direction.Gate electrode around the first nano wire periphery and The second party for intersecting first direction is upwardly extended.Source/drain is arranged at least side of gate electrode and with One nano wire connects.Contact is formed in source/drain and overlapping with the first nano wire in a first direction.Erosion Carve stop-layer to be plugged between contact and substrate.
According to the exemplary implementations of present inventive concept, there is provided a kind of method of manufacture semiconductor devices is such as Under.The fin structure for extending in a first direction is formed on substrate.Fin structure have fin pattern, Nanowire precursor, the first semiconductor pattern and the second semiconductor pattern.First and second semiconductor patterns are erected Directly it is layered on fin pattern, nanowire precursor is plugged on the first semiconductor pattern and the second semiconductor figure Between case.Dummy gate electrode is formed in fin structure, and the dummy gate electrode intersects fin structure and handing over The second party of fork first direction is upwardly extended.First sept is formed on the side wall of dummy gate electrode.It is empty If the Part I of gate electrode and the overlapping fin pattern of the first sept.The no and illusory grid of fin structure The first and second overlapping semiconductor patterns of electrode and the first sept are removed to expose out fin pattern Part II and form the pattern of nanowires obtained from nanowire precursor patterning.Oxide region shape Into in the top of the Part II of fin pattern.
According to the exemplary implementations of present inventive concept, there is provided a kind of method of manufacture semiconductor devices is such as Under.The fin pattern for projecting and extending in a first direction is formed from substrate.Formed upper with fin pattern The nano wire that spaced surface is opened and extended in a first direction.Etching stopping layer is formed in the upper of fin pattern In portion region.Source/drain is formed on etching stopping layer and nano wire.Source/drain is given birth to from nanowire epitaxy It is long.Contact hole is formed until etching stopping layer is exposed in source/drain by using etch process.Contact Formed in the contact hole.
Description of the drawings
By reference to accompanying drawing describe in detail inventive concept exemplary implementations, inventive concept these and its He will become apparent from feature, wherein:
Fig. 1 is the perspective view of the semiconductor devices of the exemplary implementations according to present inventive concept；
Fig. 2 is the sectional view obtained along the line A-A of Fig. 1；
Fig. 3 is the sectional view obtained along the line B-B of Fig. 1；
Fig. 4 is the sectional view obtained along the line C-C of Fig. 1；
Fig. 5 illustrates the gate spacer of Fig. 4；
Fig. 6 to 8 is the view of the semiconductor devices of the exemplary implementations according to present inventive concept；
Fig. 9 to 11 is the sectional view of the semiconductor devices of the exemplary implementations according to present inventive concept；
Figure 12 is the sectional view of the semiconductor devices of the exemplary implementations according to present inventive concept；
Figure 13 is the sectional view of the semiconductor devices of the exemplary implementations according to present inventive concept；
Figure 14 is the perspective view of the semiconductor devices of the exemplary implementations according to present inventive concept；
Figure 15 is the sectional view obtained along the line D-D of Figure 14；
Figure 16 to 33 is the manufacture of the semiconductor devices for illustrating the exemplary implementations according to present inventive concept The view of method；
Figure 34 is the electronic system of the semiconductor devices for including the exemplary implementations according to present inventive concept Block diagram；With
Figure 35 and 36 shows the semiconductor devices including the exemplary implementations according to present inventive concept Semiconductor system.
Although the corresponding flat figure of some sectional views and/or perspective view may be not shown, it is shown in which Device architecture sectional view provide for as by shown in plan view along two different directions The support of the multiple device architectures for extending, and/or for as by shown in the perspective in three not Tongfangs The support of upwardly extending multiple device architectures.Two different directions may be orthogonal to each other or not can that This is orthogonal.Three different directions may include that the third direction of two different directions can be orthogonal to.Multiple devices Part structure can be integrated in same electronic device.For example, when device architecture (for example, memory cell structure Or transistor arrangement) when illustrating in sectional view, (for example, electronic device may include multiple device architectures Memory cell structure or transistor arrangement), this will be illustrated by the plane of electronic device.Multiple devices Structure can be arranged to array and/or two-dimensional pattern.
Specific embodiment
The exemplary implementations of inventive concept are described in detail hereinafter with reference to accompanying drawing.However, inventive concept Can in different forms realize and should not be construed as limited to embodiment set forth herein.In accompanying drawing In, for the thickness that clearly can exaggerate layer and region.It will be further understood that when element is referred to as another One element or substrate " on " when, it directly on another element or substrate, or can also can be present Interlayer.It will be further understood that when element is referred to as " being connected to " or " being connected to " another element, It can be directly coupled to or be directly connected to another element, or can also there are intervening elements.Whole In individual specification and drawings, identical reference may refer to identical element.
Below, the semiconductor devices according to embodiment will be illustrated referring to figs. 1 to 5.
Fig. 1 is the perspective view of the semiconductor devices according to exemplary implementations, and Fig. 2 is the line along Fig. 1 The sectional view that A-A is obtained.Fig. 3 is the sectional view obtained along the line B-B of Fig. 1, and Fig. 4 is along Fig. 1 Line C-C obtain sectional view.Fig. 5 only illustrates the gate spacer of Fig. 4.For the ease of explaining, Fig. 1 Eliminate the diagram of the interlayer insulating film 180 of Fig. 2.
Referring to figs. 1 to 5, according to the semiconductor devices 1 of exemplary implementations may include fin pattern 110, First nano wire 120, gate electrode 130, gate spacer 140, source/drain 150 or contact 190.
For example, substrate 100 can be body silicon or silicon-on-insulator (SOI).Alternatively, substrate 100 can Being silicon substrate, or other materials are may include, such as SiGe, indium antimonide, telluride lead compound, arsenic Indium, indium phosphide, GaAs or gallium antimonide.Alternatively, substrate 100 can be base substrate, epitaxial layer It is formed in the base substrate.
Fin pattern 110 can be projected from substrate 100.Field insulating layer 105 can at least in part cover fin The side wall of type pattern 110.Fin pattern 110 can be limited by field insulating layer 105.Field insulating layer 105 May include such as at least one of oxide, nitride, nitrogen oxides or its combination.
As shown in figure 1, the side wall of fin pattern 110 can by field insulating layer 105 entirely around, but It is noted that this is for illustration purposes only, exemplary implementations not limited to this.
Fin pattern 110 can be extended on X in a first direction.For example, fin pattern 110 may include The long side extended on first direction X and the minor face extended in second direction Y.
Fin pattern 110 can be formed by partly etching substrate 100.Alternatively, fin pattern 110 may include to grow epitaxial layer on the substrate 100.For example, fin pattern 110 may include element half Conductor material such as silicon or germanium.Additionally, fin pattern 110 may include compound semiconductor, for example, IV-IV Compound semiconductor or Group III-V compound semiconductor.
For example, in IV-IV compound semiconductors, fin pattern 110 can be include such as carbon (C), At least two or the binary compound or ternary of more in silicon (Si), germanium (Ge) and tin (Sn) Compound or the above-mentioned binary or ternary compound doped with IV races element.
For example, in Group III-V compound semiconductor, fin pattern 110 can be binary compound, Ternary compound or quaternary compound, it is formed as group-III element and is combined with V group element, wherein the III Race's element can be at least one in aluminium (Al), gallium (Ga) and indium (In), and the V group element can be with It is at least one in phosphorus (P), arsenic (As) and antimony (Sb).
In the description below, it is assumed that fin pattern 110 may include silicon.
Oxide region 115 can be formed on fin pattern 110.Oxide region 115 can be formed in base In plate 100 and on the upper surface of the fin pattern 110 of substrate 100.For example, oxide region 115 can To be formed as filling the depression being formed in substrate 100.Oxide region 115 may include oxide skin(coating).Example Such as, oxide region 115 may include silica (SiO2)。
Oxide region 115 can be overlapping with source/drain 150, and source/drain 150 will be described hereinafter.Oxygen Compound area 115 can be with the lower surface directly contact of source/drain 150.Oxide region 115 can be prevented in grid By the upper table of substrate 100 between source/drain 150 and another source/drain 150 on electrode 130 There is parasitic planar transistor in face.Oxide region 115 can be overlapping with gate spacer 140, gate spacer 140 will be described hereinafter.Oxide region 115 can be with the lower surface directly contact of gate spacer 140. For example, gate spacer 140 can be with the lower surface directly contact of inner spacer 142, inner spacer 142 will be described hereinafter.
Oxide region 115 can be concave-like shape.Therefore, oxide region 115 can be at the center of source/drain Place is with depth capacity W1 and with the center that source/drain 150 is left on X in a first direction Distance increase and depth W2, W3 that is gradually reduced, rather than with uniform depth.Oxide region 115 concave shape can be produced due to the oxygen distribution in plasma oxidation process or ion implantation technology It is raw.
First nano wire 120 can be formed on the substrate 100, and be spaced apart with substrate 100.First receives Rice noodles 120 can extend on X in a first direction.
First nano wire 120 can be formed on fin pattern 110, and is spaced apart with fin pattern 110. First nano wire 120 can be overlapping with fin pattern 110.First nano wire 120 can be formed in fin On pattern 110, rather than it is formed on field insulating layer 105.
As shown in figure 3, width of first nano wire 120 in second direction Y can be with fin pattern 110 width in second direction Y are identical, it should be noted that this is merely to explanation conveniently assumes , exemplary implementations not limited to this.In addition, although illustrate the first nano wire 120 and there is square horizontal stroke Section, but exemplary implementations not limited to this.The turning of the first nano wire 120 can be by such as repairing Whole technique and be rounded.
First nano wire 120 can serve as the channel region of transistor.First nano wire 120 can be according to partly leading Body device 1 is p-type metal oxide semiconductor (PMOS) or n-type metal oxide semiconductor (NMOS) change, but present inventive concept not limited to this.
Additionally, the first nano wire 120 may include and the identical material of fin pattern 110, or including difference In the material of fin pattern 110.However, for convenience of description, it will be assumed herein that the of semiconductor devices One nano wire 120 may include silicon.
Gate electrode 130 can be formed on field insulating layer 105 and fin pattern 110.Gate electrode 130 can Extend in second direction Y.
Gate electrode 130 can be formed about first nanometer be spaced apart with the upper surface of fin pattern 110 The periphery of line 120.Gate electrode 130 also may be formed at and be limited to the first nano wire 120 and fin pattern 110 Between space in.
Gate electrode 130 may include conductive material.As shown, gate electrode 130 can be individual layer, but Not limited to this.For example, gate electrode 130 may include adjust work function work function conductive layer and filling by with The filling conductive layer in the space that the work function conductive layer adjusted in work function is formed.
For example, gate electrode 130 may include at least one of the following：TiN、WN、TaN、Ru、TiC、 TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W and Al.Alternatively, gate electrode 130 each can be formed by nonmetalloid such as Si or SiGe.For example, Gate electrode 130 as above can be formed by replacement technique, but present inventive concept not limited to this.
Gate spacer 140 can be formed along two side walls of the gate electrode 130 of second direction Y extension On.Gate spacer 140 can be formed on the both sides of the first nano wire 120, facing with each other.Grid are spaced Thing 140 each may include through hole 140h.
First nano wire 120 may pass through gate spacer 140.First nano wire 120 may pass through through hole 140h. Gate spacer 140 can be completely attached to the periphery of a part of side of the first nano wire 120.
When the turning of the first nano wire 120 surrounded by gate electrode 130 is by the technique such as repaired and quilt During sphering, the part contacted with gate spacer 140 of the side of the first nano wire 120 can have with by grid The different section in the section of the first nano wire 120 that electrode 130 is surrounded.
Gate spacer 140 may include outer spacers 141 and inner spacer 142.Outer spacers 141 Can be with the directly contact of inner spacer 142.Inner spacer 142 can be arranged on fin pattern 110 Upper surface and the first nano wire 120 between and contact with the upper surface surface of fin pattern 110. On YZ sections, inner spacer 142 can be enclosed by the first nano wire 120 and outer spacers 141 Around.
The through hole 140h of gate spacer 140 can be limited by outer spacers 141 and inner spacer 142 It is fixed.The end of the first nano wire 120 can contact with outer spacers 141 and inner spacer 142.
With reference to Fig. 5, through hole 140h may include first side 140h-1 facing with each other in second direction Y With second side 140h-2 facing with each other on third direction Z.Second side 140h-2 of through hole 140h First side 140h-1 facing with each other of through hole 140h can be connected.
In the semiconductor devices according to embodiment, at least one second side 140h-2 of through hole 140h Can be limited by inner spacer 142.However, first side 140h-1 of through hole 140h can be by outer Portion's sept 141 is limited.
For example, through hole 140h may include three sides 140h-1, the 140h-2 limited by outer spacers 141 With the side 140h-2 limited by inner spacer 142.
Herein, first side 140h-1 of through hole 140h can be limited by outer spacers 141.Additionally, One second side 140h-2 of through hole 140h can be limited by outer spacers 141, but through hole 140h Another second side 140h-2 can be limited by inner spacer 142.
Outer spacers 141 and inner spacer 142 may include material different from each other.When including outside Material in portion's sept 141 has the first dielectric constant and the material being included in inner spacer 142 When material has the second dielectric constant, the first dielectric constant and the second dielectric constant can be with different from each other.
The material being included in outer spacers 141 can have than being included in inner spacer 142 in material Big first dielectric constant of second dielectric constant of material.The first dielectric is less than by causing the second dielectric constant Constant, can reduce the edge capacitance between gate electrode 130 and source/drain 150.
For example, outer spacers 141 may include at least one of the following：Silicon nitride (SiN), nitrogen oxygen SiClx (SiON), silica (SiO2), oxygen carbonitride of silicium (SiOCN) and its combination.For example, it is interior Portion's sept 142 may include at least one of the following：Low k dielectric, silicon nitride (SiN), nitrogen Silica (SiON), silica (SiO2), oxygen carbonitride of silicium (SiOCN) and its combination.Low k is situated between Electric material can be the material with the dielectric constant lower than silica.
Gate spacer 140 may include the first area 140a and the second area 140b.Second area 140b of gate spacer The both sides that can be arranged on relative to the first area 140a in middle of gate spacer in second direction Y On.
First area 140a of gate spacer can be the region that the first nano wire 120 is passed through.Between grid Second area 140b of parting can be the region that the first nano wire 120 need not be passed through.For example, The through hole 140h of gate spacer 140 can be included in the first area 140a of gate spacer.
Second area 140b of gate spacer can only include outer spacers 141.Meanwhile, the of gate spacer One area 140a may include the outer spacers 141 and inner spacer 142 of fin pattern 110.Grid are spaced First area 140a of thing may include top 140a-1 and bottom 140a-2.
For example, the top 140a-1 of the first area 140a of gate spacer may include the outer spacers of part 141, the bottom 140a-2 of the first area 140a of gate spacer may include inner spacer 142.For example, The bottom 140a-2 in the firstth area of gate spacer can only include inner spacer 142.
The height of the top 140a-1 of the first area 140a from the upper surface of substrate 100 to gate spacer is big In the height of the bottom 140a-2 of the first area 140a from the upper surface of substrate 100 to gate spacer.
At least one second side 140h-2 of through hole 140h can be by the bottom in the secondth area of gate spacer 140a-2 (that is, inner spacer 142) is limited.However, first side 140h-1 of through hole 140h Can be limited by the top 140a-1 (that is, outer spacers 141) in the firstth area of gate spacer.
The bottom 140a-2 in the firstth area of gate spacer can directly connect with the second area 140b of gate spacer Touch.Additionally, the top 140a-1 in firstth area of the second area 140b and gate spacer of gate spacer is wrapped Include in outer spacers 141.Therefore, the first of the second area 140b of gate spacer and gate spacer The top 140a-1 in area can be overall structure.
The top part of the first nano wire 120 can for example in the nano wire of gate spacer 140 and first Contact with outer spacers 141 at overlap between 120.In other words, first nano wire 120 Topmost part can contact with the top 140a-1 in the firstth area of gate spacer.
Therefore, at the first area 140a of gate spacer, the bottom part of the first nano wire 120 can Contacted with the bottom 140a-2 in the firstth area with gate spacer, the top part of the first nano wire 120 can Contacted with the top 140a-1 in the firstth area with gate spacer.
For example, at the first area 140a of gate spacer, the bottom part of the first nano wire 120 can To contact with inner spacer 142, the top part of the first nano wire 120 can be with outer spacers 141 contacts.
Gate insulation layer 147 can be formed between the first nano wire 120 and gate electrode 130.Additionally, grid Insulating barrier 147 can be formed between field insulating layer 105 and gate electrode 130, in the and of fin pattern 110 Between gate electrode 130 and between gate spacer 140 and gate electrode 130.
For example, gate insulation layer 147 may include intermediate layer 146 and high k insulating barriers 145, but be not limited to This.For example, according to the material of the first nano wire 120, the intermediate layer 146 of gate insulation layer 147 can be by Omit.
Place because intermediate layer 146 can be formed in the first the outer of nano wire 120, so intermediate layer 146 Can be formed between the first nano wire 120 and gate electrode 130 and in fin pattern 110 and gate electrode Between 130.Meanwhile, high k insulating barriers 145 can be formed in the first nano wire 120 and gate electrode 130 Between, between fin pattern 110 and gate electrode 130, field insulating layer 105 and gate electrode 130 it Between and between gate spacer 140 and gate electrode 130.
Gate insulation layer 147 can be formed along the periphery of the first nano wire 120.Gate electrode 147 can edge The upper surface of the upper surface and fin pattern 110 that field insulating layer 105 is formed.In addition, gate insulation layer 147 Can be formed along the side wall of gate spacer 140.For example, gate insulation layer 147 can be along space outside The side wall of thing 141 and the side wall of inner spacer 142 are formed.
When the first nano wire 120 includes silicon, intermediate layer 146 may include silicon oxide layer.Now, it is middle Layer 146 can be formed on the upper surface of the periphery of the first nano wire 120 and fin pattern 110, but The side wall for needing not be along gate spacer 140 is formed.
High k insulating barriers 145 may include the high-k dielectric material with the dielectric constant than silica floor height. For example, high-k dielectric material may include at least one of the following：Hafnium oxide, hafnium silicon oxide, lanthanum Oxide, lanthanum aluminum oxide, Zirconium oxide, zirconium Si oxide, tantalum pentoxide, titanium oxide, barium strontium Titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum pentoxide, And lead zinc niobate, but present inventive concept not limited to this.
As described above, when intermediate layer 146 is omitted, high k insulating barriers 145 not only can be situated between including high k Electric material and including silicon oxide layer, silicon oxynitride layer or silicon nitride layer.
With reference to Fig. 1 and 2, the first nano wire 120 can be protruded past on X in a first direction and be formed in grid Gate insulation layer 147 (that is, high k insulating barriers 145) on the side wall of electrode 130.As described, first receives The jag of rice noodles 120 can pass through gate spacer 140 via through hole 140h.
Source/drain 150 can be formed on the both sides of gate electrode 130.Source/drain 150 can be formed in On fin pattern 110.Source/drain 150 may include the extension being formed on the upper surface of fin pattern 110 Layer.
The periphery of source/drain 150 can adopt variously-shaped.For example, the periphery of source/drain 150 can be At least one of rhombus, circle, rectangle and octagon-shaped.Fig. 1 illustrate rhombus (or pentagon or Hexagonal shape), for example.
Source/drain 150 can be directly connected to the first nano wire 120 as channel region.For example, source/ Drain electrode 150 can be directly connected to first nano wire 120 of the through hole 140h through gate spacer 140.
However, source/drain 150 need not be with the directly contact of gate insulation layer 147.Gate spacer 140 can be with Between source/drain 150 and gate insulation layer 147.For example, a side wall of inner spacer 142 can To contact with gate insulation layer 147, and another side wall of inner spacer 142 can be with source/drain 150 Contact, in this case, source/drain 150 and gate insulation layer 147 need not be in the first nano wires Contact with each other between 120 and substrate 100.Further, since the nano wire 120 of outer spacers 141 and first The top part contact, so source/drain 150 and gate insulation layer 147 are on the first nano wire 120 Need not contact with each other.
Interlayer insulating film 180 can be formed in source/drain 150.Interlayer insulating film 180 may include low k At least one in dielectric material, oxide, nitride and nitrogen oxides.For example, low k dielectric can Including flowable oxide (FOX), Tonen silazane (Tonen Silazen, TOSZ), undoped p Quartz glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), boron phosphorus silicon Silicate glass (BPSG), plasma enhancing tetraethyl orthosilicate (PETEOS), fluorosilicate glass (fluoride silicate glass, FSG), high-density plasma (HDP) oxide, plasma Strengthen oxide (PEOX), flowable CVD (FCVD) oxides or its combination.
Contact 190 can be formed in interlayer insulating film 180 and source/drain 150.Contact 190 may pass through Interlayer insulating film 180.Contact 190 can be formed in source/drain 150.For example, the side of contact 190 Surface can contact with interlayer insulating film 180 and source/drain 150, and the lower surface for contacting 190 can be with source / drain electrode 150 is contacted.
The lower surface of contact 190 can be less than the lower surface of the first nano wire 120.By under contact 190 Surface forms the performance that semiconductor devices 1 must can be improved less than the lower surface of the first nano wire 120, because The power path formed between the first nano wire 120 and contact 190 is shortened for this.
Contact 190 may include conductive material.For example, contact 190 may include polysilicon, metal silicide At least one of compound, conductive metal nitride and metal, but not limited to this.
Interface between source/drain 150 and substrate 100 is had according to the semiconductor devices 1 of embodiment The oxide region 115 at place.Therefore, by the presence of oxide region 115, substrate 100 and source/drain 150 It is insulated from each other.Source/drain 150 can be formed on the both sides of gate electrode 130 and by the first nano wire 120 are connected to each other.However, source/drain 150 can be additionally formed parasitism by the upper surface of substrate 100 Planar transistor.Therefore, parasitic planar transistor arrangement can be added to primary crystalline tubular construction, and this will Cause semiconductor devices that there is the performance different from desired transistor performance.Partly leading according to embodiment Body device 1 can form parasitic planar crystal by forming oxide region 115 on the substrate 100 to prevent The possibility of tubular construction, the oxide region 115 will cause source/drain 150 to electrically insulate with substrate 100.
Below, by the semiconductor devices with reference to the explanations of Fig. 1 and Fig. 6 to 8 according to another embodiment. For the ease of explaining, the difference not illustrated above with reference to Fig. 1 to 5 hereafter will be mainly illustrated.
Fig. 6 to 8 is to provide to illustrate the view of the semiconductor devices according to exemplary implementations.
Used as reference, Fig. 6 is the sectional view obtained along the line A-A of Fig. 1.Fig. 7 is the line along Fig. 1 The sectional view that C-C is obtained.Fig. 8 only illustrates the gate spacer of Fig. 7.
With reference to Fig. 6 to 8, in the semiconductor devices 2 according to another embodiment, the of gate spacer The bottom 140a-2 in one area may include the multiple insulating patterns being spaced apart on third direction Z.
Therefore, the bottom part of the top part of the first nano wire 120 and the first nano wire 120 can Contacted with the bottom 140a-2 in the firstth area with gate spacer.
The bottom part of the top part of the first nano wire 120 and the first nano wire 120 can with it is interior Portion's sept 142 is contacted.In the first area 140a of gate spacer, the material of inner spacer 142 With the dielectric constant lower than outer spacers 141, the inner spacer 142 is arranged on the first nano wire It is above 120 and following.
For example, through hole 140h may include the two side 140h-1 limited by outer spacers 141 and by Two side 140h-2 that inner spacer 142 is limited.
First side 140h-1 facing with each other in second direction Y of through hole 140h can be by between outside Parting 141 is limited, and second side 140h-2 facing with each other on third direction Z of through hole 140h can To be limited by inner spacer 142.
Below, the semiconductor devices according to exemplary implementations will be illustrated with reference to Fig. 1 and Fig. 9 to 11. For the ease of explaining, the difference not illustrated above with reference to Fig. 1 to 5 hereafter will be mainly illustrated.
Fig. 9 to 11 is the sectional view of the semiconductor devices according to exemplary implementations.
Fig. 9 is the sectional view obtained along the line A-A of Fig. 1.Figure 10 is to obtain along the line B-B of Fig. 1 Sectional view.Figure 11 is the sectional view obtained along the line C-C of Fig. 1.
With reference to Fig. 9 to 11, the second nano wire may include according to the semiconductor devices 3 of exemplary implementations 125。
Second nano wire 125 can be formed on the substrate 100, while being spaced apart with substrate 100.Second Nano wire 125 can extend on X in a first direction.
Second nano wire 125 can be spaced farther than the first nano wire 120 and substrate 100.For example, It is more than from the upper of fin pattern 110 from the upper surface of fin pattern 110 to the height of the second nano wire 125 Height of the surface to the first nano wire 120.
Second nano wire 125 can be overlapping with fin pattern 110.Second nano wire 125 can be formed in On fin pattern 110, rather than it is formed on field insulating layer 105.
Second nano wire 125 can serve as the channel region of transistor.Therefore, the second nano wire 125 can be wrapped Include and the identical material of the first nano wire 120.
Gate electrode 130 can be formed about the periphery of the first nano wire 125.Gate electrode 130 can be with shape Into in the space being limited between the first nano wire 120 and the second nano wire 125.
Gate spacer 140 can be arranged on the two ends of the first nano wire 120 and in the second nano wire On 125 two ends.Each gate spacer 140 may include multiple through hole 140h.
Second nano wire 125 may pass through gate spacer 140.Second nano wire 125 may pass through multiple through holes One in 140h.The periphery of the end of the second nano wire 125 can completely attach to gate spacer 140.
Similar to the first nano wire 120, when the turning of the second nano wire 125 surrounded by gate electrode 130 By the technique such as repaired and during sphering, the end contacted with gate spacer 140 of the second nano wire 125 Portion can have the section different from the section of the second nano wire 125 surrounded by gate electrode 130.
Second nano wire 125 can be aligned with the first nano wire 120.Second nano wire 125 can be Overlap with the first nano wire 120 on three direction Z.First and second nano wires 120,125 can have that This equal length.However, exemplary implementations are not limited to examples given above.
Inner spacer 142 can be arranged on the upper surface of fin pattern 110 and the first nano wire 120 it Between and between the first nano wire 120 and the second nano wire 125.For example, inner spacer 142 can The multiple insulating patterns being spaced apart from each other are included on third direction Z.
With reference to Fig. 9, the uppermost surface of the second nano wire 125 can contact with outer spacers 141, The nethermost surface of the second nano wire 125 can contact with inner spacer 142, although demonstration is implemented Mode not limited to this.For example, the uppermost surface of the second nano wire 125 and the second nano wire 125 Nethermost surface can contact with inner spacer 142 respectively as illustrated in fig. 6.
Gate insulation layer 147 can be formed between the second nano wire 125 and gate electrode 130.Gate insulation layer 147 can form along the periphery of the second nano wire 125.
Source/drain 150 can be directly connected to the second nano wire 125 as channel region.For example, source/ Drain electrode 150 can be received with first nano wire 120 and second of the through hole 140h through gate spacer 140 Rice noodles 125 are directly connected to.
Contact 190 can the first nano wire of distance 120 first apart from G1 and the second nano wire of distance 125 Second distance G2.Contact 190 can in a first direction X be upper and the first nano wire 120 and second nanometer Line 125 is overlapped.For example, the lower surface of contact 190 can be formed as less than under the first nano wire 120 Surface and the lower surface of the second nano wire 125.Therefore, between the nano wire 120 of contact 190 and first Power path and can be respectively shortened to the in power path of the contact 190 and second between nano wire 125 One apart from G1 and second distance G2.First can be identical apart from G1 and second distance G2, but It is present inventive concept not limited to this.
Below, the semiconductor devices 4 according to exemplary implementations will be illustrated with reference to 1 to 12.In order to just In explanation, the difference not illustrated above with reference to Fig. 1 to 5 hereafter will be mainly illustrated.
Figure 12 is the sectional view of the semiconductor devices according to exemplary implementations.Figure 12 is the line along Fig. 1 The sectional view that A-A is obtained.
With reference to Figure 12, oxide region 115-1 can be overlapping with gate electrode 130.However, oxide region 115-1 Need not be overlapping with the gate electrode 130 of part.For example, oxide region 115-1 can only with the grid of part Electrode 130 is overlapped.Oxide region 115-1 can be formed on the both sides of gate electrode 130 and each other every From.Oxide region 115-1 can be with the gate electrode 130 of part, gate spacer 140 and partial source/drain Pole 150 overlaps.
For example, it is contemplated that being provided as preventing in two positioned at the both sides of gate electrode 130 to oxide region 115-1 Parasitic planar transistor, itself and gate spacer 140 and gate electrode 130 are formed between individual source/drain 150 Overlapping is possible.For example, when extend on oxide region 115-1 in a first direction X with gate electrode 130 When overlapping, this can prevent from forming parasitic planar transistor, and therefore semiconductor devices can become more reliable.
Oxide region 115-1 can be overlapped only with the source/drain 150 of part, rather than with source/drain 150 Fully overlap.Because oxide region 115-1 insulate between source/drain 150, thus at least source/ The presence of the oxide region 115-1 that drain electrode 150 is formed at gate electrode 130 can provide enough posting Life junction transistor prevents effect.Present inventive concept not limited to this.For example, oxide region 115-1 can be with Overlap completely with source/drain 150.
Below, the semiconductor devices 5 according to exemplary implementations will be illustrated with reference to 1 to 13.In order to just In explanation, the difference not illustrated above with reference to Fig. 1 to 5 hereafter will be mainly illustrated.
Figure 13 is the sectional view of the semiconductor devices according to exemplary implementations.Figure 13 is the line along Fig. 1 The sectional view that A-A is obtained.
With reference to Figure 13, contact 190-1 can be completely through interlayer insulating film 180 and source/drain 150 To contact with oxide region 115.The lower surface of contact 190-1 can be with the upper table for being formed in substrate 100 The directly contact of oxide region 115 on face.The lower surface of contact 190-1 can pass through oxide region 115 Insulate with substrate 100.Because oxide region 115 can be used as erosion in the technique for forming contact 190-1 Stop-layer is carved, so process efficiency can be improved according to the device of embodiment.
In order to form contact 190-1, contact hole 190-H can be formed by using etch process.So When doing, oxide region 115 can serve as etching stopping layer to prevent the further of fin pattern 110 Etching.
Below, the semiconductor devices according to exemplary implementations will be illustrated with reference to Figure 14 and 15.In order to It is easy to explain, hereafter will mainly illustrates the difference not illustrated above with reference to Fig. 1 to 5.
Figure 14 is the perspective view of the semiconductor devices according to exemplary implementations, and Figure 15 is along Figure 14 The sectional view that line A-A is obtained.
With reference to Figure 14 and 15, second can be comprised additionally according to the semiconductor devices 6 of another embodiment Gate electrode 130, the second gate spacer 240, the second gate insulation layer 247 and the 3rd nano wire 220.
3rd nano wire 220 can be formed and is spaced apart on the substrate 100 and with substrate 100.3rd nanometer Line 220 can extend on X in a first direction.
For example, the 3rd nano wire 220 can be formed on fin pattern 110 and between fin pattern 110 Separate.3rd nano wire 220 can be overlapping with fin pattern 110.3rd nano wire 220 can be formed On fin pattern 110, rather than it is formed on field insulating layer 105.
3rd nano wire 220 can be overlapped on X in a first direction with the first nano wire 120.For example, Three nano wires 220 can be the extension from the first nano wire 120, and it can be by separating technology and the One nano wire 120 is spaced apart.
Additionally, the 3rd nano wire 220 may include and the identical material of fin pattern 110, or including difference In the material of fin pattern 110.However, for the ease of explaining, it is assumed that the 3rd nanometer of semiconductor devices Line 220 can include silicon.
Second gate electrode 230 can be formed on field insulating layer 105 and fin pattern 110.Second gate electricity Pole 230 can extend in second direction Y.
Second gate electrode 230 can be formed about the 3rd be spaced apart with the upper surface of fin pattern 110 The periphery of nano wire 220.Second gate electrode 230 can be formed in and be limited to the 3rd nano wire 220 and fin In space between type pattern 110.
Second gate electrode 230 can include conductive material.As shown, the second gate electrode 230 can be Individual layer, but not limited to this.For example, the second gate electrode 230 may include that the work function for adjusting work function is led The filling conductive layer in the space that electric layer and filling are formed by the work function conductive layer adjusted for work function.
For example, the second gate electrode 230 may include at least one of the following：TiN、WN、TaN、Ru、 TiC、TaC、Ti、Ag、Al、TiAl、TiAlN、TiAlC、TaCN、TaSiN、Mn、Zr、 W and Al.Alternatively, each second gate electrode 230 can be formed by nonmetalloid such as Si or SiGe. For example, the second gate electrode 230 as above can be formed by replacing technique, but not limited to this.
Second gate spacer 240 can be formed along the two of the second gate electrode 230 of second direction Y extension On individual side wall.Second gate spacer 240 can be formed in the both sides facing with each other of the 3rd nano wire 220 On.
3rd nano wire 220 can extend only through in two the second gate spacers 240.However, showing Model embodiment is not limited to example provided above.Therefore, similar to the first nano wire 120, the 3rd receives Rice noodles 220 can pass through two the second gate spacers 240.Only for the purposes of explanation, the 3rd is here it is assumed that Nano wire 220 can extend only through in the second gate spacer 240.3rd nano wire 220 has two Individual end, the end that the first nano wire 120 is only for example adjacent in the middle of two ends can be through the Two gate spacers 240.The second gate spacer 240 being through is adjacent in two the second gate spacers 240 It is bordering on second gate spacer 240 of the first nano wire 120.
Second gate spacer 240 that the first nano wire 120 is adjacent in second gate spacer 240 can With including the second outer spacers 241 and the second inner spacer 242.Second outer spacers 241 can With with the directly contact of the second inner spacer 242.Second inner spacer 242 can be arranged on fin figure Connect between the upper surface of case 110 and the 3rd nano wire 220 and with the upper surface surface of fin pattern 110 Touch.On YZ sections, the second inner spacer 242 can be by outside the 3rd nano wire 220 and second Sept 241 is surrounded.
Second outer spacers 241 and the second inner spacer 242 can include material different from each other. Material in the second outer spacers 141 are included in has the first dielectric constant and is included in second When material in portion's sept 242 has the second dielectric constant, the first dielectric constant and the second dielectric constant Can be with different from each other.
In the semiconductor devices according to embodiment, the material being included in the second outer spacers 241 There can be the first dielectric constant, first dielectric constant is more than being included in the second inner spacer 242 Second dielectric constant of material.
For example, the second outer spacers 241 may include at least one of the following：Silicon nitride (SiN), Silicon oxynitride (SiON), silica (SiO2), oxygen carbonitride of silicium (SiOCN) and its combination.For example, Second inner spacer 242 may include at least one of the following：Low k dielectric, silicon nitride (SiN), Silicon oxynitride (SiON), silica (SiO2), oxygen carbonitride of silicium (SiOCN) and its combination.Low k Dielectric material can be the material with the dielectric constant lower than silica.
Second gate spacer 240 of the first nano wire 120 is adjacent in second gate spacer 240 not Needs are passed through by the 3rd nano wire 220, it is possible to including the second outer spacers 241, and do not include the Two inner spacers 242.
Second gate insulation layer 247 can be formed between the 3rd nano wire 220 and the second gate electrode 230. Additionally, the second gate insulation layer 247 can be formed between the gate electrode 230 of field insulating layer 105 and second, Between the gate electrode 230 of fin pattern 110 and second and in the second gate spacer 240 and second gate Between electrode 230.
For example, the second gate insulation layer 247 can include the second intermediate layer 246 and the second high k insulating barriers 245, but not limited to this.For example, the second intermediate layer 246 of the second gate insulation layer 247 can basis The material of the 3rd nano wire 220 and be omitted.
Place because the second intermediate layer 246 can be formed in the 3rd the outer of nano wire 220, so in second Interbed 146 can be formed between the 3rd nano wire 220 and the second gate electrode 230 and in fin pattern 110 and second between gate electrode 230.Meanwhile, the second high k insulating barriers 245 can be formed in the 3rd and receive Between the gate electrode 230 of rice noodles 220 and second, between the gate electrode 230 of fin pattern 110 and second, Between the gate electrode 230 of field insulating layer 105 and second and in the second gate spacer 240 and second gate Between electrode 230.
Second gate insulation layer 247 can be formed along the periphery of the 3rd nano wire 220.Second gate insulation layer 247 can form along the upper surface of the upper surface of field insulating layer 105 and fin pattern 110.In addition, Second gate insulation layer 247 can be formed along the side wall of the second gate spacer 240.For example, second gate is exhausted Edge layer 247 can be along the side wall of the second outer spacers 241 and the side wall of the second inner spacer 242 Formed.
When the 3rd nano wire 220 includes silicon, the second intermediate layer 246 can include silicon oxide layer.Now, Second intermediate layer 246 can be formed in the periphery of the 3rd nano wire 220 and the upper surface of fin pattern 110 On, but the side wall for needing not be along the second gate spacer 240 is formed.
Second high k insulating barriers 245 may include the high k dielectric material with the dielectric constant than silica floor height Material.For example, high-k dielectric material may include it is following in one or more：Hafnium oxide, the oxidation of hafnium silicon Thing, lanthanum-oxides, lanthanum aluminum oxide, Zirconium oxide, zirconium Si oxide, tantalum pentoxide, titanium oxide, Barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxygen Compound and lead zinc niobate, but not limited to this.
As described above, when the second intermediate layer 246 is omitted, the second high k insulating barriers 245 can be wrapped not only Include high-k dielectric material and including silicon oxide layer, silicon oxynitride layer or silicon nitride layer.
Below, by referring to figures 16 to 33 explanation being used for producing the semiconductor devices according to embodiment Method.The semiconductor devices manufactured based on Figure 16 to 33 partly being led corresponding to what is described above with reference to Figure 13 Body device 5.
Figure 16 to 33 is the view of the manufacture method for illustrating the semiconductor devices according to exemplary implementations. Figure 30 is the sectional view obtained along the line E-E of Figure 29, and Figure 31 is along cutting that the line F-F of Figure 29 is obtained Face figure.
With reference to Figure 16, the first sacrifice layer 2001, the sacrifice layer 2003 of active layer 2002 and second are sequentially Formed on the substrate 100.
First sacrifice layer 2001 and the second sacrifice layer 2003 can include identical material, the first sacrifice layer 2001 and active layer 2002 can include different materials.Illustrating according to embodiment for manufacturing During the method for semiconductor devices, it is assumed that the first sacrifice layer 2001 and the second sacrifice layer 2003 include identical Material.Additionally, active layer 2002 can include thering is etching selectivity relative to the first sacrifice layer 2001 Material.
For example, substrate 100 and active layer 2002 can include the material of the channel region by transistor is used as Material.For example, in the pmos case, active layer 2002 can include the material with high hole mobility Material, and in the nmos case, active layer 2002 can include the material with high electron mobility.
First sacrifice layer 2001 and the second sacrifice layer 2003 can be included with similar to active layer 2002 Lattice paprmeter and lattice structure material.For example, the first sacrifice layer 2001 and the second sacrifice layer 2003 It can be the metal material of semi-conducting material or crystallization.
Explanation according to embodiment be used for producing the semiconductor devices method when, it is assumed that active layer 2002 Including silicon, the first sacrifice layer 2001 and the second sacrifice layer 2003 each include SiGe.
Figure 16 only illustrates an active layer 2002, but this is solely for the purpose of illustration, and demonstrates Embodiment not limited to this.Therefore, it can have multiple the first paired sacrifice layers 2001 being alternatively formed It is formed on uppermost active layer 2002 with active layer 2002, and the second sacrifice layer 2003.
In addition, although Figure 16 shows the second sacrifice layer on the top part of stacking Rotating fields 2003, but exemplary implementations not limited to this.Therefore, active layer 2002 can be in stacking Rotating fields The top part on.
Then, the first mask pattern 2103 is formed on the second sacrifice layer 2003.First mask pattern 2103 Can extend on X in a first direction.
For example, the first mask pattern 2103 can by comprising in silica, silicon nitride and silicon oxynitride extremely Few one material is formed.
With reference to Figure 17, etch process is performed as mask using the first mask pattern 2103, be consequently formed Fin structure 110P.
Fin structure 110P can by the second sacrifice layer 2003 of patterned features, active layer 2002, First sacrifice layer 2001 and substrate 100 and formed.
Fin structure 110P can be formed and projected on the substrate 100 and from substrate 100.Fin structure 110P Can extend on X in a first direction, as the situation of the first mask pattern 2103.
In fin structure 110P, fin pattern 110, the first sacrificial pattern 121, nanowire precursor (pre-nanowire) 122 and second sacrificial pattern 123 be sequentially laminated on the substrate 100.
With reference to Figure 18, the field insulating layer 105 for covering at least part of side wall of fin structure 110P can be with shape Into on the substrate 100.
For example, the field insulating layer 105 for covering fin structure 110P is formed on the substrate 100.Due to field The flatening process of insulating barrier 105, the upper surface of fin structure 110P and the upper table of field insulating layer 105 Face may be at identical plane.
First mask pattern 2103 can be removed in flatening process, but not limited to this.
Then the top of field insulating layer 105 is recessed into, and thus exposes fin structure 110P of part.It is recessed Entering technique can include etch process.For example, fin structure 110P can be formed as in field insulating layer 105 Upper protrusion.
With reference to Figure 18, the second sacrificial pattern 123, the sacrificial pattern 121 of nanowire precursor 122 and first can To project on the upper surface of field insulating layer 105, the side wall of fin pattern 110 can be by field insulating layer 105 Completely about, but exemplary implementations not limited to this.For example, the one of the side wall of fin pattern 110 Part can be by the recessed technique on the top of field insulating layer 105 on the upper surface of field insulating layer 105 It is prominent.
Beyond causing to be partially project into described in fin structure 110P the upper surface of field insulating layer 105 Before or after the recessed technique, nanowire precursor 122 can be doped to adjust the crystalline substance that will be formed The threshold voltage of body pipe.When semiconductor devices 1-6 is nmos pass transistor, impurity can be boron (B). When semiconductor devices 1-6 is PMOS transistor, impurity can be phosphorus (P) or arsenic (As), but Not limited to this.
With reference to Figure 19, etch process is performed by using the second mask pattern 2104, can be formed illusory Gate pattern 135, it extends across fin structure 110P in second direction Y.Dummy gate electrode pattern 135 can be formed in fin structure 110P.
Dummy gate electrode pattern 135 can include illusory gate insulation layer 136 and dummy gate electrode 137.For example, Dummy gate electrode insulating barrier 136 can include silicon oxide layer, dummy gate electrode 137 can include polysilicon or Non-crystalline silicon.
With reference to Figure 20, outer spacers 141 can be formed on the side wall of dummy gate electrode pattern 135.Example Such as, outer spacers 141 can be formed in the side wall and dummy gate electrode 137 of illusory gate insulation layer 136 Side wall on.
For example, the first spacer layer is formed on field insulating layer 105, covers the He of dummy gate electrode pattern 135 Fin structure 110P.Then, the first spacer layer is etched back quarter, so as in dummy gate electrode pattern 135 Side wall on retain outer spacers 141.
With reference to Figure 21, using etch process remove not with dummy gate electrode 137 and outer spacers 141 Overlapping fin structure 110P.In the etch process, including dummy gate electrode 137 dummy gate electrode pattern 135 can serve as etching mask.By doing so it is possible, depression 150r can be formed in fin structure 110P It is interior.The basal surface of depression 150r can be fin pattern 110.
Forming outer spacers 141 and forming depression 150r to be carried out simultaneously, although demonstration embodiment party Formula not limited to this.For example, the 150r that is recessed can pass through removal portion after outer spacers 141 are formed Point fin structure 110P and formed.
Can be to remove not having and illusory grid electricity although depression 150r is formed in fin structure 110P The first overlapping sacrificial pattern 121 of pole 137 and outer spacers 141 and the second sacrificial pattern 123.This Outward, when the 150r that is recessed is formed in fin structure 110P, with not with dummy gate electrode 137 and outward The overlapping nanowire precursor 122 of portion's sept 141 is removed, and can form the first nano wire 120.
By the presence of the 150r that is recessed, the section of the first sacrificial pattern 121, the second sacrificial pattern are cut The section of face and the first nano wire 120 can be exposed.
With reference to Figure 22, oxidation prevents layer 143 to be formed on the side wall of outer spacers 141.Oxidation Prevent layer 143 from can again cover the first sacrificial pattern 121, the second sacrificial pattern 123 and first nanometer The exposed section of line 120.
For example, oxidation prevents layer 143 from can be carbon polymer or other insulating materials.Oxidation technology it Afterwards, oxidation prevents the stage that layer 143 can be to be below removed.In order to using ashing or wet etching It is removed, the material that ashing or wet etching can be utilized processed can be included.If oxidation prevents layer 143 include another insulating materials, then oxidation prevents layer 143 to have the erosion relative to gate spacer 140 Carve selective, it is possible to be removed by using the wet etching process of the etching selectivity.
For example, oxidation prevents a layer precursor (pre-oxidation preventing layer) to be formed in field insulating layer On 105, dummy gate electrode pattern 135, fin structure 110P and outer spacers 141 are covered.With oxygen Chemoprevention is stopped layer precursor and is etched back quarter, and oxidation prevents layer 143 to be formed in the side wall of outer spacers 141 On.
Forming oxidation prevents layer 143 to be omitted according to the type of subsequent oxidation technology.For example, For having directive oxidation technology, the oxidation technology can be carried out without requiring that to form oxidation prevents Layer 143.
With reference to Figure 23, oxidation technology 114 can be in the fin pattern 100 being exposed by the 150r that is recessed On carry out.Oxidation technology can include plasma oxidation process or O +ion implanted technique.In oxidation work In skill 114, the top of fin pattern 110 can be oxidized, and be changed into oxide region 115.Therefore, fin Type pattern 110 can include oxide region 115, used as a part for fin pattern 110.In this situation Under, oxide region 115 may be located in the top of fin pattern 110.
Plasma oxidation process on third direction Z by applying O2Plasma and aoxidize.Carrying Under being supplied to the high bias of substrate 100, only the top of fin pattern 110 can be oxidized.Implement in demonstration In mode, the above-mentioned technique of layer 143 is prevented to be omitted for forming oxidation.
O +ion implanted injects oxonium ion to fin pattern 110 and then carries out by using ion implantation device Heat treatment makes the upper oxide of fin pattern 110.O +ion implanted can allow in the vertical direction from Son injection.In exemplary implementations, the oxidation for forming Figure 22 prevents the technique of layer 143 can be with It is omitted.
With reference to Figure 24, oxide region 115 can be formed by oxidation technology 114.Oxide region 115 can In to be formed in the top of fin pattern 110.For example, the thickness of oxide region 115 can be about 10nm, but not limited to this.The thickness of oxide region 115 can become according to the characteristic of oxidation technology 114 Change.In exemplary implementations, oxide region 115 can have X along a first direction gradually to increase then The thickness of reduction.
With reference to Figure 25, at least portion for being exposed by the 150r that is recessed and being overlapped with outer spacers 141 The first sacrificial pattern 121 and at least part of second sacrificial pattern 123 divided can be removed to form recessed Hole 142r, pit 142r can be formed between the nano wire 120 of outer spacers 141 and first.
First nano wire 120 can be from the first sacrificial pattern 121 and second being retained in pit 142r Sacrificial pattern 123 is projected.
For example, pit 142r can be formed by using etch process is selected.For example, pit 142r Can use and there is the first sacrificial pattern 121 and the second sacrificial pattern 123 relative to the first nano wire 120 The etchant of etching selectivity formed by etch process.
With reference to Figure 26, inner spacer 142 can be formed by filling pit 142r with insulating materials.
For example, the second spacer layer can be formed, pit 142r is filled.Second spacer layer can be tool There is the material of excellent clearance filling capability.Second spacer layer can also be formed in field insulating layer 105, On the side wall and dummy gate electrode pattern 135 of outer spacers 141.
Then, etch process can be performed to remove the second spacer layer, until no and dummy gate electrode The upper surface of the overlapping fin pattern 110 of pattern 135 and outer spacers 141 is exposed.As a result, may be used To form inner spacer 142.
Now, the thickness of inner spacer 142 can be controlled to make the first nano wire 120 between inside Parting 142 is projected.For example, the thickness of inner spacer 142 can be equal to the thickness of outer spacers 141 Degree.However, present inventive concept not limited to this.For example, the thickness of inner spacer 142 can be differently configured from The thickness of outer spacers 141.
Therefore, it can to form the gate spacer 140 including outer spacers 141 and inner spacer 142.
With reference to Figure 27, can be formed for the source/drain 150 of filling depression 150r.Source/drain 150 can To be formed on the both sides of dummy gate electrode pattern 135.
Source/drain 150 can be formed on the nano wire 120 of oxide region 115 and first, as inculating crystal layer. However, present inventive concept not limited to this.For example, inculating crystal layer is additionally formed in sudden and violent by the 150r that is recessed On the section and oxide region 115 of the first nano wire 120 of dew.
Source/drain 150 can be formed as covering inner spacer 142.Source/drain 150 can be with inside Sept 142 is contacted.
Source/drain 150 can be formed by epitaxy technique.It is according to the semiconductor devices of exemplary implementations N-type transistor or p-type transistor, thus it is possible to vary the impurity adulterated in the epitaxial layer of source/drain 150. In exemplary implementations, impurity can be in-situ doped during epitaxy technique.
With reference to Figure 28, interlayer insulating film 180 can be formed on field insulating layer 105, cover source/drain 150th, gate spacer 140, dummy gate electrode pattern 135 etc..
Interlayer insulating film 180 may include in low k dielectric, oxide, nitride and nitrogen oxides extremely It is few one.For example, low k dielectric can be flowable oxide (FOX), Tonen silazane (TOSZ), unadulterated quartz glass (USG), borosilicate glass (BSG), phosphosilicate glass Glass (PSG), boron phosphorus silicate glass (BPSG), plasma enhancing tetraethyl orthosilicate (PETEOS), Fluorosilicate glass (FSG), high-density plasma (HDP) oxide, plasma enhancing oxygen Compound (PEOX), flowable CVD (FCVD) oxides or its combination.
Then, interlayer insulating film 180 is flattened until the upper surface of dummy gate electrode 137 is exposed. As a result, the second mask pattern 2104 is removed, and exposes the upper surface of dummy gate electrode 137.
With reference to Figure 29 to 31, dummy gate electrode pattern 135 can be removed, i.e. remove illusory gate insulation layer 136 and dummy gate electrode 137.
Due to eliminating illusory gate insulation layer 136 and dummy gate electrode 137, with dummy gate electrode pattern 135 Overlapping field insulating layer 105 and fin structure 110P can be exposed.For example, with dummy gate electrode pattern 135 the first overlapping sacrificial patterns 121, the second sacrificial pattern 123 and the first nano wire 120 now may be used To be exposed.
With reference to Figure 32 and 33, the first sacrificial pattern 121 and the second sacrificial pattern 123 can be tied from fin Structure 110P is removed, and the first nano wire 120 can be retained in fin structure 110P.
As a result, space can be formed between the first nano wire 120 and fin pattern 100, first nanometer Line 120 can be formed in the top of fin pattern 110.
Remove the first sacrificial pattern 121 and the second sacrificial pattern above and below the first nano wire 120 123 can perform for example, by etch process.For example, it is possible to use the first sacrificial pattern 121 and Etching selectivity of two sacrificial patterns 123 relative to the first nano wire 120.
In addition, removing the first sacrificial pattern 121 and the second sacrificial pattern 123 can allow gate spacer 140 Inner spacer 142 be exposed.
Referring again to Figure 13, intermediate layer 146 can be formed in the periphery of the first nano wire 120 and fin figure On the upper surface of case 110.
Then high k insulating barriers 145 can be formed on the side wall of gate spacer 140, i.e. between outside On the side wall of parting 141 and inner spacer 142 and along the periphery of the first nano wire 120.High k Insulating barrier 145 can be contacted with inner spacer 142.Therefore, it can be formed including the He of intermediate layer 146 The gate insulation layer 147 of high k insulating barriers 145.
It is then possible to form gate electrode 130, prolong around the first nano wire 120 and in second direction Y Stretch.Gate electrode 130 can replace metal gate electrode.
It is then possible to contact 190-1 is formed, through interlayer insulating film 180 and source/drain 150.In shape During into contact 190-1, oxide region 115 can serve as etching stopping layer.For example, source/drain 150 can To be etched until exposed oxide area 115.
Figure 34 is the block diagram of the electronic system for including the semiconductor devices according to several embodiments.
With reference to Figure 34, according to the electronic system 1100 of exemplary implementations can include controller 1110, Input/output (I/O) device 1120, memory device 1130, interface 1140 and bus 1150.Control Device 1110, I/O devices 1120, memory device 1130 and/or interface 1140 can via bus 1150 that This connection.The path that bus 1150 is transmitted corresponding to data by it.
Controller 1110 can include at least one of the following：Microprocessor, digital signal processor, Microcontroller and it is able to carry out the logical device of the function similar to the above.I/O devices 1120 May include keypad, keyboard or display device.Memory device 1130 can be with data storage and/or order.Connect Mouth 1140 can be performed and transmit data to communication network or the function from communication network receiving data.Interface 1140 can be wired or wireless.For example, interface 1140 may include antenna or wire/wireless transmitting-receiving Device.Although it is not shown, electronic system 1100 can comprise additionally in the operation for being configured to improve controller 1110 Operation memory, such as high speed dram (DRAM) and/or static random-access Memory (SRAM).According to exemplary implementations, according to the semiconductor device of exemplary implementations manufacture Part may be provided in memory device 1130, or be provided as controller 1110 or I/O devices 1120 A part.
Electronic system 1100 may be used on personal digital assistant (PDA) portable computer, online and put down Plate, radio telephone, mobile phone, digital music player, storage card or can be in the wireless context Transmission and/or nearly all electronic product of receiving data.
Figure 35 and 36 illustrates the Exemplary semiconductor system including the semiconductor devices according to exemplary implementations System.Figure 35 illustrates tablet PC, and Figure 36 illustrates laptop computer.According to the half of exemplary implementations Conductor device can be used in tablet PC or laptop computer.According to the semiconductor of exemplary implementations Device may apply to the IC-components being not shown here.
Although present inventive concept has been shown and described by reference to the exemplary implementations of present inventive concept, so And for the ordinary skill in the art it is evident that without departing from being defined by claim In the case of the spirit and scope of inventive concept, the different changes in form and details can be made to it.

Claims (20)

1. a kind of semiconductor devices, including：
Fin pattern, the first oxide region being included in the top of the fin pattern and the second oxide Area, wherein the fin pattern extends in a first direction；
First nano wire, extends in said first direction and opens with the fin pattern spacing；
Gate electrode, prolongs around first nano wire and in the second direction for intersecting the first direction Stretch, wherein the gate electrode is arranged on a region of the fin pattern, wherein the region is located at institute State between the first oxide region and second oxide region；With
First source/drain, be arranged on first oxide region and with the end part of first nano wire Connection.
2. semiconductor devices as claimed in claim 1, also includes：
Second nano wire, is arranged on first nano wire and extends in said first direction,
Wherein described first nano wire is plugged on the area of second nano wire and the fin pattern Between domain, and
Wherein described gate electrode surrounds second nano wire.
3. semiconductor devices as claimed in claim 1, also includes：
Gate spacer, is formed on the side wall of the gate electrode,
Wherein described first oxide region includes：
The firstth area overlapped with the source/drain；With
The secondth area overlapped with the gate spacer.
4. semiconductor devices as claimed in claim 3,
Wherein described firstth area is thicker than secondth area.
5. semiconductor devices as claimed in claim 3,
Wherein described first oxide region also includes：
With the 3rd area of the gate electrode crossover,
Wherein described secondth area is thicker than the 3rd area.
6. semiconductor devices as claimed in claim 1, also includes：
The interlayer insulating film being arranged in first source/drain；With
First source/drain contact with the interlayer insulating film is arranged on,
Lower surface of the basal surface of wherein described contact less than first nano wire.
7. semiconductor devices as claimed in claim 6,
Wherein described contact and first oxide region directly contact.
8. semiconductor devices as claimed in claim 7,
The whole lower surface of wherein described contact is contacted with first oxide region.
9. semiconductor devices as claimed in claim 6, also includes：
The second nano wire being arranged on first nano wire, wherein first nano wire is plugged on institute State between the region of the second nano wire and the fin pattern, wherein second nano wire is described First party is upwardly extended, wherein the gate electrode surrounds second nano wire, and
The distance between wherein described contact and first nano wire are substantially equal to described contact and described The distance between second nano wire.
10. semiconductor devices as claimed in claim 1,
Wherein described first source/drain is overlapping with first oxide region.
11. semiconductor devices as claimed in claim 10,
Wherein described first source/drain is overlapped completely with first oxide region.
12. semiconductor devices as claimed in claim 10,
Wherein described first source/drain includes：
Firstth area different from each other and the secondth area, secondth area is located at firstth area and the gate electrode Between；
First oxide region overlaps with secondth area and does not overlap with firstth area.
A kind of 13. semiconductor devices, including：
Substrate with oxide region；
First nano wire and the second nano wire, are spaced apart with the substrate, extend in a first direction, and It is spaced apart from each other in said first direction；
First gate electrode, around first nano wire and in the second direction for intersecting the first direction Extend；
Second gate electrode, extends around second nano wire and in this second direction；
First gate spacer and the second gate spacer, are separately positioned on side wall and the institute of the first gate electrode State on the side wall of the second gate electrode；
The groove being arranged between the first gate electrode and second gate electrode, wherein the groove by The oxide region of first gate spacer and the second gate spacer and the substrate limits, wherein The oxide region limits the basal surface of the groove and does not overlap at least part of first gate electrode With the second gate electrode；And
Source/drain, is arranged on the oxide region and fills the groove.
14. semiconductor devices as claimed in claim 13,
Wherein described oxide region overlaps completely the source/drain.
15. semiconductor devices as claimed in claim 13
The lower surface and described second of the upper surface of wherein described oxide region and first gate spacer At least one of lower surface of gate spacer is contacted.
16. semiconductor devices as claimed in claim 13,
Wherein described oxide region includes the firstth area, the secondth area and the 3rd area,
Adjacent to first gate spacer, the 3rd area is adjacent between the second gate in wherein described firstth area Parting, secondth area is arranged between firstth area and the 3rd area, and
Wherein described secondth area is thicker than firstth area and the 3rd area.
A kind of 17. semiconductor devices, including：
Substrate；
First nano wire, is spaced apart with the substrate and extends in a first direction；
Gate electrode, prolongs around first nano wire and in the second direction intersected with the first direction Stretch；And
Source/drain, is arranged at least side of the gate electrode and is connected with first nano wire；
Contact, be formed in the source/drain and in said first direction with first nano wire friendship It is folded；And
Etching stopping layer, is plugged between the contact and the substrate.
18. semiconductor devices as claimed in claim 17,
Wherein described etching stopping layer includes oxide skin(coating).
19. semiconductor devices as claimed in claim 18,
Wherein described etching stopping layer is contacted with the lower surface of the source/drain.
20. semiconductor devices as claimed in claim 19
Wherein described etching stopping layer includes：
The firstth area contacted with the lower surface of the contact；And
The secondth area contacted with the lower surface of the source/drain,
Wherein described firstth area is thicker than secondth area.
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